添加一些关于midi播放的项目
This commit is contained in:
terryLP
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/******************************************************************************
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* @brief provide generic high-level routines for ARM Cortex M0/M0+ processors.
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*
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*******************************************************************************/
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#include "common.h"
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/***********************************************************************/
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/*
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* Configures the ARM system control register for STOP (deep sleep) mode
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* and then executes the WFI instruction to enter the mode.
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*
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* Parameters:
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* none
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*
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* Note: Might want to change this later to allow for passing in a parameter
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* to optionally set the sleep on exit bit.
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*/
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void stop (void)
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{
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/* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */
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SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
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/* WFI instruction will start entry into STOP mode */
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#ifndef KEIL
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// If not using KEIL's uVision use the standard assembly command
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asm("WFI");
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#else
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// If using KEIL's uVision, use the CMSIS intrinsic
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__wfi();
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#endif
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}
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/***********************************************************************/
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/*
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* Configures the ARM system control register for WAIT (sleep) mode
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* and then executes the WFI instruction to enter the mode.
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*
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* Parameters:
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* none
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*
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* Note: Might want to change this later to allow for passing in a parameter
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* to optionally set the sleep on exit bit.
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*/
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void wait (void)
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{
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/* Clear the SLEEPDEEP bit to make sure we go into WAIT (sleep) mode instead
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* of deep sleep.
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*/
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SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
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/* WFI instruction will start entry into WAIT mode */
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#ifndef KEIL
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// If not using KEIL's uVision use the standard assembly command
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asm("WFI");
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#else
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// If using KEIL's uVision, use the CMSIS intrinsic
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__wfi();
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#endif
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}
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/***********************************************************************/
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/*
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* Change the value of the vector table offset register to the specified value.
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*
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* Parameters:
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* vtor new value to write to the VTOR
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*/
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void write_vtor (int vtor)
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{
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/* Write the VTOR with the new value */
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SCB->VTOR = vtor;
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}
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/***********************************************************************/
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@@ -0,0 +1,100 @@
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/******************************************************************************
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*
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* @brief provide generic high-level routines for ARM Cortex M0/M0+ processors.
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*
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*******************************************************************************/
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#ifndef _CPU_ARM_CM0_H
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#define _CPU_ARM_CM0_H
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/*ARM Cortex M0 implementation for interrupt priority shift*/
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#define ARM_INTERRUPT_LEVEL_BITS 2
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/***********************************************************************/
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/*!< Macro to enable all interrupts. */
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#ifndef KEIL
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#define EnableInterrupts __set_PRIMASK(0) //Modify
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#else
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#define EnableInterrupts __set_PRIMASK(0)
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#endif
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/*!< Macro to disable all interrupts. */
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#ifndef KEIL
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#define DisableInterrupts __set_PRIMASK(1)
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#else
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#define DisableInterrupts __set_PRIMASK(1)
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#endif
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#define disable_irq(irq) NVIC_DisableIRQ(irq)
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#define enable_irq(irq) NVIC_EnableIRQ(irq)
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#define set_irq_priority(irq, prio) NVIC_SetPriority(irq, prio)
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/***********************************************************************/
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/*
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* Misc. Defines
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*/
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#ifdef FALSE
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#undef FALSE
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#endif
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#define FALSE (0)
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#ifdef TRUE
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#undef TRUE
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#endif
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#define TRUE (1)
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#ifdef NULL
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#undef NULL
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#endif
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#define NULL (0)
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#ifdef ON
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#undef ON
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#endif
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#define ON (1)
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#ifdef OFF
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#undef OFF
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#endif
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#define OFF (0)
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#undef ENABLE
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#define ENABLE (1)
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#undef DISABLE
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#define DISABLE (0)
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/***********************************************************************/
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/*
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* The basic data types
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*/
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typedef unsigned char uint8; /* 8 bits */
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typedef unsigned short int uint16; /* 16 bits */
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typedef unsigned long int uint32; /* 32 bits */
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typedef char int8; /* 8 bits */
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typedef short int int16; /* 16 bits */
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typedef int int32; /* 32 bits */
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typedef volatile int8 vint8; /* 8 bits */
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typedef volatile int16 vint16; /* 16 bits */
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typedef volatile int32 vint32; /* 32 bits */
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typedef volatile uint8 vuint8; /* 8 bits */
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typedef volatile uint16 vuint16; /* 16 bits */
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typedef volatile uint32 vuint32; /* 32 bits */
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// function prototype for main function
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int main(void);
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/***********************************************************************/
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// function prototypes for arm_cm0.c
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void stop (void);
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void wait (void);
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void write_vtor (int);
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/***********************************************************************/
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#endif /* _CPU_ARM_CM4_H */
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,8 @@
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/*
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* Note: This file is recreated by the project wizard whenever the MCU is
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* changed and should not be edited by hand
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*/
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/* Include the derivative-specific header file */
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#include <NV32.h>
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#include "arm_cm0.h"
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@@ -0,0 +1,65 @@
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/******************************************************************************
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* @brief provide high-level startup routines for NV32Fxx.
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*
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*******************************************************************************/
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#include "start.h"
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#include "common.h"
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#include "wdog.h"
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#include "sysinit.h"
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void start(void);
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void SystemInit( void );
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/********************************************************************/
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/*!
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* \brief Start
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* \return None
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*
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* This function calls all of the needed starup routines and then
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* branches to the main process.
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*/
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void start(void)
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{
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/* Disable the watchdog ETMer but enable update */
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WDOG_DisableWDOGEnableUpdate();
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#ifndef __GNUC__
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#ifndef KEIL
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/* Copy any vector or data sections that need to be in RAM */
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common_startup();
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#endif
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#endif
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/* Jump to main process */
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main();
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/* No actions to perform after this so wait forever */
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while(1);
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}
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/********************************************************************/
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/********************************************************************/
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/*!
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* \brief flash SystemInit
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* \return None
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*
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* this is a system initialization function which dediu16Cated in Keil
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* others complier don't use it.
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* it is similar to start function
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*/
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void SystemInit( void )
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{
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#if !defined(ENABLE_WDOG)
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/* Disable the watchdog ETMer */
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WDOG_Disable();
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#else
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/* Disable the watchdog ETMer but enable update */
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WDOG_DisableWDOGEnableUpdate();
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#endif
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}
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@@ -0,0 +1,7 @@
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/******************************************************************************
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* @brief provide high-level startup routines for NV32Fxx.
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*
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*******************************************************************************/
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/* Function prototypes */
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void start(void);
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@@ -0,0 +1,88 @@
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.syntax unified
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.arch armv6-m
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr r0, =_estack
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mov sp, r0 /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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movs r1, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r3, =_sidata
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ldr r3, [r3, r1]
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str r3, [r0, r1]
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adds r1, r1, #4
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LoopCopyDataInit:
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ldr r0, =_sdata
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ldr r3, =_edata
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adds r2, r0, r1
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cmp r2, r3
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bcc CopyDataInit
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ldr r2, =_sbss
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b LoopFillZerobss
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/* Zero fill the bss segment. */
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FillZerobss:
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movs r3, #0
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str r3, [r2]
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adds r2, r2, #4
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LoopFillZerobss:
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ldr r3, = _ebss
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cmp r2, r3
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call the application's entry point.*/
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bl main
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LoopForever:
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b LoopForever
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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*
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* @param None
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* @retval : None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/* Vectors and flash protection config in vectors.c */
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@@ -0,0 +1,348 @@
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;/*****************************************************************************
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; * @file: startup_NV32.s
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; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
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; * NV32F100
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;*
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; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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; *
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; *****************************************************************************/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD Reserved16_IRQHandler ; Reserved interrupt 16
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DCD Reserved17_IRQHandler ; Reserved interrupt 17
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DCD Reserved18_IRQHandler ; Reserved interrupt 18
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DCD Reserved19_IRQHandler ; Reserved interrupt 19
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DCD Reserved20_IRQHandler ; Reserved interrupt 20
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DCD ETMRH_IRQHandler ; ETMRH command complete/read collision interrupt
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DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
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DCD IRQ_IRQHandler ; External interrupt
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DCD I2C0_IRQHandler ; I2C0 interrupt
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DCD Reserved25_IRQHandler ; Reserved interrupt 25
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DCD SPI0_IRQHandler ; SPI0 interrupt
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DCD SPI1_IRQHandler ; SPI1 interrupt
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DCD UART0_IRQHandler ; UART0 status/error interrupt
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DCD UART1_IRQHandler ; UART1 status/error interrupt
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DCD UART2_IRQHandler ; UART2 status/error interrupt
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DCD ADC0_IRQHandler ; ADC0 interrupt
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DCD ACMP0_IRQHandler ; ACMP0 interrupt
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DCD ETM0_IRQHandler ; ETM0 Single interrupt vector for all sources
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DCD ETM1_IRQHandler ; ETM1 Single interrupt vector for all sources
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DCD ETM2_IRQHandler ; ETM2 Single interrupt vector for all sources
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DCD RTC_IRQHandler ; RTC overflow
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DCD ACMP1_IRQHandler ; ACMP1 interrupt
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DCD PIT_CH0_IRQHandler ; PIT CH0 overflow
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DCD PIT_CH1_IRQHandler ; PIT CH1 overflow
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DCD KBI0_IRQHandler ; Keyboard interrupt 0
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DCD KBI1_IRQHandler ; Keyboard interrupt 1
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DCD Reserved42_IRQHandler ; Reserved interrupt 42
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DCD ICS_IRQHandler ; MCG interrupt
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DCD Watchdog_IRQHandler ; WDOG Interrupt
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DCD Reserved45_IRQHandler ; Reserved interrupt 45
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DCD Reserved46_IRQHandler ; Reserved interrupt 46
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DCD Reserved47_IRQHandler ; Reserved interrupt 47
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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; <h> Flash Configuration
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; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
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; <i> and security information that allows the MCU to restrict acces to the FTFL module.
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; <h> Backdoor Comparison Key
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; <o0> Backdoor Key 0 <0x0-0xFF:2>
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; <o1> Backdoor Key 1 <0x0-0xFF:2>
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; <o2> Backdoor Key 2 <0x0-0xFF:2>
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; <o3> Backdoor Key 3 <0x0-0xFF:2>
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; <o4> Backdoor Key 4 <0x0-0xFF:2>
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; <o5> Backdoor Key 5 <0x0-0xFF:2>
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; <o6> Backdoor Key 6 <0x0-0xFF:2>
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; <o7> Backdoor Key 7 <0x0-0xFF:2>
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BackDoorK0 EQU 0xFF
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BackDoorK1 EQU 0xFF
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BackDoorK2 EQU 0xFF
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BackDoorK3 EQU 0xFF
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BackDoorK4 EQU 0xFF
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BackDoorK5 EQU 0xFF
|
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BackDoorK6 EQU 0xFF
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BackDoorK7 EQU 0xFF
|
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; </h>
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; <h> EEPROM Protection Register (EEPROT)
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; <i> The DFPROT register defines which D-Flash sectors are protected against program and erase operations.
|
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; <o.7> DPOPEN
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; <0=> Enables EEPROM memory protection
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; <1=> Disables EEPROM memory protection
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; <o.0..2> DPS
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; <0=> Flash address range: 0x00_0000 - 0x00_001F; protected size: 32 bytes
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; <1=> Flash address range: 0x00_0000 - 0x00_003F; protected size: 64 bytes
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; <2=> Flash address range: 0x00_0000 - 0x00_005F; protected size: 96 bytes
|
||||
; <3=> Flash address range: 0x00_0000 - 0x00_007F; protected size: 128 bytes
|
||||
; <4=> Flash address range: 0x00_0000 - 0x00_009F; protected size: 160 bytes
|
||||
; <5=> Flash address range: 0x00_0000 - 0x00_00BF; protected size: 192 bytes
|
||||
; <6=> Flash address range: 0x00_0000 - 0x00_00DF; protected size: 224 bytes
|
||||
; <7=> Flash address range: 0x00_0000 - 0x00_00FF; protected size: 256 bytes
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EEPROT EQU 0xFF
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; </h>
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; <h> FPROT
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; <i> P-Flash Protection Register
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; <o.7> FPOPEN
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; <0=> FPHDIS and FPLDIS bits define unprotected address ranges as specified by the corresponding FPHS and FPLS bits FPROT1.1
|
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; <1=> FPHDIS and FPLDIS bits enable protection for the address range specified by the corresponding FPHS and FPLS bits
|
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; <o.5> FPHDIS
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; <0=> Protection/Unprotection enabled
|
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; <1=> Protection/Unprotection disabled
|
||||
; <o.3..4> FPHS
|
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; <0=> Address range: 0x00_7C00-0x00_7FFF; protected size: 1 KB
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||||
; <1=> Address range: 0x00_7800-0x00_7FFF; protected size: 2 KB
|
||||
; <2=> Address range: 0x00_7000-0x00_7FFF; protected size: 4 KB
|
||||
; <3=> Address range: 0x00_6000-0x00_7FFF; protected size: 8 KB
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||||
; <o.5> FPLDIS
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; <0=> Protection/Unprotection enabled
|
||||
; <1=> Protection/Unprotection disabled
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||||
; <o.3..4> FPLS
|
||||
; <0=> Address range: 0x00_0000-0x00_07FF; protected size: 2 KB
|
||||
; <1=> Address range: 0x00_0000-0x00_0FFF; protected size: 4 KB
|
||||
; <2=> Address range: 0x00_0000-0x00_1FFF; protected size: 8 KB
|
||||
; <3=> Address range: 0x00_0000-0x00_3FFF; protected size: 16 KB
|
||||
FPROT EQU 0xFF
|
||||
; </h>
|
||||
; </h>
|
||||
; <h> Flash security byte (FSEC)
|
||||
; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
|
||||
; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
|
||||
; <o.0..1> SEC
|
||||
; <2=> MCU security status is unsecure
|
||||
; <3=> MCU security status is secure
|
||||
; <i> Flash Security
|
||||
; <i> This bits define the security state of the MCU.
|
||||
; <o.6..7> KEYEN
|
||||
; <2=> Backdoor key access enabled
|
||||
; <3=> Backdoor key access disabled
|
||||
; <i> Backdoor key Security Enable
|
||||
; <i> These bits enable and disable backdoor key access to the FTFL module.
|
||||
FSEC EQU 0xFE
|
||||
; </h>
|
||||
; <h> Flash Option Register (FOPT)
|
||||
FOPT EQU 0xFE
|
||||
; </h>
|
||||
IF :LNOT::DEF:RAM_TARGET
|
||||
AREA |.ARM.__at_0x400|, CODE, READONLY
|
||||
DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
|
||||
DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
|
||||
DCB 0xFF, 0xFF, 0xFF, 0xFF
|
||||
DCB EEPROT, FPROT, FSEC, FOPT ;Modified by ARM. DCB FPROT, EEPROT, FOPT, FSEC
|
||||
ENDIF
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT Reserved16_IRQHandler [WEAK]
|
||||
EXPORT Reserved17_IRQHandler [WEAK]
|
||||
EXPORT Reserved18_IRQHandler [WEAK]
|
||||
EXPORT Reserved19_IRQHandler [WEAK]
|
||||
EXPORT Reserved20_IRQHandler [WEAK]
|
||||
EXPORT ETMRH_IRQHandler [WEAK]
|
||||
EXPORT LVD_LVW_IRQHandler [WEAK]
|
||||
EXPORT IRQ_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT Reserved25_IRQHandler [WEAK]
|
||||
EXPORT SPI0_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT UART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT UART2_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT ACMP0_IRQHandler [WEAK]
|
||||
EXPORT ETM0_IRQHandler [WEAK]
|
||||
EXPORT ETM1_IRQHandler [WEAK]
|
||||
EXPORT ETM2_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT ACMP1_IRQHandler [WEAK]
|
||||
EXPORT PIT_CH0_IRQHandler [WEAK]
|
||||
EXPORT PIT_CH1_IRQHandler [WEAK]
|
||||
EXPORT KBI0_IRQHandler [WEAK]
|
||||
EXPORT KBI1_IRQHandler [WEAK]
|
||||
EXPORT Reserved42_IRQHandler [WEAK]
|
||||
EXPORT ICS_IRQHandler [WEAK]
|
||||
EXPORT Watchdog_IRQHandler [WEAK]
|
||||
EXPORT Reserved45_IRQHandler [WEAK]
|
||||
EXPORT Reserved46_IRQHandler [WEAK]
|
||||
EXPORT Reserved47_IRQHandler [WEAK]
|
||||
EXPORT DefaultISR [WEAK]
|
||||
|
||||
Reserved16_IRQHandler
|
||||
Reserved17_IRQHandler
|
||||
Reserved18_IRQHandler
|
||||
Reserved19_IRQHandler
|
||||
Reserved20_IRQHandler
|
||||
ETMRH_IRQHandler
|
||||
LVD_LVW_IRQHandler
|
||||
IRQ_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
Reserved25_IRQHandler
|
||||
SPI0_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
UART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
UART2_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
ACMP0_IRQHandler
|
||||
ETM0_IRQHandler
|
||||
ETM1_IRQHandler
|
||||
ETM2_IRQHandler
|
||||
RTC_IRQHandler
|
||||
ACMP1_IRQHandler
|
||||
PIT_CH0_IRQHandler
|
||||
PIT_CH1_IRQHandler
|
||||
KBI0_IRQHandler
|
||||
KBI1_IRQHandler
|
||||
Reserved42_IRQHandler
|
||||
ICS_IRQHandler
|
||||
Watchdog_IRQHandler
|
||||
Reserved45_IRQHandler
|
||||
Reserved46_IRQHandler
|
||||
Reserved47_IRQHandler
|
||||
DefaultISR
|
||||
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
|
||||
ALIGN
|
||||
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
@@ -0,0 +1,257 @@
|
||||
/*****************************************************************************
|
||||
* @brief provide system init routine/configuration for NV32Fxx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include "common.h"
|
||||
#include "sysinit.h"
|
||||
#include "sim.h"
|
||||
#include "uart.h"
|
||||
#include "ics.h"
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
uint16_t global_pass_count = 0;
|
||||
uint16_t global_fail_count = 0;
|
||||
|
||||
|
||||
void print_sys_log(void);
|
||||
void UART_InitPrint(void);
|
||||
|
||||
/*****************************************************************************//*!
|
||||
+FUNCTION----------------------------------------------------------------
|
||||
* @function name: sysinit
|
||||
*
|
||||
* @brief initalize system including SIM, ICS, UART, etc
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return none
|
||||
*
|
||||
* @ Pass/ Fail criteria: none
|
||||
*****************************************************************************/
|
||||
void sysinit (void)
|
||||
{
|
||||
SIM_ConfigType sSIMConfig = {{0},0};
|
||||
ICS_ConfigType sICSConfig = {0};
|
||||
|
||||
/* initialize the Pass/Fail counts to 0 */
|
||||
global_pass_count = 0;
|
||||
global_fail_count = 0;
|
||||
|
||||
EFMCR &=0xFFFF0001; // set wait state 1
|
||||
|
||||
#if defined(TRIM_IRC)
|
||||
/* if not trimmed, do trim first */
|
||||
ICS_Trim(ICS_TRIM_VALUE);
|
||||
#endif
|
||||
/*
|
||||
* Enable SWD pin, RESET pin
|
||||
*/
|
||||
/*
|
||||
* NOTE: please make sure other register bits are also write-once and
|
||||
* need add other bit mask here if needed.
|
||||
*/
|
||||
#if defined(SPI0_PINREMAP)
|
||||
sSIMConfig.u32PinSel |= SIM_PINSEL_SPI0PS_MASK;
|
||||
#endif
|
||||
|
||||
#if defined(OUTPUT_BUSCLK)
|
||||
sSIMConfig.sBits.bEnableCLKOUT = 1; /* output bus clock if enabled */
|
||||
#endif
|
||||
|
||||
#if defined(DISABLE_NMI)
|
||||
sSIMConfig.sBits.bDisableNMI = 1;
|
||||
#endif
|
||||
|
||||
/* make sure clocks to peripheral modules are enabled */
|
||||
sSIMConfig.u32SCGC |= SIM_SCGC_SWD_MASK | SIM_SCGC_FLASH_MASK |
|
||||
SIM_SCGC_UART0_MASK | SIM_SCGC_UART1_MASK |
|
||||
SIM_SCGC_UART2_MASK;
|
||||
|
||||
sSIMConfig.sBits.bBusDiv |= BUSDIV_ENCODE;
|
||||
|
||||
|
||||
SIM_Init(&sSIMConfig); /* initialize SIM */
|
||||
|
||||
#if defined(XOSC_STOP_ENABLE)
|
||||
sICSConfig.oscConfig.bStopEnable = 1; /* enabled in stop mode */
|
||||
#endif
|
||||
|
||||
#if defined(CRYST_HIGH_GAIN)
|
||||
sICSConfig.oscConfig.bGain = 1; /* high gain */
|
||||
#endif
|
||||
|
||||
|
||||
#if (EXT_CLK_FREQ_KHZ >=4000)
|
||||
sICSConfig.oscConfig.bRange = 1; /* high range */
|
||||
#endif
|
||||
|
||||
sICSConfig.oscConfig.bEnable = 1; /* enable OSC */
|
||||
sICSConfig.u32ClkFreq = EXT_CLK_FREQ_KHZ;
|
||||
|
||||
#if defined(USE_FEE)
|
||||
sICSConfig.u8ClkMode = ICS_CLK_MODE_FEE;
|
||||
#elif defined(USE_FBE_OSC)
|
||||
sICSConfig.u8ClkMode = ICS_CLK_MODE_FBE_OSC;
|
||||
#elif defined(USE_FEE_OSC)
|
||||
sICSConfig.u8ClkMode = ICS_CLK_MODE_FEE_OSC;
|
||||
#elif defined(USE_FBILP)
|
||||
sICSConfig.u8ClkMode = ICS_CLK_MODE_FBILP;
|
||||
#elif defined(USE_FBELP)
|
||||
sICSConfig.u8ClkMode = ICS_CLK_MODE_FBELP;
|
||||
#endif
|
||||
|
||||
ICS_Init(&sICSConfig); /* initialize ICS */
|
||||
|
||||
/* initialize UART for printing */
|
||||
//UART_InitPrint();
|
||||
|
||||
#if defined(PRINT_SYS_LOG)
|
||||
//print_sys_log();
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/*****************************************************************************//*!
|
||||
+FUNCTION----------------------------------------------------------------
|
||||
* @function name: print_sys_log
|
||||
*
|
||||
* @brief print system reset sources
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return none
|
||||
*
|
||||
* @ Pass/ Fail criteria: none
|
||||
*****************************************************************************/
|
||||
void print_sys_log(void)
|
||||
{
|
||||
uint8_t u8Rst = 0;
|
||||
uint8_t u8FamID,u8SubFamID,u8RevID,u8PinID;
|
||||
uint32_t u32Status;
|
||||
|
||||
u32Status = SIM_GetStatus(0xFF); /* get all status bits */
|
||||
|
||||
/* get all IDs */
|
||||
u8FamID = SIM_ReadID(ID_TYPE_FAMID);
|
||||
u8SubFamID = SIM_ReadID(ID_TYPE_SUBFAMID);
|
||||
u8RevID = SIM_ReadID(ID_TYPE_REVID);
|
||||
u8PinID = SIM_ReadID(ID_TYPE_PINID);
|
||||
|
||||
printf("\n\n--System Log BEGINS--\n\n");
|
||||
printf("\n Familly ID = 0x%x, Sub-family ID = 0x%x, Revision ID = 0x%x, Pin ID = 0x%x \n",
|
||||
u8FamID, u8SubFamID, u8RevID, u8PinID);
|
||||
|
||||
if((u32Status & SIM_SRSID_POR_MASK) && (u32Status & SIM_SRSID_LVD_MASK))
|
||||
{
|
||||
u8Rst = 1;
|
||||
printf(" Power On Reset\n");
|
||||
}
|
||||
|
||||
if(!(u32Status & SIM_SRSID_POR_MASK) && (u32Status & SIM_SRSID_LVD_MASK))
|
||||
{
|
||||
u8Rst = 1;
|
||||
printf(" LVD Reset\n");
|
||||
}
|
||||
|
||||
if(u32Status & SIM_SRSID_WDOG_MASK)
|
||||
{
|
||||
u8Rst = 1;
|
||||
printf(" WDOG Reset\n");
|
||||
}
|
||||
|
||||
|
||||
if(u32Status & SIM_SRSID_PIN_MASK)
|
||||
{
|
||||
u8Rst = 1;
|
||||
printf(" Pin Reset\n");
|
||||
}
|
||||
if(u32Status & SIM_SRSID_LOC_MASK)
|
||||
{
|
||||
u8Rst = 1;
|
||||
printf(" Loss of Clock Reset\n");
|
||||
}
|
||||
if(u32Status & SIM_SRSID_SACKERR_MASK)
|
||||
{
|
||||
u8Rst = 1;
|
||||
printf(" Stop Mode Acknowledge Error Reset\n");
|
||||
}
|
||||
if(u32Status & SIM_SRSID_MDMAP_MASK)
|
||||
{
|
||||
u8Rst = 1;
|
||||
printf(" MDM-AP System Reset Request\n");
|
||||
}
|
||||
if(u32Status & SIM_SRSID_SW_MASK)
|
||||
{
|
||||
u8Rst = 1;
|
||||
printf(" Software/SYSRESETREQ Reset\n");
|
||||
}
|
||||
if(u32Status & SIM_SRSID_LOCKUP_MASK)
|
||||
{
|
||||
u8Rst = 1;
|
||||
printf(" Core lockup Reset\n");
|
||||
}
|
||||
|
||||
if(u8Rst != 1)
|
||||
{
|
||||
printf("SWD Reset\n");
|
||||
}
|
||||
|
||||
printf("\n--System Log ENDS--\n\n");
|
||||
}
|
||||
|
||||
|
||||
/*****************************************************************************//*!
|
||||
+FUNCTION----------------------------------------------------------------
|
||||
* @function name: end_test
|
||||
*
|
||||
* @brief print test result (pass/fail counts) after end of test
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return none
|
||||
*
|
||||
* @ Pass/ Fail criteria: none
|
||||
*****************************************************************************/
|
||||
|
||||
void end_test(void)
|
||||
{
|
||||
|
||||
if(global_fail_count==0){
|
||||
printf("\n global_pass_count = 0x%02x%02x",(uint8)(global_pass_count>>8),(uint8)global_pass_count);
|
||||
printf("\n\n TEST PASSED");
|
||||
} else{
|
||||
printf("\n global_pass_count = 0x%02x%02x",(uint8)(global_pass_count>>8),(uint8)global_pass_count);
|
||||
printf("\n global_fail_count = 0x%02x%02x",(uint8)(global_fail_count>>8),(uint8)global_fail_count);
|
||||
printf("\n\n TEST FAILED");
|
||||
}
|
||||
|
||||
printf("\n\n TEST FINISHED");
|
||||
|
||||
}
|
||||
|
||||
/*****************************************************************************//*!
|
||||
+FUNCTION----------------------------------------------------------------
|
||||
* @function name: UART_InitPrint
|
||||
*
|
||||
* @brief initialize UART for print on port defined by TERM_PORT.
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return none
|
||||
*
|
||||
* @ Pass/ Fail criteria: none
|
||||
*****************************************************************************/
|
||||
|
||||
void UART_InitPrint(void)
|
||||
{
|
||||
UART_ConfigType sConfig;
|
||||
|
||||
sConfig.u32SysClkHz = BUS_CLK_HZ;
|
||||
sConfig.u32Baudrate = UART_PRINT_BITRATE;
|
||||
|
||||
SIM_RemapUART0Pin();
|
||||
|
||||
UART_Init (TERM_PORT, &sConfig);
|
||||
}
|
||||
@@ -0,0 +1,38 @@
|
||||
/******************************************************************************
|
||||
* @brief provide system init routine/configuration for KExx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#ifndef SYSINIT_H_
|
||||
#define SYSINIT_H_
|
||||
|
||||
/******************************************************************************
|
||||
* Includes
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
* Constants
|
||||
******************************************************************************/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Macros
|
||||
******************************************************************************/
|
||||
#define SIM_SCGC_VALUE 0x00003000L
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* Global variables
|
||||
******************************************************************************/
|
||||
|
||||
/******************************************************************************
|
||||
* Global functions
|
||||
******************************************************************************/
|
||||
void sysinit (void);
|
||||
void enable_abort_button(void);
|
||||
void end_test(void);
|
||||
|
||||
/********************************************************************/
|
||||
#endif /* SYSINIT_H_ */
|
||||
@@ -0,0 +1,51 @@
|
||||
/*
|
||||
** ###################################################################
|
||||
*
|
||||
* Provides a system configuration function and a global variable that contains
|
||||
* the system frequency. It configures the device and initializes the oscillator
|
||||
* (PLL) that is part of the microcontroller device.
|
||||
*/
|
||||
|
||||
#ifndef SYSTEM_MKE02Z2_H_
|
||||
#define SYSTEM_MKE02Z2_H_ /**< Symbol preventing repeated inclusion */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/**
|
||||
* @brief System clock frequency (core clock)
|
||||
*
|
||||
* The system clock frequency supplied to the SysTick timer and the processor
|
||||
* core clock. This variable can be used by the user application to setup the
|
||||
* SysTick timer or configure other parameters. It may also be used by debugger to
|
||||
* query the frequency of the debug timer or configure the trace clock speed
|
||||
* SystemCoreClock is initialized with a correct predefined value.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
*
|
||||
* Typically this function configures the oscillator (PLL) that is part of the
|
||||
* microcontroller device. For systems with variable clock speed it also updates
|
||||
* the variable SystemCoreClock. SystemInit is called from startup_device file.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
/**
|
||||
* @brief Updates the SystemCoreClock variable.
|
||||
*
|
||||
* It must be called whenever the core clock is changed during program
|
||||
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
|
||||
* the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* #if !defined(SYSTEM_MKE02Z2_H_) */
|
||||
@@ -0,0 +1,89 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* @brief provide systick utility routines.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include "common.h"
|
||||
#include "systick.h"
|
||||
//#include "stdint.h"
|
||||
uint32_t cnt_start_value;
|
||||
uint32_t cnt_end_value;
|
||||
uint32_t overhead;
|
||||
SysTick_CallbackType SysTick_Callback[1] = {NULL};
|
||||
#if 0
|
||||
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
#endif
|
||||
void systick_init(void)
|
||||
{
|
||||
|
||||
SysTick->VAL = 0x0; /* clear current ETMer value */
|
||||
SysTick->LOAD = 0x00FFFFFF;
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
void SysTick_SetCallBack(SysTick_CallbackType pSysTick_CallBack)
|
||||
{
|
||||
SysTick_Callback[0] = pSysTick_CallBack;
|
||||
}
|
||||
|
||||
/***
|
||||
void delay_us(int n)//微秒级别的延时
|
||||
{
|
||||
int temp;
|
||||
SysTick->LOAD= 48 *n; //????
|
||||
SysTick->VAL=0x00000000; //?????
|
||||
SysTick->CTRL=0x00000005;
|
||||
while(SysTick->CTRL&0x00010000); //????
|
||||
SysTick->CTRL=0x00000004;
|
||||
}
|
||||
***/
|
||||
|
||||
/****
|
||||
void delay_ms(int n)//毫秒级别的延时
|
||||
{
|
||||
int temp;
|
||||
SysTick->LOAD= 48000 *n; //????
|
||||
SysTick->VAL=0x00000000; //?????
|
||||
SysTick->CTRL=0x00000005;
|
||||
while(SysTick->CTRL&0x00010000); //????
|
||||
SysTick->CTRL=0x00000004;
|
||||
}******////
|
||||
|
||||
void systick_disable(void)
|
||||
{
|
||||
SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
void cal_systick_read_overhead(void)
|
||||
{
|
||||
uint32_t cnt_start_value;
|
||||
uint32_t cnt_end_value;
|
||||
|
||||
cnt_start_value = SysTick->VAL;
|
||||
|
||||
cnt_end_value = SysTick->VAL;
|
||||
|
||||
overhead = cnt_start_value - cnt_end_value;
|
||||
|
||||
#ifdef DEBUG_PRINT
|
||||
printf("systick start value: 0x%x\n\r", (unsigned int)cnt_start_value);
|
||||
printf("systick end value: 0x%x\n\r", (unsigned int) cnt_end_value);
|
||||
printf("systick current value read overhead: 0x%x\n\r", (unsigned int)overhead);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
void SysTick_Isr(void)
|
||||
{
|
||||
//printf("input any character to start a new conversion!\n");
|
||||
if( SysTick_Callback[0] )
|
||||
{
|
||||
SysTick_Callback[0]();
|
||||
}
|
||||
}
|
||||
|
||||
@@ -0,0 +1,25 @@
|
||||
/******************************************************************************
|
||||
* @brief provide systick utility routines.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#ifndef __SYSTICK_H
|
||||
#define __SYSTICK_H
|
||||
typedef void (*SysTick_CallbackType)(void);
|
||||
|
||||
#define SYS_COUNT_ETME 10 //ms
|
||||
#define SYS_COUNT MCU_CLCOK*SYS_COUNT_ETME/16
|
||||
/* Global variables */
|
||||
extern uint32_t cnt_start_value;
|
||||
extern uint32_t cnt_end_value;
|
||||
extern uint32_t overhead;
|
||||
void SysTick_SetCallBack(SysTick_CallbackType pSysTick_CallBack);
|
||||
|
||||
/* Function declaration */
|
||||
void systick_init(void);
|
||||
void systick_disable(void);
|
||||
void cal_systick_read_overhead(void);
|
||||
//void delay_us(int n);
|
||||
//void delay_ms(int n);
|
||||
void SysTick_SetCallBack(SysTick_CallbackType pSysTick_CallBack);
|
||||
#endif
|
||||
@@ -0,0 +1,171 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* @brief provide interrupt vector table for NV32Fxxx.
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
#include "vectors.h"
|
||||
#include "isr.h"
|
||||
#include "common.h"
|
||||
|
||||
/******************************************************************************
|
||||
* Vector Table
|
||||
******************************************************************************/
|
||||
typedef void (*vector_entry)(void);
|
||||
|
||||
#ifdef KEIL
|
||||
const vector_entry __vector_table[] __attribute__((at(0x00))) =
|
||||
#elif (defined(__GNUC__))
|
||||
//void (* const __vector_table[])() __attribute__ ((section(".vectortable"))) =
|
||||
void (* const InterruptVector[])() __attribute__ ((section(".isr_vector"))) =
|
||||
#else
|
||||
#pragma location = ".intvec"
|
||||
const vector_entry __vector_table[] = //@ ".intvec" =
|
||||
#endif
|
||||
{
|
||||
VECTOR_000, /* Initial SP */
|
||||
VECTOR_001, /* Initial PC */
|
||||
VECTOR_002,
|
||||
VECTOR_003,
|
||||
VECTOR_004,
|
||||
VECTOR_005,
|
||||
VECTOR_006,
|
||||
VECTOR_007,
|
||||
VECTOR_008,
|
||||
VECTOR_009,
|
||||
VECTOR_010,
|
||||
VECTOR_011,
|
||||
VECTOR_012,
|
||||
VECTOR_013,
|
||||
VECTOR_014,
|
||||
VECTOR_015,
|
||||
VECTOR_016,
|
||||
VECTOR_017,
|
||||
VECTOR_018,
|
||||
VECTOR_019,
|
||||
VECTOR_020,
|
||||
VECTOR_021,
|
||||
VECTOR_022,
|
||||
VECTOR_023,
|
||||
VECTOR_024,
|
||||
VECTOR_025,
|
||||
VECTOR_026,
|
||||
VECTOR_027,
|
||||
VECTOR_028,
|
||||
VECTOR_029,
|
||||
VECTOR_030,
|
||||
VECTOR_031,
|
||||
VECTOR_032,
|
||||
VECTOR_033,
|
||||
VECTOR_034,
|
||||
VECTOR_035,
|
||||
VECTOR_036,
|
||||
VECTOR_037,
|
||||
VECTOR_038,
|
||||
VECTOR_039,
|
||||
VECTOR_040,
|
||||
VECTOR_041,
|
||||
VECTOR_042,
|
||||
VECTOR_043,
|
||||
VECTOR_044,
|
||||
VECTOR_045,
|
||||
VECTOR_046,
|
||||
VECTOR_047 // END of real vector table
|
||||
};
|
||||
// VECTOR_TABLE end
|
||||
#ifndef KEIL
|
||||
#ifndef USE_BOOTLOADER
|
||||
#ifdef KEIL
|
||||
const uint32_t __flash_config[] __attribute__((at(0x400))) =
|
||||
#elif (defined(__GNUC__))
|
||||
const uint32_t __flash_config[] __attribute__ ((section(".nv32_flash_config_field"))) =
|
||||
#else
|
||||
#pragma location = 0x400
|
||||
__root const uint32_t __flash_config[] = //@ ".intvec" =
|
||||
#endif
|
||||
{
|
||||
CONFIG_1,
|
||||
CONFIG_2,
|
||||
CONFIG_3,
|
||||
CONFIG_4,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
/******************************************************************************
|
||||
* default_isr(void)
|
||||
*
|
||||
* Default ISR definition.
|
||||
*
|
||||
* In: n/a
|
||||
* Out: n/a
|
||||
******************************************************************************/
|
||||
void default_isr(void)
|
||||
{
|
||||
#define VECTORNUM (*(volatile uint32_t*)(0xE000ED04))
|
||||
|
||||
printf("\n****default_isr entered on vector %lu*****\r\n\n",VECTORNUM);
|
||||
return;
|
||||
}
|
||||
/******************************************************************************/
|
||||
/* Generic interrupt handler for a GPIO interrupt connected to an
|
||||
* abort switch.
|
||||
* NOTE: For true abort operation this handler should be modified
|
||||
* to jump to the main process instead of executing a return.
|
||||
*/
|
||||
void abort_isr(void)
|
||||
{
|
||||
//printf("\n****Abort button interrupt****\n\n");
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Exception frame without floating-point storage
|
||||
* hard fault handler in C,
|
||||
* with stack frame location as input parameter
|
||||
*/
|
||||
void
|
||||
hard_fault_handler_c(unsigned int * hardfault_args)
|
||||
{
|
||||
/*
|
||||
unsigned int stacked_r0;
|
||||
unsigned int stacked_r1;
|
||||
unsigned int stacked_r2;
|
||||
unsigned int stacked_r3;
|
||||
unsigned int stacked_r12;
|
||||
unsigned int stacked_lr;
|
||||
unsigned int stacked_pc;
|
||||
unsigned int stacked_psr;
|
||||
|
||||
//Exception stack frame
|
||||
stacked_r0 = ((unsigned long) hardfault_args[0]);
|
||||
stacked_r1 = ((unsigned long) hardfault_args[1]);
|
||||
stacked_r2 = ((unsigned long) hardfault_args[2]);
|
||||
stacked_r3 = ((unsigned long) hardfault_args[3]);
|
||||
|
||||
stacked_r12 = ((unsigned long) hardfault_args[4]);
|
||||
stacked_lr = ((unsigned long) hardfault_args[5]);
|
||||
stacked_pc = ((unsigned long) hardfault_args[6]);
|
||||
stacked_psr = ((unsigned long) hardfault_args[7]);
|
||||
|
||||
printf ("[Hard fault handler]\n");
|
||||
printf ("R0 = %x\n", stacked_r0);
|
||||
printf ("R1 = %x\n", stacked_r1);
|
||||
printf ("R2 = %x\n", stacked_r2);
|
||||
printf ("R3 = %x\n", stacked_r3);
|
||||
printf ("R12 = %x\n", stacked_r12);
|
||||
printf ("LR = %x\n", stacked_lr);
|
||||
printf ("PC = %x\n", stacked_pc);
|
||||
printf ("PSR = %x\n", stacked_psr);
|
||||
printf ("BFAR = %x\n", (*((volatile unsigned long *)(0xE000ED38))));
|
||||
printf ("CFSR = %x\n", (*((volatile unsigned long *)(0xE000ED28))));
|
||||
printf ("HFSR = %x\n", (*((volatile unsigned long *)(0xE000ED2C))));
|
||||
printf ("DFSR = %x\n", (*((volatile unsigned long *)(0xE000ED30))));
|
||||
printf ("AFSR = %x\n", (*((volatile unsigned long *)(0xE000ED3C))));
|
||||
*/
|
||||
//for(;;)
|
||||
//;/*infinite loop*/
|
||||
}
|
||||
|
||||
|
||||
/* End of "vectors.c" */
|
||||
@@ -0,0 +1,146 @@
|
||||
/******************************************************************************
|
||||
* @brief provide interrupt vector table for NV32Fxxx
|
||||
*
|
||||
*******************************************************************************/
|
||||
|
||||
|
||||
#ifndef __VECTORS_H
|
||||
#define __VECTORS_H 1
|
||||
|
||||
// function prototype for default_isr in vectors.c
|
||||
void default_isr(void);
|
||||
void abort_isr(void);
|
||||
|
||||
|
||||
void hard_fault_handler_c(unsigned int * hardfault_args);
|
||||
|
||||
/* Interrupt Vector Table Function Pointers */
|
||||
typedef void pointer(void);
|
||||
|
||||
extern void __startup(void);
|
||||
extern unsigned long __BOOT_STACK_ADDRESS[];
|
||||
extern unsigned long __initial_sp[];
|
||||
extern void Reset_Handler( void );
|
||||
#if (defined(__GNUC__))
|
||||
extern unsigned long _estack;
|
||||
extern void Reset_Handler(void);
|
||||
#define VECTOR_000 (pointer*)&_estack // ARM core Initial Supervisor SP
|
||||
#define VECTOR_001 Reset_Handler // 0x0000_0004 1 - ARM core Initial Program Counter
|
||||
#elif (defined(KEIL))
|
||||
#define VECTOR_000 (pointer*)__initial_sp // ARM core Initial Supervisor SP
|
||||
#define VECTOR_001 Reset_Handler // 0x0000_0004 1 - ARM core Initial Program Counter
|
||||
#else
|
||||
// Address Vector IRQ Source module Source description
|
||||
#define VECTOR_000 (pointer*)__BOOT_STACK_ADDRESS // ARM core Initial Supervisor SP
|
||||
#define VECTOR_001 __startup // 0x0000_0004 1 - ARM core Initial Program Counter
|
||||
#endif
|
||||
#define VECTOR_002 default_isr // 0x0000_0008 2 - ARM core Non-maskable Interrupt (NMI)
|
||||
#define VECTOR_003 default_isr // 0x0000_000C 3 - ARM core Hard Fault
|
||||
#define VECTOR_004 default_isr // 0x0000_0010 4 -
|
||||
#define VECTOR_005 default_isr // 0x0000_0014 5 - ARM core Bus Fault
|
||||
#define VECTOR_006 default_isr // 0x0000_0018 6 - ARM core Usage Fault
|
||||
#define VECTOR_007 default_isr // 0x0000_001C 7 -
|
||||
#define VECTOR_008 default_isr // 0x0000_0020 8 -
|
||||
#define VECTOR_009 default_isr // 0x0000_0024 9 -
|
||||
#define VECTOR_010 default_isr // 0x0000_0028 10 -
|
||||
#define VECTOR_011 default_isr // 0x0000_002C 11 - ARM core Supervisor call (SVCall)
|
||||
#define VECTOR_012 default_isr // 0x0000_0030 12 - ARM core Debug Monitor
|
||||
#define VECTOR_013 default_isr // 0x0000_0034 13 -
|
||||
#define VECTOR_014 default_isr // 0x0000_0038 14 - ARM core Pendable request for system service (PendableSrvReq)
|
||||
#define VECTOR_015 default_isr // 0x0000_003C 15 - ARM core System tick ETMer (SysTick)
|
||||
#define VECTOR_016 default_isr // 0x0000_0040 16 0 Reserved DMA DMA Channel 0 transfer complete
|
||||
#define VECTOR_017 default_isr // 0x0000_0044 17 1 Reserved DMA DMA Channel 1 transfer complete
|
||||
#define VECTOR_018 default_isr // 0x0000_0048 18 2 Reserved DMA DMA Channel 2 transfer complete
|
||||
#define VECTOR_019 default_isr // 0x0000_004C 19 3 Reserved DMA DMA Channel 3 transfer complete
|
||||
#define VECTOR_020 default_isr // 0x0000_0050 20 4 Reserved MCM MCM
|
||||
#define VECTOR_021 default_isr // 0x0000_0054 21 5 NVM ETMRH flash memory command complete,ECC fault
|
||||
#define VECTOR_022 default_isr // 0x0000_0058 22 6 PMC LVD,LVW interrupt
|
||||
#define VECTOR_023 default_isr // 0x0000_005C 23 7 LLWU LLWU/IRQ
|
||||
#define VECTOR_024 default_isr // 0x0000_0060 24 8 I2C0 I2C
|
||||
#define VECTOR_025 default_isr // 0x0000_0064 25 9 - --
|
||||
#define VECTOR_026 default_isr // 0x0000_0068 26 10 SPI0 SPI0
|
||||
#define VECTOR_027 default_isr // 0x0000_006C 27 11 SPI1 SPI1
|
||||
#define VECTOR_028 default_isr // 0x0000_0070 28 12 SCI0 UART0
|
||||
#define VECTOR_029 default_isr // 0x0000_0074 29 13 SCI1 UART1
|
||||
#define VECTOR_030 default_isr // 0x0000_0078 30 14 SCI2 UART2
|
||||
#define VECTOR_031 default_isr // 0x0000_007C 31 15 ADC0 ADC conversion complete
|
||||
#define VECTOR_032 default_isr // 0x0000_0080 32 16 ACMP0 ACMP0
|
||||
#define VECTOR_033 default_isr // 0x0000_0084 33 17 ETM0 FlexETMer0
|
||||
#define VECTOR_034 default_isr // 0x0000_0088 34 18 ETM1 FlexETMer1
|
||||
#define VECTOR_035 default_isr // 0x0000_008C 35 19 ETM2 FlexETMer2
|
||||
#define VECTOR_036 default_isr // 0x0000_0090 36 20 RTC RTC overflow
|
||||
#define VECTOR_037 default_isr // 0x0000_0094 37 21 ACMP1 ACMP1
|
||||
#define VECTOR_038 default_isr // 0x0000_0098 38 22 PIT_CH0 PIT_CH0 overflow
|
||||
#define VECTOR_039 default_isr // 0x0000_009C 39 23 PIT_CH1 PIT_CH1 overflow
|
||||
#define VECTOR_040 default_isr // 0x0000_00A0 40 24 KBI0 Keyboard0 interrupt
|
||||
#define VECTOR_041 default_isr // 0x0000_00A4 41 25 KBI1 Keyboard1 interrupt
|
||||
#define VECTOR_042 default_isr // 0x0000_00A8 42 26 Reserved ---
|
||||
#define VECTOR_043 default_isr // 0x0000_00AC 43 27 ICS ICS loss of lock
|
||||
#define VECTOR_044 default_isr // 0x0000_00B0 44 28 WDOG Watchdog ETMeout
|
||||
#define VECTOR_045 default_isr // 0x0000_00B4 45 29 Reserved
|
||||
#define VECTOR_046 default_isr // 0x0000_00B8 46 30 Reserved
|
||||
#define VECTOR_047 default_isr // 0x0000_00BC 47 31 Reserved // END of real vector table
|
||||
/********************************************************************************************************************/
|
||||
#define VECTOR_048 default_isr // 0x0000_00C0 48 32 Reserved
|
||||
#define VECTOR_049 default_isr // 0x0000_00C4 49 33 Reserved
|
||||
#define VECTOR_050 default_isr // 0x0000_00C8 50 34 Reserved
|
||||
#define VECTOR_051 default_isr // 0x0000_00CC 51 35 Reserved
|
||||
#define VECTOR_052 default_isr // 0x0000_00D0 52 36 Reserved
|
||||
#define VECTOR_053 default_isr // 0x0000_00D4 53 37 Reserved
|
||||
#define VECTOR_054 default_isr // 0x0000_00D8 54 38 Reserved
|
||||
#define VECTOR_055 default_isr // 0x0000_00DC 55 39 Reserved
|
||||
#define VECTOR_056 default_isr // 0x0000_00E0 56 40 Reserved
|
||||
#define VECTOR_057 default_isr // 0x0000_00E4 57 41 Reserved
|
||||
#define VECTOR_058 default_isr // 0x0000_00E8 58 42 Reserved
|
||||
#define VECTOR_059 default_isr // 0x0000_00EC 59 43 Reserved
|
||||
#define VECTOR_060 default_isr // 0x0000_00F0 60 44 Reserved
|
||||
#define VECTOR_061 default_isr // 0x0000_00F4 61 45 Reserved Single interrupt vector for SCI status sources
|
||||
#define VECTOR_062 default_isr // 0x0000_00F8 62 46 Reserved Single interrupt vector for SCI error sources
|
||||
#define VECTOR_063 default_isr // 0x0000_00FC 63 47 Reserved Single interrupt vector for SCI status sources
|
||||
#define VECTOR_064 default_isr // 0x0000_0100 64 48 Reserved Single interrupt vector for SCI error sources
|
||||
#define VECTOR_065 default_isr // 0x0000_0104 65 49 Reserved Single interrupt vector for SCI status sources
|
||||
#define VECTOR_066 default_isr // 0x0000_0108 66 50 Reserved Single interrupt vector for SCI error sources
|
||||
#define VECTOR_067 default_isr // 0x0000_010C 67 51 Reserved Single interrupt vector for SCI status sources
|
||||
#define VECTOR_068 default_isr // 0x0000_0110 68 52 Reserved Single interrupt vector for SCI error sources
|
||||
#define VECTOR_069 default_isr // 0x0000_0114 69 53 Reserved Single interrupt vector for SCI status sources
|
||||
#define VECTOR_070 default_isr // 0x0000_0118 70 54 Reserved Single interrupt vector for SCI error sources
|
||||
#define VECTOR_071 default_isr // 0x0000_011C 71 55 Reserved Single interrupt vector for SCI status sources
|
||||
#define VECTOR_072 default_isr // 0x0000_0120 72 56 Reserved Single interrupt vector for SCI error sources
|
||||
#define VECTOR_073 default_isr // 0x0000_0124 73 57 Reserved
|
||||
#define VECTOR_074 default_isr // 0x0000_0128 74 58 Reserved
|
||||
#define VECTOR_075 default_isr // 0x0000_012C 75 59 Reserved
|
||||
#define VECTOR_076 default_isr // 0x0000_0130 76 60 Reserved
|
||||
#define VECTOR_077 default_isr // 0x0000_0134 77 61 Reserved
|
||||
#define VECTOR_078 default_isr // 0x0000_0138 78 62 Reserved Single interrupt vector for all sources
|
||||
#define VECTOR_079 default_isr // 0x0000_013C 79 63 Reserved Single interrupt vector for all sources
|
||||
#define VECTOR_080 default_isr // 0x0000_0140 80 64 Reserved Single interrupt vector for all sources
|
||||
#define VECTOR_081 default_isr // 0x0000_0144 81 65 Reserved
|
||||
#define VECTOR_082 default_isr // 0x0000_0148 82 66 Reserved
|
||||
#define VECTOR_083 default_isr // 0x0000_014C 83 67
|
||||
#define VECTOR_084 default_isr // 0x0000_0150 84 68
|
||||
#define VECTOR_085 default_isr // 0x0000_0154 85 69
|
||||
#define VECTOR_086 default_isr // 0x0000_0158 86 70
|
||||
#define VECTOR_087 default_isr // 0x0000_015C 87 71
|
||||
#define VECTOR_088 default_isr // 0x0000_0160 88 72
|
||||
#define VECTOR_089 default_isr // 0x0000_0164 89 73
|
||||
#define VECTOR_090 default_isr // 0x0000_0168 90 74
|
||||
#define VECTOR_091 default_isr // 0x0000_016C 91 75
|
||||
#define VECTOR_092 default_isr // 0x0000_0170 92 76
|
||||
#define VECTOR_093 default_isr // 0x0000_0174 93 77
|
||||
#define VECTOR_094 default_isr // 0x0000_0178 94 78
|
||||
#define VECTOR_095 default_isr // 0x0000_017C 95 79
|
||||
#define VECTOR_096 default_isr // 0x0000_0180 96 80
|
||||
#define VECTOR_097 default_isr // 0x0000_0184 97 81
|
||||
#define VECTOR_098 default_isr // 0x0000_0188 98 82
|
||||
#define VECTOR_099 default_isr // 0x0000_018C 99 83
|
||||
|
||||
#ifdef USE_BOOTLOADER
|
||||
#else
|
||||
#define CONFIG_1 0xffffffff
|
||||
#define CONFIG_2 0xffffffff
|
||||
#define CONFIG_3 0xffffffff
|
||||
#define CONFIG_4 0xfffeffff
|
||||
#endif
|
||||
#endif /*__VECTORS_H*/
|
||||
|
||||
/* End of "vectors.h" */
|
||||
Reference in New Issue
Block a user