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PAN159/PAN159-Template/Library/StdDriver/inc/acmp.h
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/**************************************************************************//**
* @file acmp.h
* @version V1.00
* $Revision: 4 $
* $Date: 15/05/26 5:56p $
* @brief Mini58 series Analog Comparator(ACMP) driver header file
*
* @note
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ACMP_H__
#define __ACMP_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
@{
*/
/** @addtogroup Mini58_ACMP_Driver ACMP Driver
@{
*/
/** @addtogroup Mini58_ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
@{
*/
#define ACMP_VNEG_PIN (0xFFUL) ///< Selecting the voltage of ACMP negative input pin as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_BANDGAP (0x00UL) ///< Selecting band-gap voltage as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_4_OVER_24_VDD (0x80UL) ///< Selecting 4/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_5_OVER_24_VDD (0x81UL) ///< Selecting 5/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_6_OVER_24_VDD (0x82UL) ///< Selecting 6/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_7_OVER_24_VDD (0x83UL) ///< Selecting 7/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_8_OVER_24_VDD (0x84UL) ///< Selecting 8/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_9_OVER_24_VDD (0x85UL) ///< Selecting 9/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_10_OVER_24_VDD (0x86UL) ///< Selecting 10/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_11_OVER_24_VDD (0x87UL) ///< Selecting 11/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_12_OVER_24_VDD (0x88UL) ///< Selecting 12/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_13_OVER_24_VDD (0x89UL) ///< Selecting 13/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_14_OVER_24_VDD (0x8AUL) ///< Selecting 14/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_15_OVER_24_VDD (0x8BUL) ///< Selecting 15/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_16_OVER_24_VDD (0x8CUL) ///< Selecting 16/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_17_OVER_24_VDD (0x8DUL) ///< Selecting 17/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_18_OVER_24_VDD (0x8EUL) ///< Selecting 18/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_VNEG_19_OVER_24_VDD (0x8FUL) ///< Selecting 19/24 VDD as the source of ACMP V- \hideinitializer
#define ACMP_HYSTERESIS_ENABLE (1UL << ACMP_CTL_HYSSEL_Pos) ///< Enable hysteresis function \hideinitializer
#define ACMP_HYSTERESIS_DISABLE (0UL) ///< Disable hysteresis function \hideinitializer
#define ACMP_CH0_POSPIN_P15 (0UL) ///< Selecting P1.5 as ACMP Channel 0 positive input pin \hideinitializer
#define ACMP_CH0_POSPIN_P10 (1UL << ACMP_CTL_POSSEL_Pos) ///< Selecting P1.0 as ACMP Channel 0 positive input pin \hideinitializer
#define ACMP_CH0_POSPIN_P12 (2UL << ACMP_CTL_POSSEL_Pos) ///< Selecting P1.2 as ACMP Channel 0 positive input pin \hideinitializer
#define ACMP_CH0_POSPIN_P13 (3UL << ACMP_CTL_POSSEL_Pos) ///< Selecting P1.3 as ACMP Channel 0 positive input pin \hideinitializer
#define ACMP_CH1_POSPIN_P31 (0UL) ///< Selecting P3.1 as ACMP Channel 1 positive input pin \hideinitializer
#define ACMP_CH1_POSPIN_P32 (1UL << ACMP_CTL_POSSEL_Pos) ///< Selecting P3.2 as ACMP Channel 1 positive input pin \hideinitializer
#define ACMP_CH1_POSPIN_P34 (2UL << ACMP_CTL_POSSEL_Pos) ///< Selecting P3.4 as ACMP Channel 1 positive input pin \hideinitializer
#define ACMP_CH1_POSPIN_P35 (3UL << ACMP_CTL_POSSEL_Pos) ///< Selecting P3.5 as ACMP Channel 1 positive input pin \hideinitializer
#define ACMP_FILTSEL_OFF (0UL) ///< Comparator output filter function is disabled \hideinitializer
#define ACMP_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 1 consecutive PCLK \hideinitializer
#define ACMP_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 2 consecutive PCLKs \hideinitializer
#define ACMP_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 4 consecutive PCLKs \hideinitializer
#define ACMP_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 8 consecutive PCLKs \hideinitializer
#define ACMP_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 16 consecutive PCLKs \hideinitializer
#define ACMP_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 32 consecutive PCLKs \hideinitializer
#define ACMP_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 64 consecutive PCLKs \hideinitializer
#define ACMP_FILTSEL_128PCLK (8UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 128 consecutive PCLKs \hideinitializer
#define ACMP_FILTSEL_256PCLK (9UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 256 consecutive PCLKs \hideinitializer
#define ACMP_FILTSEL_512PCLK (10UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 512 consecutive PCLKs \hideinitializer
/*@}*/ /* end of group Mini58_ACMP_EXPORTED_CONSTANTS */
/** @addtogroup Mini58_ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
@{
*/
/**
* @brief This macro is used to select ACMP negative input source
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number, ether 0 or 1
* @param[in] u32Src is comparator negative input selection. Including :
* - \ref ACMP_VNEG_PIN
* - \ref ACMP_VNEG_BANDGAP
* - \ref ACMP_VNEG_4_OVER_24_VDD
* - \ref ACMP_VNEG_5_OVER_24_VDD
* - \ref ACMP_VNEG_6_OVER_24_VDD
* - \ref ACMP_VNEG_7_OVER_24_VDD
* - \ref ACMP_VNEG_8_OVER_24_VDD
* - \ref ACMP_VNEG_9_OVER_24_VDD
* - \ref ACMP_VNEG_10_OVER_24_VDD
* - \ref ACMP_VNEG_11_OVER_24_VDD
* - \ref ACMP_VNEG_12_OVER_24_VDD
* - \ref ACMP_VNEG_13_OVER_24_VDD
* - \ref ACMP_VNEG_14_OVER_24_VDD
* - \ref ACMP_VNEG_15_OVER_24_VDD
* - \ref ACMP_VNEG_16_OVER_24_VDD
* - \ref ACMP_VNEG_17_OVER_24_VDD
* - \ref ACMP_VNEG_18_OVER_24_VDD
* - \ref ACMP_VNEG_19_OVER_24_VDD
*
* @return None
* @note The V- setting is shared by both comparators if input source is not coming from PIN
* \hideinitializer
*/
#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) do{\
if(u32Src == ACMP_VNEG_PIN)\
ACMP->CTL[u32ChNum] &= ~ACMP_CTL_NEGSEL_Msk;\
else {\
ACMP->CTL[u32ChNum] |= ACMP_CTL_NEGSEL_Msk;\
ACMP->VREF = u32Src;\
}\
}while(0)
/**
* @brief This macro is used to enable hysteresis function
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number, ether 0 or 1
* @return None
* \hideinitializer
*/
#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_HYSSEL_Msk)
/**
* @brief This macro is used to disable hysteresis function
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number, ether 0 or 1
* @return None
* \hideinitializer
*/
#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_HYSSEL_Msk)
/**
* @brief This macro is used to enable interrupt
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number, ether 0 or 1
* @return None
* \hideinitializer
*/
#define ACMP_ENABLE_INT(acmp, u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPIE_Msk)
/**
* @brief This macro is used to disable interrupt
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number, ether 0 or 1
* @return None
* \hideinitializer
*/
#define ACMP_DISABLE_INT(acmp, u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPIE_Msk)
/**
* @brief This macro is used to enable ACMP
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number
* @return None
* \hideinitializer
*/
#define ACMP_ENABLE(acmp, u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPEN_Msk)
/**
* @brief This macro is used to disable ACMP
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number, ether 0 or 1
* @return None
* \hideinitializer
*/
#define ACMP_DISABLE(acmp, u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPEN_Msk)
/**
* @brief This macro is used to get ACMP output value
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number, ether 0 or 1
* @return 1 or 0
* \hideinitializer
*/
#define ACMP_GET_OUTPUT(acmp, u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPO0_Msk<<(u32ChNum))?1:0)
/**
* @brief This macro is used to get ACMP interrupt flag
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number, ether 0 or 1
* @return ACMP interrupt occurred or not
* \hideinitializer
*/
#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum))?1:0)
/**
* @brief This macro is used to clear ACMP interrupt flag
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number, ether 0 or 1
* @return None
* \hideinitializer
*/
#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) (ACMP->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum)))
/**
* @brief This macro is used to select the V+ pin of ACMP
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number, ether 0 or 1
* @param[in] u32Pin The input pin. For channel 0, valid values are \ref ACMP_CH0_POSPIN_P15,
* \ref ACMP_CH0_POSPIN_P10, \ref ACMP_CH0_POSPIN_P12, and \ref ACMP_CH0_POSPIN_P13. For
* channel 1, valid values are , \ref ACMP_CH1_POSPIN_P31, \ref ACMP_CH1_POSPIN_P32,
* \ref ACMP_CH1_POSPIN_P34, and \ref ACMP_CH1_POSPIN_P35.
* @return None
* @note Except this setting, multi-function pin also needs to be configured
* \hideinitializer
*/
#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) (ACMP->CTL[u32ChNum] = (ACMP->CTL[u32ChNum] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
/**
* @brief This macro is used to set the level of CRV(Comparator Reference Voltage)
* @param[in] acmp The base address of ACMP module
* @param[in] u32Level CRV level, possible values are
* - \ref ACMP_VNEG_4_OVER_24_VDD
* - \ref ACMP_VNEG_5_OVER_24_VDD
* - \ref ACMP_VNEG_6_OVER_24_VDD
* - \ref ACMP_VNEG_7_OVER_24_VDD
* - \ref ACMP_VNEG_8_OVER_24_VDD
* - \ref ACMP_VNEG_9_OVER_24_VDD
* - \ref ACMP_VNEG_10_OVER_24_VDD
* - \ref ACMP_VNEG_11_OVER_24_VDD
* - \ref ACMP_VNEG_12_OVER_24_VDD
* - \ref ACMP_VNEG_13_OVER_24_VDD
* - \ref ACMP_VNEG_14_OVER_24_VDD
* - \ref ACMP_VNEG_15_OVER_24_VDD
* - \ref ACMP_VNEG_16_OVER_24_VDD
* - \ref ACMP_VNEG_17_OVER_24_VDD
* - \ref ACMP_VNEG_18_OVER_24_VDD
* - \ref ACMP_VNEG_19_OVER_24_VDD
* @return None
* \hideinitializer
*/
#define ACMP_CRV_SEL(acmp, u32Level) (ACMP->VREF = (ACMP->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level) & ~ACMP_VREF_IREFSEL_Msk))
/**
* @brief This macro is used to enable CRV(Comparator Reference Voltage)
* @param[in] acmp The base address of ACMP module
* @return None
* \hideinitializer
*/
#define ACMP_ENABLE_CRV(acmp) (ACMP->VREF |= ACMP_VREF_IREFSEL_Msk)
/**
* @brief This macro is used to disable CRV(Comparator Reference Voltage)
* @param[in] acmp The base address of ACMP module
* @return None
* \hideinitializer
*/
#define ACMP_DISABLE_CRV(acmp) (ACMP->VREF &= ~ACMP_VREF_IREFSEL_Msk)
/**
* @brief This macro is used to enable ACMP falling edge trigger Timer/PWM
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number, ether 0 or 1
* @return None
* \hideinitializer
*/
#define ACMP_ENABLE_FALLING_EDGE_TRIGGER(acmp, u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_FTRGEN_Msk)
/**
* @brief This macro is used to disable ACMP falling edge trigger Timer/PWM
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number, ether 0 or 1
* @return None
* \hideinitializer
*/
#define ACMP_DISABLE_FALLING_EDGE_TRIGGER(acmp, u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_FTRGEN_Msk)
/**
* @brief This macro is used to enable ACMP rising edge trigger Timer/PWM
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number, ether 0 or 1
* @return None
* \hideinitializer
*/
#define ACMP_ENABLE_RISING_EDGE_TRIGGER(acmp, u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_RTRGEN_Msk)
/**
* @brief This macro is used to disable ACMP rising edge trigger Timer/PWM
* @param[in] acmp The base address of ACMP module
* @param[in] u32ChNum The ACMP number, ether 0 or 1
* @return None
* \hideinitializer
*/
#define ACMP_DISABLE_RISING_EDGE_TRIGGER(acmp, u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_RTRGEN_Msk)
/**
* @brief This macro is used to set ACMP filter function
* @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum The ACMP number
* @param[in] u32Cnt is comparator filter count setting.
* - \ref ACMP_FILTSEL_OFF
* - \ref ACMP_FILTSEL_1PCLK
* - \ref ACMP_FILTSEL_2PCLK
* - \ref ACMP_FILTSEL_4PCLK
* - \ref ACMP_FILTSEL_8PCLK
* - \ref ACMP_FILTSEL_16PCLK
* - \ref ACMP_FILTSEL_32PCLK
* - \ref ACMP_FILTSEL_64PCLK
* - \ref ACMP_FILTSEL_128PCLK
* - \ref ACMP_FILTSEL_256PCLK
* - \ref ACMP_FILTSEL_512PCLK
* @return None
* \hideinitializer
*/
#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[u32ChNum] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))
void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn);
void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum);
/*@}*/ /* end of group Mini58_ACMP_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group Mini58_ACMP_Driver */
/*@}*/ /* end of group Mini58_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__ACMP_H__
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
PAN159/PAN159-Template/Library/StdDriver/inc/adc.h
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/**************************************************************************//**
* @file adc.h
* @version V1.00
* $Revision: 3 $
* $Date: 15/06/03 9:34p $
* @brief Mini58 series ADC driver header file
*
* @note
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __ADC_H__
#define __ADC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
@{
*/
/** @addtogroup Mini58_ADC_Driver ADC Driver
@{
*/
/** @addtogroup Mini58_ADC_EXPORTED_CONSTANTS ADC Exported Constants
@{
*/
#define ADC_CH7_EXT (0UL) /*!< Use external input pin as ADC channel 7 source */
#define ADC_CH7_BGP (ADC_CHEN_CH7SEL_Msk) /*!< Use internal band-gap voltage (VBG) as channel 7 source. */
#define ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos) /*!< ADC compare condition less than */
#define ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos) /*!< ADC compare condition less than */
#define ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos) /*!< ADC compare condition greater or equal to */
#define ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos) /*!< ADC compare condition greater or equal to */
#define ADC_TRIGGER_BY_EXT_PIN (0UL) /*!< ADC trigger by STADC (P3.2) pin */
#define ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk) /*!< ADC trigger by PWM events */
#define ADC_FALLING_EDGE_TRIGGER (0UL) /*!< External pin falling edge trigger ADC */
#define ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk) /*!< External pin rising edge trigger ADC */
#define ADC_ADIF_INT (ADC_STATUS_ADIF_Msk) /*!< ADC convert complete interrupt */
#define ADC_CMP0_INT (ADC_STATUS_ADCMPF0_Msk) /*!< ADC comparator 0 interrupt */
#define ADC_CMP1_INT (ADC_STATUS_ADCMPF1_Msk) /*!< ADC comparator 0 interrupt */
#define ADC_SAMPLE_CLOCK_0 (0UL) /*!< ADC sample time is 0 ADC clock */
#define ADC_SAMPLE_CLOCK_1 (1UL) /*!< ADC sample time is 1 ADC clock */
#define ADC_SAMPLE_CLOCK_2 (2UL) /*!< ADC sample time is 2 ADC clock */
#define ADC_SAMPLE_CLOCK_4 (3UL) /*!< ADC sample time is 4 ADC clock */
#define ADC_SAMPLE_CLOCK_8 (4UL) /*!< ADC sample time is 8 ADC clock */
#define ADC_SAMPLE_CLOCK_16 (5UL) /*!< ADC sample time is 16 ADC clock */
#define ADC_SAMPLE_CLOCK_32 (6UL) /*!< ADC sample time is 32 ADC clock */
#define ADC_SAMPLE_CLOCK_64 (7UL) /*!< ADC sample time is 64 ADC clock */
#define ADC_SAMPLE_CLOCK_128 (8UL) /*!< ADC sample time is 128 ADC clock */
#define ADC_SAMPLE_CLOCK_256 (9UL) /*!< ADC sample time is 256 ADC clock */
#define ADC_SAMPLE_CLOCK_512 (10UL) /*!< ADC sample time is 512 ADC clock */
#define ADC_SAMPLE_CLOCK_1024 (11UL) /*!< ADC sample time is 1024 ADC clock */
#define ADC_SEQMODE_TYPE_23SHUNT (0UL) /*!< ADC sequential mode 23-shunt type */
#define ADC_SEQMODE_TYPE_1SHUNT (1UL) /*!< ADC sequential mode 1-shunt type */
#define ADC_SEQMODE_MODESELECT_CH01 (0UL) /*!< ADC channel 0 then channel 1 conversion */
#define ADC_SEQMODE_MODESELECT_CH12 (1UL) /*!< ADC channel 1 then channel 2 conversion */
#define ADC_SEQMODE_MODESELECT_CH02 (2UL) /*!< ADC channel 0 then channel 2 conversion */
#define ADC_SEQMODE_PWM0_RISING (0UL) /*!< ADC sequential mode PWM0 rising trigger ADC*/
#define ADC_SEQMODE_PWM0_CENTER (1UL) /*!< ADC sequential mode PWM0 center trigger ADC*/
#define ADC_SEQMODE_PWM0_FALLING (2UL) /*!< ADC sequential mode PWM0 falling trigger ADC*/
#define ADC_SEQMODE_PWM0_PERIOD (3UL) /*!< ADC sequential mode PWM0 period trigger ADC*/
#define ADC_SEQMODE_PWM2_RISING (4UL) /*!< ADC sequential mode PWM2 rising trigger ADC*/
#define ADC_SEQMODE_PWM2_CENTER (5UL) /*!< ADC sequential mode PWM2 center trigger ADC*/
#define ADC_SEQMODE_PWM2_FALLING (6UL) /*!< ADC sequential mode PWM2 falling trigger ADC*/
#define ADC_SEQMODE_PWM2_PERIOD (7UL) /*!< ADC sequential mode PWM2 period trigger ADC*/
#define ADC_SEQMODE_PWM4_RISING (8UL) /*!< ADC sequential mode PWM4 rising trigger ADC*/
#define ADC_SEQMODE_PWM4_CENTER (9UL) /*!< ADC sequential mode PWM4 center trigger ADC*/
#define ADC_SEQMODE_PWM4_FALLING (10UL) /*!< ADC sequential mode PWM4 falling trigger ADC*/
#define ADC_SEQMODE_PWM4_PERIOD (11UL) /*!< ADC sequential mode PWM4 period trigger ADC*/
/*@}*/ /* end of group Mini58_ADC_EXPORTED_CONSTANTS */
/** @addtogroup Mini58_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
@{
*/
/**
* @brief Configure the analog input source of channel 7
* @param[in] adc Base address of ADC module
* @param[in] u32Source Decides the analog input source of channel 7, valid values are
* - \ref ADC_CH7_EXT
* - \ref ADC_CH7_BGP
* @return None
* @note While using VBG as channel 7 source, ADC module clock must /b not exceed 300kHz
* \hideinitializer
*/
#define ADC_CONFIG_CH7(adc, u32Source) (ADC->CHEN = ((adc)->CHEN & ~ADC_CHEN_CH7SEL_Msk) | (u32Source))
/**
* @brief Get the latest ADC conversion data
* @param[in] adc Base address of ADC module
* @param[in] u32ChNum Currently not used
* @return Latest ADC conversion data
* \hideinitializer
*/
#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ((adc)->DAT & ADC_DAT_RESULT_Msk)
/**
* @brief Return the user-specified interrupt flags
* @param[in] adc Base address of ADC module
* @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
* - \ref ADC_ADIF_INT
* - \ref ADC_CMP0_INT
* - \ref ADC_CMP1_INT
* @return User specified interrupt flags
* \hideinitializer
*/
#define ADC_GET_INT_FLAG(adc, u32Mask) ((adc)->STATUS & (u32Mask))
/**
* @brief This macro clear the selected interrupt status bits
* @param[in] adc Base address of ADC module
* @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
* - \ref ADC_ADIF_INT
* - \ref ADC_CMP0_INT
* - \ref ADC_CMP1_INT
* @return None
* \hideinitializer
*/
#define ADC_CLR_INT_FLAG(adc, u32Mask) ((adc)->STATUS = ((adc)->STATUS & ~(ADC_STATUS_ADIF_Msk | \
ADC_STATUS_ADCMPF0_Msk | \
ADC_STATUS_ADCMPF1_Msk)) | (u32Mask))
/**
* @brief Get the busy state of ADC
* @param[in] adc Base address of ADC module
* @return busy state of ADC
* @retval 0 ADC is not busy
* @retval 1 ADC is busy
* \hideinitializer
*/
#define ADC_IS_BUSY(adc) ((adc)->STATUS & ADC_STATUS_BUSY_Msk ? 1 : 0)
/**
* @brief Check if the ADC conversion data is over written or not
* @param[in] adc Base address of ADC module
* @param[in] u32ChNum Currently not used
* @return Over run state of ADC data
* @retval 0 ADC data is not overrun
* @retval 1 ADC data is overrun
* \hideinitializer
*/
#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) ((adc)->STATUS & ADC_STATUS_OV_Msk ? 1 : 0)
/**
* @brief Check if the ADC conversion data is valid or not
* @param[in] adc Base address of ADC module
* @param[in] u32ChNum Currently not used
* @return Valid state of ADC data
* @retval 0 ADC data is not valid
* @retval 1 ADC data us valid
* \hideinitializer
*/
#define ADC_IS_DATA_VALID(adc, u32ChNum) ((adc)->STATUS & ADC_STATUS_VALID_Msk ? 1 : 0)
/**
* @brief Power down ADC module
* @param[in] adc Base address of ADC module
* @return None
* \hideinitializer
*/
#define ADC_POWER_DOWN(adc) ((adc)->CTL &= ~ADC_CTL_ADCEN_Msk)
/**
* @brief Power on ADC module
* @param[in] adc Base address of ADC module
* @return None
* \hideinitializer
*/
#define ADC_POWER_ON(adc) ((adc)->CTL |= ADC_CTL_ADCEN_Msk)
/**
* @brief Configure the comparator 0 and enable it
* @param[in] adc Base address of ADC module
* @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7
* @param[in] u32Condition Specifies the compare condition
* - \ref ADC_CMP0_LESS_THAN
* - \ref ADC_CMP0_GREATER_OR_EQUAL_TO
* @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF
* @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16
* @return None
* @details For example, ADC_ENABLE_CMP0(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10);
* Means ADC will assert comparator 0 flag if channel 5 conversion result is
* greater or equal to 0x800 for 10 times continuously.
* \hideinitializer
*/
#define ADC_ENABLE_CMP0(adc, \
u32ChNum, \
u32Condition, \
u32Data, \
u32MatchCount) (ADC->CMP0 = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | \
(u32Condition) | \
((u32Data) << ADC_CMP0_CMPDAT_Pos) | \
(((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) |\
ADC_CMP0_ADCMPIE_Msk |\
ADC_CMP0_ADCMPEN_Msk)
/**
* @brief Disable comparator 0
* @param[in] adc Base address of ADC module
* \hideinitializer
*/
#define ADC_DISABLE_CMP0(adc) ((adc)->CMP0 = 0)
/**
* @brief Configure the comparator 1 and enable it
* @param[in] adc Base address of ADC module
* @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7
* @param[in] u32Condition Specifies the compare condition
* - \ref ADC_CMP1_LESS_THAN
* - \ref ADC_CMP1_GREATER_OR_EQUAL_TO
* @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF
* @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16
* @return None
* @details For example, ADC_ENABLE_CMP1(ADC, 5, ADC_CMP1_GREATER_OR_EQUAL_TO, 0x800, 10);
* Means ADC will assert comparator 1 flag if channel 5 conversion result is
* greater or equal to 0x800 for 10 times continuously.
* \hideinitializer
*/
#define ADC_ENABLE_CMP1(adc, \
u32ChNum, \
u32Condition, \
u32Data, \
u32MatchCount) (ADC->CMP1 = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | \
(u32Condition) | \
((u32Data) << ADC_CMP1_CMPDAT_Pos) | \
((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) |\
ADC_CMP1_ADCMPEN_Msk)
/**
* @brief Disable comparator 1
* @param[in] adc Base address of ADC module
* \hideinitializer
*/
#define ADC_DISABLE_CMP1(adc) ((adc)->CMP1 = 0)
/**
* @brief Set ADC input channel. Enabled channel will be converted while ADC starts.
* @param[in] adc Base address of ADC module
* @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1...
* @return None
* @note Mini58 series MCU ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel
* with smallest number will be convert.
* \hideinitializer
*/
#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) ((adc)->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN0_Msk) | (u32Mask))
/**
* @brief Start the A/D conversion.
* @param[in] adc Base address of ADC module
* @return None
* \hideinitializer
*/
#define ADC_START_CONV(adc) ((adc)->CTL |= ADC_CTL_SWTRG_Msk)
/**
* @brief Stop the A/D conversion.
* @param[in] adc Base address of ADC module
* @return None
* \hideinitializer
*/
#define ADC_STOP_CONV(adc) ((adc)->CTL &= ~ADC_CTL_SWTRG_Msk)
void ADC_Open(ADC_T *adc,
uint32_t u32InputMode,
uint32_t u32OpMode,
uint32_t u32ChMask);
void ADC_Close(ADC_T *adc);
void ADC_EnableHWTrigger(ADC_T *adc,
uint32_t u32Source,
uint32_t u32Param);
void ADC_DisableHWTrigger(ADC_T *adc);
void ADC_SetExtraSampleTime(ADC_T *adc,
uint32_t u32ChNum,
uint32_t u32SampleTime);
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
void ADC_SeqModeEnable(ADC_T *adc, uint32_t u32SeqTYPE, uint32_t u32ModeSel);
void ADC_SeqModeTriggerSrc(ADC_T *adc, uint32_t u32SeqModeTriSrc1, uint32_t u32SeqModeTriSrc2);
/*@}*/ /* end of group Mini58_ADC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group Mini58_ADC_Driver */
/*@}*/ /* end of group Mini58_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__ADC_H__
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
PAN159/PAN159-Template/Library/StdDriver/inc/clk.h
+263
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/**************************************************************************//**
* @file clk.h
* @version V1.00
* $Revision: 16 $
* $Date: 15/06/05 9:38a $
* @brief Mini58 series CLK driver header file
*
* @note
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __CLK_H__
#define __CLK_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
@{
*/
/** @addtogroup Mini58_CLK_Driver CLK Driver
@{
*/
/** @addtogroup Mini58_CLK_EXPORTED_CONSTANTS CLK Exported Constants
@{
*/
#define FREQ_25MHZ 25000000
#define FREQ_50MHZ 50000000
#define FREQ_72MHZ 72000000
#define FREQ_100MHZ 100000000
#define FREQ_200MHZ 200000000
#define FREQ_250MHZ 250000000
#define FREQ_500MHZ 500000000
/*---------------------------------------------------------------------------------------------------------*/
/* PWRCTL constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_PWRCTL_XTL12M 0x01UL /*!< Setting External Crystal Oscillator as 12MHz */
#define CLK_PWRCTL_XTLEN_HXT 0x01UL /*!< Setting External Crystal Oscillator as 12MHz */
#define CLK_PWRCTL_XTL32K 0x02UL /*!< Setting External Crystal Oscillator as 32KHz */
#define CLK_PWRCTL_XTLEN_LXT 0x02UL /*!< Setting External Crystal Oscillator as 32KHz */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL0 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL /*!< Setting clock source as external XTAL */
#define CLK_CLKSEL0_HCLKSEL_HXT 0x00UL /*!< Setting clock source as external HXT */
#define CLK_CLKSEL0_HCLKSEL_LXT 0x00UL /*!< Setting clock source as external LXT */
#define CLK_CLKSEL0_HCLKSEL_PLL 0x02UL /*!< Setting clock source as PLL */
#define CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL /*!< Setting clock source as internal 10KHz RC clock */
#define CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL /*!< Setting clock source as internal RC clock */
#define CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL /*!< Setting clock source as external XTAL */
#define CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL /*!< Setting clock source as external XTAL/2 */
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL /*!< Setting clock source as HCLK/2 */
#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL /*!< Setting clock source as internal RC clock/2 */
#define CLK_CLKSEL0_STCLKSEL_HCLK 0x08UL /*!< Setting clock source as HCLK */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL1 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL /*!< Setting WDT clock source as external XTAL */
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL /*!< Setting WDT clock source as HCLK/2048 */
#define CLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL /*!< Setting WDT clock source as internal 10KHz RC clock */
#define CLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL /*!< Setting WDT clock source as internal 10KHz RC clock */
#define CLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL /*!< Setting ADC clock source as external XTAL */
#define CLK_CLKSEL1_ADCSEL_PLL 0x00000004UL /*!< Setting ADC clock source as PLL */
#define CLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL /*!< Setting ADC clock source as HCLK */
#define CLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL /*!< Setting ADC clock source as internal RC clock */
#define CLK_CLKSEL1_SPISEL_XTAL 0x00000000UL /*!< Setting SPI clock source as HXT or LXT */
#define CLK_CLKSEL1_SPISEL_HCLK 0x00000010UL /*!< Setting SPI clock source as HCLK */
#define CLK_CLKSEL1_SPISEL_PLL 0x00000020UL /*!< Setting SPI clock source as PLL */
#define CLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL /*!< Setting Timer 0 clock source as external XTAL */
#define CLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL /*!< Setting Timer 0 clock source as internal 10KHz RC clock */
#define CLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL /*!< Setting Timer 0 clock source as HCLK */
#define CLK_CLKSEL1_TMR0SEL_TM0 0x00000300UL /*!< Setting Timer 0 clock source as external trigger */
#define CLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL /*!< Setting Timer 0 clock source as internal RC clock */
#define CLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL /*!< Setting Timer 1 clock source as external XTAL */
#define CLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL /*!< Setting Timer 1 clock source as internal 10KHz RC clock */
#define CLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL /*!< Setting Timer 1 clock source as HCLK */
#define CLK_CLKSEL1_TMR1SEL_TM1 0x00003000UL /*!< Setting Timer 1 clock source as external trigger */
#define CLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL /*!< Setting Timer 1 clock source as internal RC clock */
#define CLK_CLKSEL1_UARTSEL_XTAL 0x00000000UL /*!< Setting UART clock source as external XTAL */
#define CLK_CLKSEL1_UARTSEL_PLL 0x01000000UL /*!< Setting UART clock source as external PLL */
#define CLK_CLKSEL1_UARTSEL_HIRC 0x02000000UL /*!< Setting UART clock source as external internal RC clock */
#define CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL /*!< Setting PWM01 clock source as external HCLK */
#define CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL /*!< Setting PWM23 clock source as external HCLK */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL2 constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKSEL2_CLKOSEL_XTAL 0x00000000UL /*!< Setting CLKODIV clock source as external XTAL */
#define CLK_CLKSEL2_CLKOSEL_HXT 0x00000000UL /*!< Setting CLKODIV clock source as external XTAL */
#define CLK_CLKSEL2_CLKOSEL_LXT 0x00000000UL /*!< Setting CLKODIV clock source as external XTAL */
#define CLK_CLKSEL2_CLKOSEL_LIRC 0x00000004UL /*!< Setting CLKODIV clock source as LIRC */
#define CLK_CLKSEL2_CLKOSEL_HCLK 0x00000008UL /*!< Setting CLKODIV clock source as HCLK */
#define CLK_CLKSEL2_CLKOSEL_HIRC 0x0000000CUL /*!< Setting CLKODIV clock source as internal RC clock */
#define CLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL /*!< Setting PWMCH45 clock source as HCLK */
#define CLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 0x00020000UL /*!< Setting WWDT clock source as HCLK/2048 */
#define CLK_CLKSEL2_WWDTSEL_LIRC 0x00030000UL /*!< Setting WWDT clock source as internal RC clock */
/*---------------------------------------------------------------------------------------------------------*/
/* CLKDIV constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_CLKDIV_ADC(x) (((x)-1) << 16) /*!< CLKDIV Setting for ADC clock divider. It could be 1~256 */
#define CLK_CLKDIV_UART(x) (((x)-1) << 8) /*!< CLKDIV Setting for UART clock divider. It could be 1~16 */
#define CLK_CLKDIV_HCLK(x) ((x)-1) /*!< CLKDIV Setting for HCLK clock divider. It could be 1~16 */
/*---------------------------------------------------------------------------------------------------------*/
/* PLLCTL constant definitions. PLL = FIN * NF / NR / NO */
/*---------------------------------------------------------------------------------------------------------*/
#define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 3.2MHz < FIN < 150MHz */
#define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 3.2MHz < FIN < 150MHz */
#define CLK_PLLCTL_NF(x) ((x)-2) /*!< x must be constant and 2 <= x <= 513. 200MHz < FIN*NF/NR < 500MHz. (FIN*NF/NR > 250MHz is preferred.) */
#define CLK_PLLCTL_NR(x) (((x)-2)<<9) /*!< x must be constant and 2 <= x <= 33. 1.6MHz < FIN/NR < 16MHz */
#define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 */
#define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 */
#define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 */
#define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 24) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) */
#define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 32) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 96MHz PLL output with HXT(12MHz X'tal) */
#define CLK_PLLCTL_100MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 50) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 100MHz PLL output with HXT(12MHz X'tal) */
#define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 26) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 71.884800MHz PLL output with HIRC(22.1184MHz X'tal) */
#define CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13)| CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 96.129968MHz PLL output with HIRC(22.1184MHz X'tal) */
#define CLK_PLLCTL_100MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 36) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 99.532800MHz PLL output with HIRC(22.1184MHz X'tal) */
/*---------------------------------------------------------------------------------------------------------*/
/* MODULE constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define MODULE_APBCLK(x) ((x >>31) & 0x1) /*!< Calculate APBCLK offset on MODULE index */
#define MODULE_CLKSEL(x) ((x >>29) & 0x3) /*!< Calculate CLKSEL offset on MODULE index */
#define MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) /*!< Calculate CLKSEL mask offset on MODULE index */
#define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index */
#define MODULE_CLKDIV(x) ((x >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index */
#define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index */
#define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index */
#define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index */
#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index */
#define NA MODULE_NoMsk /*!< Not Available */
#define MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK */
#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1 0x3 CLKSEL2*/
#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25) /*!< CLKSEL mask offset on MODULE index */
#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) /*!< CLKSEL position offset on MODULE index */
#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV */
#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) /*!< CLKDIV mask offset on MODULE index */
#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) /*!< CLKDIV position offset on MODULE index */
#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) /*!< APBCLK offset on MODULE index */
/*-------------------------------------------------------------------------------------------------------------------------------*/
/* APBCLK(1) | CLKSEL(2) | CLKSEL_Msk(4) | CLKSEL_Pos(5) | CLKDIV(2) | CLKDIV_Msk(8) | CLKDIV_Pos(5) | IP_EN_Pos(5)*/
/*-------------------------------------------------------------------------------------------------------------------------------*/
#define ISP_MODULE (( 0UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 2<<0)) /*!< ISP Module \hideinitializer */
#define WDT_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 0<<0)) /*!< WDT Module \hideinitializer */
#define TMR0_MODULE (( 1UL<<31)|( 1<<29)|( 7<<25)|( 8<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 2<<0)) /*!< TMR0 Module \hideinitializer */
#define TMR1_MODULE (( 1UL<<31)|( 1<<29)|( 7<<25)|(12<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 3<<0)) /*!< TMR1 Module \hideinitializer */
#define CLKO_MODULE (( 1UL<<31)|( 3<<29)|( 3<<25)|( 2<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 6<<0)) /*!< CLKO Module \hideinitializer */
#define I2C0_MODULE (( 1UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 8<<0)) /*!< I2C0 Module \hideinitializer */
#define I2C1_MODULE (( 1UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 9<<0)) /*!< I2C1 Module \hideinitializer */
#define SPI0_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|( 4<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(12<<0)) /*!< SPI Module \hideinitializer */
#define UART0_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(24<<20)|( 0<<18)|( 0xF<<10)|( 8<<5)|(16<<0)) /*!< UART0 Module \hideinitializer */
#define UART1_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(24<<20)|( 0<<18)|( 0xF<<10)|( 8<<5)|(17<<0)) /*!< UART1 Module \hideinitializer */
#define PWMCH01_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(28<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(20<<0)) /*!< PWMCH01 Module \hideinitializer */
#define PWMCH23_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(30<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(21<<0)) /*!< PWMCH23 Module \hideinitializer */
#define PWMCH45_MODULE (( 1UL<<31)|( 3<<29)|( 3<<25)|( 4<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(22<<0)) /*!< PWMCH45 Module \hideinitializer */
#define ADC_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|( 2<<20)|( 0<<18)|( 0xFF<<10)|(16<<5)|(28<<0)) /*!< ADC Module \hideinitializer */
#define ACMP_MODULE (( 1UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(30<<0)) /*!< ACMP Module \hideinitializer */
#define WWDT_MODULE (( 1UL<<31)|( 3<<29)|( 3<<25)|(16<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 0<<0)) /*!< WWDT Module \hideinitializer */
/*@}*/ /* end of group Mini58_CLK_EXPORTED_CONSTANTS */
/** @addtogroup Mini58_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
@{
*/
/**
* @brief Get PLL clock frequency
* @param None
* @return PLL frequency
* @details This function get PLL frequency. The frequency unit is Hz.
*/
__STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void)
{
uint32_t u32PllFreq = 0, u32PllReg;
uint32_t u32FIN, u32NF, u32NR, u32NO;
uint8_t au8NoTbl[4] = {1, 2, 2, 4};
u32PllReg = CLK->PLLCTL;
if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))
return 0; /* PLL is in power down mode or fix low */
if(u32PllReg & CLK_PLLCTL_PLLSRC_HIRC)
u32FIN = __HIRC; /* PLL source clock from HIRC */
else
u32FIN = __XTAL; /* PLL source clock from HXT */
if(u32PllReg & CLK_PLLCTL_BP_Msk)
return u32FIN; /* PLL is in bypass mode */
/* PLL is output enabled in normal work mode */
u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2;
u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 2;
/* u32FIN is shifted 2 bits to avoid overflow */
u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2);
return u32PllFreq;
}
void CLK_DisableCKO(void);
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
void CLK_PowerDown(void);
void CLK_Idle(void);
uint32_t CLK_GetHXTFreq(void);
uint32_t CLK_GetLXTFreq(void);
uint32_t CLK_GetHCLKFreq(void);
uint32_t CLK_GetCPUFreq(void);
uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
void CLK_DisableSysTick(void);
void CLK_EnableXtalRC(uint32_t u32ClkMask);
void CLK_DisableXtalRC(uint32_t u32ClkMask);
void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
void CLK_SysTickDelay(uint32_t us);
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
void CLK_DisablePLL(void);
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
/*@}*/ /* end of group Mini58_CLK_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group Mini58_CLK_Driver */
/*@}*/ /* end of group Mini58_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__CLK_H__
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
PAN159/PAN159-Template/Library/StdDriver/inc/fmc.h
+111
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/**************************************************************************//**
* @file FMC.h
* @version V1.00
* $Revision: 5 $
* $Date: 15/05/26 12:39p $
* @brief Mini58 series FMC driver header file
*
* @note
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/
#ifndef __FMC_H__
#define __FMC_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
@{
*/
/** @addtogroup Mini58_FMC_Driver FMC Driver
@{
*/
/** @addtogroup Mini58_FMC_EXPORTED_CONSTANTS FMC Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Define Base Address */
/*---------------------------------------------------------------------------------------------------------*/
#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */
#define FMC_APROM_END 0x00008000UL /*!< APROM End Address */
#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */
#define FMC_LDROM_END 0x00100A00UL /*!< LDROM End Address */
#define FMC_SPROM_BASE 0x00200000UL /*!< SPROM Base Address */
#define FMC_SPROM_END 0x00200200UL /*!< SPROM End Address */
#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */
#define FMC_FLASH_PAGE_SIZE 0x200 /*!< Flash Page Size (512 Bytes) */
#define FMC_LDROM_SIZE 0xA00 /*!< LDROM Size (2 Kbytes) */
#define FMC_SPROM_SIZE 0x200 /*!< SPROM Size (512 bytes) */
/*---------------------------------------------------------------------------------------------------------*/
/* ISPCMD constant definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define FMC_ISPCMD_READ 0x00 /*!< ISP Command: Read Flash */
#define FMC_ISPCMD_READ_UID 0x04 /*!< ISP Command: Read Unique ID */
#define FMC_ISPCMD_READ_CID 0x0B /*!< ISP Command: Read Company ID */
#define FMC_ISPCMD_READ_PID 0x0C /*!< ISP Command: Read Product ID */
#define FMC_ISPCMD_READ_CRC32 0x0D /*!< ISP Command: Read CRC32 checksum */
#define FMC_ISPCMD_PROGRAM 0x21 /*!< ISP Command: Program Flash */
#define FMC_ISPCMD_PAGE_ERASE 0x22 /*!< ISP Command: Page Erase Flash */
#define FMC_ISPCMD_CAL_CRC32 0x2D /*!< ISP Command: Run CRC32 checksum calculation */
#define FMC_ISPCMD_VECMAP 0x2E /*!< ISP Command: Vector Page Remap */
/*@}*/ /* end of group Mini58_FMC_EXPORTED_CONSTANTS */
/** @addtogroup Mini58_FMC_EXPORTED_FUNCTIONS FMC Exported Functions
@{
*/
#define FMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk) /*!< Select booting from APROM */
#define FMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk) /*!< Select booting from LDROM */
#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM update */
#define FMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk) /*!< Disable SPROM update */
#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable User Config update */
#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM update */
#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP function */
#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM update */
#define FMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk) /*!< Enable SPROM update */
#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM update */
#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable User Config update */
#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP function */
#define FMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1 : 0) /*!< Get ISP fail flag */
extern void FMC_Close(void);
extern int32_t FMC_Erase(uint32_t u32PageAddr);
extern int32_t FMC_GetBootSource(void);
extern void FMC_Open(void);
extern uint32_t FMC_Read (uint32_t u32Addr);
extern uint32_t FMC_ReadCID(void);
extern uint32_t FMC_ReadPID(void);
extern uint32_t FMC_ReadUCID(uint32_t u32Index);
extern uint32_t FMC_ReadUID(uint32_t u32Index);
extern uint32_t FMC_ReadDataFlashBaseAddr(void);
extern void FMC_SetVectorPageAddr(uint32_t u32PageAddr);
extern uint32_t FMC_GetVectorPageAddr(void);
extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data);
extern int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count);
extern int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count);
extern int32_t FMC_GetCRC32Sum(uint32_t addr, uint32_t count, uint32_t *chksum);
/*@}*/ /* end of group Mini58_FMC_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group Mini58_FMC_Driver */
/*@}*/ /* end of group Mini58_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif
PAN159/PAN159-Template/Library/StdDriver/inc/gpio.h
+375
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@@ -0,0 +1,375 @@
/**************************************************************************//**
* @file gpio.h
* @version V1.00
* $Revision: 3 $
* $Date: 15/06/11 4:13p $
* @brief Mini58 series GPIO driver header file
*
* @note
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __GPIO_H__
#define __GPIO_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
@{
*/
/** @addtogroup Mini58_GPIO_Driver GPIO Driver
@{
*/
/** @addtogroup Mini58_GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
@{
*/
#define GPIO_PIN_MAX 8 /*!< Specify Maximum Pins of Each GPIO Port */
/*---------------------------------------------------------------------------------------------------------*/
/* MODE Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode */
#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode */
#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */
#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */
/*---------------------------------------------------------------------------------------------------------*/
/* GPIO Interrupt Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */
#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */
#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */
#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */
#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */
/*---------------------------------------------------------------------------------------------------------*/
/* IMD Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_INTTYPE_EDGE 0UL /*!< INTTYPE Setting for Edge Trigger Mode */
#define GPIO_INTTYPE_LEVEL 1UL /*!< INTTYPE Setting for Edge Level Mode */
/*---------------------------------------------------------------------------------------------------------*/
/* DBNCECON Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< DBCTL setting for all IO pins edge detection circuit is always active after reset */
#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */
#define GPIO_DBCTL_DBCLKSRC_IRC10K 0x00000010UL /*!< DBCTL setting for de-bounce counter clock source is the internal 10 kHz */
#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< DBCTL setting for de-bounce counter clock source is the internal HCLK */
#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< DBCTL setting for sampling cycle = 1 clocks */
#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< DBCTL setting for sampling cycle = 2 clocks */
#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< DBCTL setting for sampling cycle = 4 clocks */
#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< DBCTL setting for sampling cycle = 8 clocks */
#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< DBCTL setting for sampling cycle = 16 clocks */
#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< DBCTL setting for sampling cycle = 32 clocks */
#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< DBCTL setting for sampling cycle = 64 clocks */
#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< DBCTL setting for sampling cycle = 128 clocks */
#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< DBCTL setting for sampling cycle = 256 clocks */
#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< DBCTL setting for sampling cycle = 512 clocks */
#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< DBCTL setting for sampling cycle = 1024 clocks */
#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< DBCTL setting for sampling cycle = 2048 clocks */
#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< DBCTL setting for sampling cycle = 4096 clocks */
#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< DBCTL setting for sampling cycle = 8192 clocks */
#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< DBCTL setting for sampling cycle = 16384 clocks */
#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< DBCTL setting for sampling cycle = 32768 clocks */
/** Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
* Example 1:
*
* P00 = 1;
*
* It is used to set P0.0 to high;
*
* Example 2:
*
* if (P00)
* P00 = 0;
*
* If P0.0 pin status is high, then set P0.0 data output to low.
*/
#define GPIO_PIN_ADDR(port, pin) (*((volatile uint32_t *)((GPIOBIT0_BASE+(0x20*(port))) + ((pin)<<2))))
#define P00 GPIO_PIN_ADDR(0, 0) /*!< Specify P00 Pin Data Input/Output */
#define P01 GPIO_PIN_ADDR(0, 1) /*!< Specify P01 Pin Data Input/Output */
#define P02 GPIO_PIN_ADDR(0, 2) /*!< Specify P02 Pin Data Input/Output */
#define P03 GPIO_PIN_ADDR(0, 3) /*!< Specify P03 Pin Data Input/Output */
#define P04 GPIO_PIN_ADDR(0, 4) /*!< Specify P04 Pin Data Input/Output */
#define P05 GPIO_PIN_ADDR(0, 5) /*!< Specify P05 Pin Data Input/Output */
#define P06 GPIO_PIN_ADDR(0, 6) /*!< Specify P06 Pin Data Input/Output */
#define P07 GPIO_PIN_ADDR(0, 7) /*!< Specify P07 Pin Data Input/Output */
#define P10 GPIO_PIN_ADDR(1, 0) /*!< Specify P10 Pin Data Input/Output */
#define P11 GPIO_PIN_ADDR(1, 1) /*!< Specify P11 Pin Data Input/Output */
#define P12 GPIO_PIN_ADDR(1, 2) /*!< Specify P12 Pin Data Input/Output */
#define P13 GPIO_PIN_ADDR(1, 3) /*!< Specify P13 Pin Data Input/Output */
#define P14 GPIO_PIN_ADDR(1, 4) /*!< Specify P14 Pin Data Input/Output */
#define P15 GPIO_PIN_ADDR(1, 5) /*!< Specify P15 Pin Data Input/Output */
#define P16 GPIO_PIN_ADDR(1, 6) /*!< Specify P16 Pin Data Input/Output */
#define P17 GPIO_PIN_ADDR(1, 7) /*!< Specify P17 Pin Data Input/Output */
#define P20 GPIO_PIN_ADDR(2, 0) /*!< Specify P20 Pin Data Input/Output */
#define P21 GPIO_PIN_ADDR(2, 1) /*!< Specify P21 Pin Data Input/Output */
#define P22 GPIO_PIN_ADDR(2, 2) /*!< Specify P22 Pin Data Input/Output */
#define P23 GPIO_PIN_ADDR(2, 3) /*!< Specify P23 Pin Data Input/Output */
#define P24 GPIO_PIN_ADDR(2, 4) /*!< Specify P24 Pin Data Input/Output */
#define P25 GPIO_PIN_ADDR(2, 5) /*!< Specify P25 Pin Data Input/Output */
#define P26 GPIO_PIN_ADDR(2, 6) /*!< Specify P26 Pin Data Input/Output */
#define P27 GPIO_PIN_ADDR(2, 7) /*!< Specify P27 Pin Data Input/Output */
#define P30 GPIO_PIN_ADDR(3, 0) /*!< Specify P30 Pin Data Input/Output */
#define P31 GPIO_PIN_ADDR(3, 1) /*!< Specify P31 Pin Data Input/Output */
#define P32 GPIO_PIN_ADDR(3, 2) /*!< Specify P32 Pin Data Input/Output */
#define P33 GPIO_PIN_ADDR(3, 3) /*!< Specify P33 Pin Data Input/Output */
#define P34 GPIO_PIN_ADDR(3, 4) /*!< Specify P34 Pin Data Input/Output */
#define P35 GPIO_PIN_ADDR(3, 5) /*!< Specify P35 Pin Data Input/Output */
#define P36 GPIO_PIN_ADDR(3, 6) /*!< Specify P36 Pin Data Input/Output */
#define P37 GPIO_PIN_ADDR(3, 7) /*!< Specify P37 Pin Data Input/Output */
#define P40 GPIO_PIN_ADDR(4, 0) /*!< Specify P40 Pin Data Input/Output */
#define P41 GPIO_PIN_ADDR(4, 1) /*!< Specify P41 Pin Data Input/Output */
#define P42 GPIO_PIN_ADDR(4, 2) /*!< Specify P42 Pin Data Input/Output */
#define P43 GPIO_PIN_ADDR(4, 3) /*!< Specify P43 Pin Data Input/Output */
#define P44 GPIO_PIN_ADDR(4, 4) /*!< Specify P44 Pin Data Input/Output */
#define P45 GPIO_PIN_ADDR(4, 5) /*!< Specify P45 Pin Data Input/Output */
#define P46 GPIO_PIN_ADDR(4, 6) /*!< Specify P46 Pin Data Input/Output */
#define P47 GPIO_PIN_ADDR(4, 7) /*!< Specify P47 Pin Data Input/Output */
#define P50 GPIO_PIN_ADDR(5, 0) /*!< Specify P50 Pin Data Input/Output */
#define P51 GPIO_PIN_ADDR(5, 1) /*!< Specify P51 Pin Data Input/Output */
#define P52 GPIO_PIN_ADDR(5, 2) /*!< Specify P52 Pin Data Input/Output */
#define P53 GPIO_PIN_ADDR(5, 3) /*!< Specify P53 Pin Data Input/Output */
#define P54 GPIO_PIN_ADDR(5, 4) /*!< Specify P54 Pin Data Input/Output */
#define P55 GPIO_PIN_ADDR(5, 5) /*!< Specify P55 Pin Data Input/Output */
/*@}*/ /* end of group Mini58_GPIO_EXPORTED_CONSTANTS */
/** @addtogroup Mini58_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
@{
*/
/**
* @brief Clear GPIO Pin Interrupt Flag
*
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
*
* @return None
*
* @details Clear the interrupt status of specified GPIO pin.
*/
#define GPIO_CLR_INT_FLAG(gpio, u32PinMask) ((gpio)->INTSRC = u32PinMask)
/**
* @brief Disable Pin De-bounce Function
*
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
*
* @return None
*
* @details Disable the interrupt de-bounce function of specified GPIO pin.
*/
#define GPIO_DISABLE_DEBOUNCE(gpio, u32PinMask) ((gpio)->DBEN &= ~u32PinMask)
/**
* @brief Enable Pin De-bounce Function
*
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
*
* @return None
*
* @details Enable the interrupt de-bounce function of specified GPIO pin.
*/
#define GPIO_ENABLE_DEBOUNCE(gpio, u32PinMask) ((gpio)->DBEN |= u32PinMask)
/**
* @brief Disable I/O Digital Input Path
*
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
*
* @return None
*
* @details Disable I/O digital input path of specified GPIO pin.
*/
#define GPIO_DISABLE_DIGITAL_PATH(gpio, u32PinMask) ((gpio)->DINOFF |= (u32PinMask << 16))
/**
* @brief Enable I/O Digital Input Path
*
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
*
* @return None
*
* @details Enable I/O digital input path of specified GPIO pin.
*/
#define GPIO_ENABLE_DIGITAL_PATH(gpio, u32PinMask) ((gpio)->DINOFF &= ~(u32PinMask << 16))
/**
* @brief Disable I/O DOUT mask
*
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
*
* @return None
*
* @details Disable I/O DOUT mask of specified GPIO pin.
*/
#define GPIO_DISABLE_DOUT_MASK(gpio, u32PinMask) ((gpio)->DATMSK &= ~u32PinMask)
/**
* @brief Enable I/O DOUT mask
*
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
*
* @return None
*
* @details Enable I/O DOUT mask of specified GPIO pin.
*/
#define GPIO_ENABLE_DOUT_MASK(gpio, u32PinMask) ((gpio)->DATMSK |= u32PinMask)
/**
* @brief Get GPIO Pin Interrupt Flag
*
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
*
* @retval 0 No interrupt at specified GPIO pin
* @retval 1 The specified GPIO pin generate an interrupt
*
* @details Get the interrupt status of specified GPIO pin.
*/
#define GPIO_GET_INT_FLAG(gpio, u32PinMask) ((gpio)->INTSRC & u32PinMask)
/**
* @brief Set De-bounce Sampling Cycle Time
*
* @param[in] clksrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_IRC10K.
* @param[in] clksel The de-bounce sampling cycle selection. It could be \n
* - \ref GPIO_DBCTL_DBCLKSEL_1, \ref GPIO_DBCTL_DBCLKSEL_2, \ref GPIO_DBCTL_DBCLKSEL_4, \ref GPIO_DBCTL_DBCLKSEL_8, \n
* - \ref GPIO_DBCTL_DBCLKSEL_16, \ref GPIO_DBCTL_DBCLKSEL_32, \ref GPIO_DBCTL_DBCLKSEL_64, \ref GPIO_DBCTL_DBCLKSEL_128, \n
* - \ref GPIO_DBCTL_DBCLKSEL_256, \ref GPIO_DBCTL_DBCLKSEL_512, \ref GPIO_DBCTL_DBCLKSEL_1024, \ref GPIO_DBCTL_DBCLKSEL_2048, \n
* - \ref GPIO_DBCTL_DBCLKSEL_4096, \ref GPIO_DBCTL_DBCLKSEL_8192, \ref GPIO_DBCTL_DBCLKSEL_16384, \ref GPIO_DBCTL_DBCLKSEL_32768.
*
* @return None
*
* @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
* Example: GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_IRC10K, GPIO_DBCTL_DBCLKSEL_4). \n
* It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
* Then the target de-bounce sampling cycle time is (2^4)*(1/(10*1000)) s = 16*0.0001 s = 1600 us,
* and system will sampling interrupt input once per 1600 us.
*/
#define GPIO_SET_DEBOUNCE_TIME(clksrc, clksel) (GPIO->DBCTL = (GP_DBCTL_ICLKON_Msk | clksrc | clksel))
/**
* @brief Get GPIO Port IN Data
*
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
*
* @retval The specified port data
*
* @details Get the PIN register of specified GPIO port.
*/
#define GPIO_GET_IN_DATA(gpio) ((gpio)->PIN)
/**
* @brief Set GPIO Port OUT Data
*
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
* @param[in] data GPIO port data.
*
* @retval None
*
* @details Set the Data into specified GPIO port.
*/
#define GPIO_SET_OUT_DATA(gpio, data) ((gpio)->DOUT = (data))
/**
* @brief Toggle Specified GPIO pin
*
* @param[in] u32Pin Pxy
*
* @retval None
*
* @details Toggle the specified GPIO pint.
*/
#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
/**
* @brief Enable External GPIO interrupt 0
*
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
* @param[in] u32Pin The pin of specified GPIO port.
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
* - \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
#define GPIO_EnableEINT0 GPIO_EnableInt
/**
* @brief Disable External GPIO interrupt 0
*
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
#define GPIO_DisableEINT0 GPIO_DisableInt
/**
* @brief Enable External GPIO interrupt 1
*
* @param[in] gpio GPIO port. It could \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
* @param[in] u32Pin The pin of specified GPIO port.
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
* - \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
#define GPIO_EnableEINT1 GPIO_EnableInt
/**
* @brief Disable External GPIO interrupt 1
*
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
*
* @return None
*
* @details This function is used to enable specified GPIO pin interrupt.
*/
#define GPIO_DisableEINT1 GPIO_DisableInt
void GPIO_SetMode(GPIO_T *gpio, uint32_t u32PinMask, uint32_t u32Mode);
void GPIO_EnableInt(GPIO_T *gpio, uint32_t u32Pin, uint32_t u32IntAttribs);
void GPIO_DisableInt(GPIO_T *gpio, uint32_t u32Pin);
/*@}*/ /* end of group Mini58_GPIO_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group Mini58_GPIO_Driver */
/*@}*/ /* end of group Mini58_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__GPIO_H__
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
PAN159/PAN159-Template/Library/StdDriver/inc/i2c.h
+212
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@@ -0,0 +1,212 @@
/**************************************************************************//**
* @file i2c.h
* @version V1.00
* $Revision: 7 $
* $Date: 15/12/31 1:36p $
* @brief Mini58 series I2C driver header file
*
* @note
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __I2C_H__
#define __I2C_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
@{
*/
/** @addtogroup Mini58_I2C_Driver I2C Driver
@{
*/
/** @addtogroup Mini58_I2C_EXPORTED_CONSTANTS I2C Exported Constants
@{
*/
#define I2C_STA 0x20 /*!< I2C START */
#define I2C_STO 0x10 /*!< I2C STOP */
#define I2C_SI 0x08 /*!< I2C SI */
#define I2C_AA 0x04 /*!< I2C ACK */
/*@}*/ /* end of group Mini58_I2C_EXPORTED_CONSTANTS */
/** @addtogroup Mini58_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
@{
*/
/**
* @brief This macro sets the I2C control register at one time.
* @param[in] i2c is the base address of I2C module.
* @param[in] u8Ctrl is the register value of I2C control register.
* @return none
*/
#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ( (i2c)->CTL = ((i2c)->CTL & ~0x3c) | u8Ctrl )
/**
* @brief This macro only set START bit to the control register of I2C module.
* @param[in] i2c is the base address of I2C module.
* @return none
*/
#define I2C_START(i2c) ( (i2c)->CTL = ((i2c)->CTL & ~I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk )
/**
* @brief This macro only set STOP bit to the control register of I2C module.
* @param[in] i2c is the base address of I2C module.
* @return none
*/
#define I2C_STOP(i2c) \
do { \
(i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk); \
while((i2c)->CTL & I2C_CTL_STO_Msk); \
} while(0)
/**
* @brief This macro will return when I2C module is ready.
* @param[in] i2c is the base address of I2C module.
* @return none
*/
#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL & I2C_CTL_SI_Msk))
/**
* @brief This macro disables the FIFO function.
* @param[in] i2c is the base address of I2C module.
* @return none
*/
#define I2C_DISABLE_FIFO(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_TWOLVFIFO_Msk )
/**
* @brief This macro enables the FIFO function.
* @param[in] i2c is the base address of I2C module.
* @return none
*/
#define I2C_ENABLE_FIFO(i2c) ( (i2c)->CTL1 |= I2C_CTL1_TWOLVFIFO_Msk )
/**
* @brief This macro disables clock stretch function.
* @param[in] i2c is the base address of I2C module.
* @return none
*/
#define I2C_DISABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_NSTRETCH_Msk )
/**
* @brief This macro enables clock stretch function.
* @param[in] i2c is the base address of I2C module.
* @return none
*/
#define I2C_ENABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 |= I2C_CTL1_NSTRETCH_Msk )
/**
* @brief This macro disables over-run interrupt.
* @param[in] i2c is the base address of I2C module.
* @return none
*/
#define I2C_DISABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_OVIEN_Msk )
/**
* @brief This macro enables over-run interrupt.
* @param[in] i2c is the base address of I2C module.
* @return none
*/
#define I2C_ENABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_OVIEN_Msk )
/**
* @brief This macro enables under-run interrupt.
* @param[in] i2c is the base address of I2C module.
* @return none
*/
#define I2C_ENABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_URIEN_Msk )
/**
* @brief This macro disables under-run interrupt.
* @param[in] i2c is the base address of I2C module.
* @return none
*/
#define I2C_DISABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_URIEN_Msk )
/**
* @brief This macro returns the data stored in data register of I2C module.
* @param[in] i2c is the base address of I2C module.
* @return Data.
*/
#define I2C_GET_DATA(i2c) ( (i2c)->DAT )
/**
* @brief This macro writes the data to data register of I2C module.
* @param[in] i2c is the base address of I2C module.
* @param[in] u8Data is the data which will be write to data register of I2C module.
* @return none
*/
#define I2C_SET_DATA(i2c, u8Data) ( (i2c)->DAT = u8Data )
/**
* @brief This macro returns the status of I2C module.
* @param[in] i2c is the base address of I2C module.
* @return Status.
*/
#define I2C_GET_STATUS(i2c) ( (i2c)->STATUS )
/**
* @brief This macro returns timeout flag.
* @param[in] i2c is the base address of I2C module.
* @return Status.
* @retval 0 Flag is not set.
* @retval 1 Flag is set.
*/
#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
/**
* @brief This macro returns wakeup flag.
* @param[in] i2c is the base address of I2C module.
* @return Status.
* @retval 0 Flag is not set.
* @retval 1 Flag is set.
*/
#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->STATUS1 & I2C_STATUS1_WKIF_Msk) == I2C_STATUS1_WKIF_Msk ? 1:0 )
/**
* @brief This macro clears wakeup flag.
* @param[in] i2c is the base address of I2C module.
* @return none
*/
#define I2C_CLEAR_WAKEUP_FLAG(i2c) ( (i2c)->STATUS1 = I2C_STATUS1_WKIF_Msk )
uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
void I2C_Close(I2C_T *i2c);
void I2C_ClearTimeoutFlag(I2C_T *i2c);
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
void I2C_DisableInt(I2C_T *i2c);
void I2C_EnableInt(I2C_T *i2c);
uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
uint32_t I2C_GetIntFlag(I2C_T *i2c);
uint32_t I2C_GetStatus(I2C_T *i2c);
uint32_t I2C_GetData(I2C_T *i2c);
void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
void I2C_DisableTimeout(I2C_T *i2c);
void I2C_EnableWakeup(I2C_T *i2c);
void I2C_DisableWakeup(I2C_T *i2c);
/*@}*/ /* end of group Mini58_I2C_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group Mini58_I2C_Driver */
/*@}*/ /* end of group Mini58_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__I2C_H__
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
PAN159/PAN159-Template/Library/StdDriver/inc/pwm.h
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/**************************************************************************//**
* @file pwm.h
* @version V1.00
* $Revision: 6 $
* $Date: 15/06/05 1:41p $
* @brief Mini58 series PWM driver header file
*
* @note
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __PWM_H__
#define __PWM_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
@{
*/
/** @addtogroup Mini58_PWM_Driver PWM Driver
@{
*/
/** @addtogroup Mini58_PWM_EXPORTED_CONSTANTS PWM Exported Constants
@{
*/
#define PWM_CHANNEL_NUM (6) /*!< PWM channel number */
#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 */
#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 */
#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 */
#define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 */
#define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 */
#define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type */
#define PWM_CENTER_ALIGNED (PWM_CTL_CNTTYPE_Msk) /*!< PWM working in center aligned type */
#define PWM_TRIGGER_ADC_CNTR_IS_0 PWM_ADCTCTL0_ZPTRGEN0_Msk /*!< PWM trigger ADC while counter matches 0 */
#define PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_ADCTCTL0_CDTRGEN0_Msk /*!< PWM trigger ADC while counter matches CMR during down count */
#define PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_ADCTCTL0_CPTRGEN0_Msk /*!< PWM trigger ADC while counter matches CNR */
#define PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_ADCTCTL0_CUTRGEN0_Msk /*!< PWM trigger ADC while counter matches CMR during up count */
#define PWM_FB0_EINT0 (PWM_BRKCTL_BRK0EN_Msk) /*!< External interrupt 0 as fault brake 0 source */
#define PWM_FB0_ACMP1 (PWM_BRKCTL_BRK0EN_Msk | PWM_BRKCTL_BRK1SEL_Msk) /*!< Comparator 1 as fault brake 0 source */
#define PWM_FB1_EINT1 (PWM_BRKCTL_BRK1EN_Msk) /*!< External interrupt 1 as fault brake 1 source */
#define PWM_FB1_ACMP0 (PWM_BRKCTL_BRK1EN_Msk | PWM_BRKCTL_BRK0SEL_Msk) /*!< Comparator 0 as fault brake 1 source */
#define PWM_PERIOD_INT_UNDERFLOW (0) /*!< PWM period interrupt trigger if counter underflow */
#define PWM_PERIOD_INT_MATCH_CNR (PWM_INTEN_PINTTYPE_Msk) /*!< PWM period interrupt trigger if counter match CNR */
/*---------------------------------------------------------------------------------------------------------*/
/* PWM Group channel number constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define PWM_CH0 0x0 /*!< PWM channel 0 */
#define PWM_CH1 0x1 /*!< PWM channel 1 */
#define PWM_CH2 0x2 /*!< PWM channel 2 */
#define PWM_CH3 0x3 /*!< PWM channel 3 */
#define PWM_CH4 0x4 /*!< PWM channel 4 */
#define PWM_CH5 0x5 /*!< PWM channel 5 */
/*@}*/ /* end of group Mini58_PWM_EXPORTED_CONSTANTS */
/** @addtogroup Mini58_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
@{
*/
/**
* @brief This macro enable complementary mode
* @param[in] pwm The base address of PWM module
* @return None
* \hideinitializer
*/
#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (PWM->CTL & ~PWM_CTL_MODE_Msk) |(1UL << PWM_CTL_MODE_Pos))
/**
* @brief This macro disable complementary mode, and enable independent mode.
* @param[in] pwm The base address of PWM module
* @return None
* \hideinitializer
*/
#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
/**
* @brief This macro enable group mode
* @param[in] pwm The base address of PWM module
* @return None
* \hideinitializer
*/
#define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL |= PWM_CTL_GROUPEN_Msk)
/**
* @brief This macro disable group mode
* @param[in] pwm The base address of PWM module
* @return None
* \hideinitializer
*/
#define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_GROUPEN_Msk)
/**
* @brief This macro enable synchronous mode
* @param[in] pwm The base address of PWM module
* @return None
* \hideinitializer
*/
#define PWM_ENABLE_SYNC_MODE(pwm) (PWM->CTL = ((pwm)->CTL & ~PWM_CTL_MODE_Msk) |(2UL << PWM_CTL_MODE_Pos))
/**
* @brief This macro disable synchronous mode, and enable independent mode.
* @param[in] pwm The base address of PWM module
* @return None
* \hideinitializer
*/
#define PWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
/**
* @brief This macro enable output inverter of specified channel(s)
* @param[in] pwm The base address of PWM module
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
* Bit 0 represents channel 0, bit 1 represents channel 1...
* @return None
* \hideinitializer
*/
#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) \
do{ \
int i;\
(pwm)->CTL &= ~(PWM_CTL_PINV0_Msk|PWM_CTL_PINV1_Msk|PWM_CTL_PINV2_Msk|PWM_CTL_PINV3_Msk|PWM_CTL_PINV4_Msk|PWM_CTL_PINV5_Msk);\
for(i = 0; i < 6; i++) { \
if((u32ChannelMask) & (1 << i)) \
(pwm)->CTL |= (1 << (PWM_CTL_PINV0_Pos + (i * 4))); \
} \
}while(0)
/**
* @brief This macro set the prescaler of the selected channel
* @param[in] pwm The base address of PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF
* @return None
* @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
* channel 1 will also be affected.
* \hideinitializer
*/
#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
((pwm)->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
/**
* @brief This macro set the divider of the selected channel
* @param[in] pwm The base address of PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32Divider Clock divider of specified channel. Valid values are
* - \ref PWM_CLK_DIV_1
* - \ref PWM_CLK_DIV_2
* - \ref PWM_CLK_DIV_4
* - \ref PWM_CLK_DIV_8
* - \ref PWM_CLK_DIV_16
* @return None
* \hideinitializer
*/
#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
/**
* @brief This macro set the duty of the selected channel
* @param[in] pwm The base address of PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
* @return None
* @note This new setting will take effect on next PWM period
* \hideinitializer
*/
#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4)))= (u32CMR))
/**
* @brief This macro set the period of the selected channel
* @param[in] pwm The base address of PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
* @return None
* @note This new setting will take effect on next PWM period
* @note PWM counter will stop if period length set to 0
* \hideinitializer
*/
#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = (u32CNR))
/**
* @brief This macro set the duty of the selected channel for PWM asymmetric Mode
* @param[in] pwm The base address of PWM module
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
* @param[in] u32CMRD Down counter in Asymmetric Mode. Valid values are between 0~0xFFFF
* @return None
* @note This new setting will take effect on next PWM period
* \hideinitializer
*/
#define PWM_SET_CMRD(pwm, u32ChannelNum, u32CMRD) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + (u32ChannelNum) * 4)))= (u32CMRD << 16))
/**
* @brief This macro set the PWM aligned type
* @param[in] pwm The base address of PWM module
* @param[in] u32ChannelMask This parameter is not used
* @param[in] u32AlignedType PWM aligned type, valid values are:
* - \ref PWM_EDGE_ALIGNED
* - \ref PWM_CENTER_ALIGNED
* @return None
* \hideinitializer
*/
#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
((pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk) | (u32AlignedType))
/**
* @brief This macro enables PWM asymmetric mode
* @param[in] pwm The base address of PWM module
* @return None
* \hideinitializer
*/
#define PWM_ENABLE_ASYMMETRIC_MODE(pwm) ((pwm)->CTL |= PWM_CTL_ASYMEN_Msk)
/**
* @brief This macro enables PWM Precise Center-Aligned Type
* @param[in] pwm The base address of PWM module
* @return None
* \hideinitializer
*/
#define PWM_ENABLE_PCAEN(pwm) (PWM->PCACTL |= PWM_PCACTL_PCAEN_Msk)
uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
uint32_t u32ChannelNum,
uint32_t u32Frequency,
uint32_t u32DutyCycle);
void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
void PWM_EnableFaultBrake(PWM_T *pwm,
uint32_t u32ChannelMask,
uint32_t u32LevelMask,
uint32_t u32BrakeSource);
void PWM_ClearFaultBrakeFlag(PWM_T *pwm, uint32_t u32BrakeSource);
void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_EnableCenterInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
void PWM_DisableCenterInt(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_ClearCenterIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
uint32_t PWM_GetCenterIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_EnableRiseInt(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_DisableRiseInt(PWM_T *pwm, uint32_t u32ChannelNum);
void PWM_ClearRiseIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
uint32_t PWM_GetRiseIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
/*@}*/ /* end of group Mini58_PWM_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group Mini58_PWM_Driver */
/*@}*/ /* end of group Mini58_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__PWM_H__
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
PAN159/PAN159-Template/Library/StdDriver/inc/spi.h
+258
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/**************************************************************************//**
* @file spi.h
* @version V1.00
* $Revision: 3 $
* $Date: 15/04/17 11:45a $
* @brief Mini58 series SPI driver header file
*
* @note
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SPI_H__
#define __SPI_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
@{
*/
/** @addtogroup Mini58_SPI_Driver SPI Driver
@{
*/
/** @addtogroup Mini58_SPI_EXPORTED_CONSTANTS SPI Exported Constants
@{
*/
#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKP=0; RX_NEG=0; TX_NEG=1 */
#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKP=0; RX_NEG=1; TX_NEG=0 */
#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKP=1; RX_NEG=1; TX_NEG=0 */
#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKP=1; RX_NEG=0; TX_NEG=1 */
#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */
#define SPI_MASTER (0x0) /*!< Set as master */
#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS0 */
#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */
#define SPI_SS_ACTIVE_LOW (0x0) /*!< SS active low */
#define SPI_IE_MASK (0x01) /*!< Interrupt enable mask */
#define SPI_SSTA_INTEN_MASK (0x04) /*!< Slave 3-Wire mode start interrupt enable mask */
#define SPI_FIFO_TX_INTEN_MASK (0x08) /*!< FIFO TX interrupt mask */
#define SPI_FIFO_RX_INTEN_MASK (0x10) /*!< FIFO RX interrupt mask */
#define SPI_FIFO_RXOV_INTEN_MASK (0x20) /*!< FIFO RX overrun interrupt mask */
#define SPI_FIFO_TIMEOUT_INTEN_MASK (0x40) /*!< FIFO timeout interrupt mask */
/*@}*/ /* end of group Mini58_SPI_EXPORTED_CONSTANTS */
/** @addtogroup Mini58_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
@{
*/
/**
* @brief Abort the current transfer in slave 3-wire mode.
* @param[in] spi is the base address of SPI module.
* @return none
*/
#define SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLVABT_Msk )
/**
* @brief Clear the slave 3-wire mode start interrupt flag.
* @param[in] spi is the base address of SPI module.
* @return none
*/
#define SPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLVSTIF_Msk )
/**
* @brief Clear the unit transfer interrupt flag.
* @param[in] spi is the base address of SPI module.
* @return none
*/
#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )
/**
* @brief Disable slave 3-wire mode.
* @param[in] spi is the base address of SPI module.
* @return none
*/
#define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL &= ~SPI_SLVCTL_SLV3WIRE_Msk )
/**
* @brief Enable slave 3-wire mode.
* @param[in] spi is the base address of SPI module.
* @return none
*/
#define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLV3WIRE_Msk )
/**
* @brief Get the count of available data in RX FIFO.
* @param[in] spi is the base address of SPI module.
* @return The count of available data in RX FIFO.
*/
#define SPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) & 0xf )
/**
* @brief Get the Rx FIFO empty flag.
* @param[in] spi is the base address of SPI module.
* @return Rx FIFO flag
* @retval 0 Rx FIFO is not empty
* @retval 1 Rx FIFO is empty
*/
#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) == SPI_STATUS_RXEMPTY_Msk ? 1:0 )
/**
* @brief Get the Tx FIFO empty flag.
* @param[in] spi is the base address of SPI module.
* @return Tx FIFO flag
* @retval 0 Tx FIFO is not empty
* @retval 1 Tx FIFO is empty
*/
#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) == SPI_STATUS_TXEMPTY_Msk ? 1:0 )
/**
* @brief Get the Tx FIFO full flag.
* @param spi is the base address of SPI module.
* @return Tx FIFO flag
* @retval 0 Tx FIFO is not full
* @retval 1 Tx FIFO is full
*/
#define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) == SPI_STATUS_TXFULL_Msk ? 1:0 )
/**
* @brief Get the datum read from Rx FIFO.
* @param[in] spi is the base address of SPI module.
* @return Data in Rx buffer
*/
#define SPI_READ_RX(spi) ( (spi)->RX )
/**
* @brief Write datum to TX register.
* @param[in] spi is the base address of SPI module.
* @param[in] u32TxData is the datum which user attempt to transfer through SPI bus.
* @return none
*/
#define SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = u32TxData )
/**
* @brief Disable automatic slave select function and set SPI_SS pin to high state.
* @param[in] spi is the base address of SPI module.
* @return none
*/
static __INLINE void SPI_SET_SS_HIGH(SPI_T *spi)
{
spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
spi->SSCTL |= (SPI_SSCTL_LTF_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk);
}
/**
* @brief Disable automatic slave select function and set SPI_SS pin to low state.
* @param[in] spi is the base address of SPI module.
* @return none
*/
static __INLINE void SPI_SET_SS_LOW(SPI_T *spi)
{
spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
spi->SSCTL |= SPI_SSCTL_LTF_Msk;
spi->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk;
spi->SSCTL |= SPI_SSCTL_SS_Msk;
}
/**
* @brief Enable byte reorder function.
* @param[in] spi is the base address of SPI module.
* @return none
*/
#define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
/**
* @brief Disable byte reorder function.
* @param[in] spi is the base address of SPI module.
* @return none
*/
#define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
/**
* @brief Set the length of suspend interval.
* @param[in] spi is the base address of SPI module.
* @param[in] u32SuspCycle decides the length of suspend interval.
* @return none
*/
#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | (u32SuspCycle << SPI_CTL_SUSPITV_Pos) )
/**
* @brief Set the SPI transfer sequence with LSB first.
* @param[in] spi is the base address of SPI module.
* @return none
*/
#define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
/**
* @brief Set the SPI transfer sequence with MSB first.
* @param[in] spi is the base address of SPI module.
* @return none
*/
#define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
/**
* @brief Set the data width of a SPI transaction.
* @param[in] spi is the base address of SPI module.
* @param[in] u32Width is the bit width of transfer data.
* @return none
*/
static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
{
if(u32Width == 32)
u32Width = 0;
spi->CTL = (spi->CTL & ~SPI_CTL_DWIDTH_Msk) | (u32Width << SPI_CTL_DWIDTH_Pos);
}
/**
* @brief Get the SPI busy state.
* @param[in] spi is the base address of SPI module.
* @return SPI busy status
* @retval 0 SPI module is not busy
* @retval 1 SPI module is busy
*/
#define SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_SPIEN_Msk) == SPI_CTL_SPIEN_Msk ? 1:0 )
/**
* @brief Set the GO_BUSY bit to trigger SPI transfer.
* @param[in] spi is the base address of SPI module.
* @return none
*/
#define SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
void SPI_Close(SPI_T *spi);
void SPI_ClearRxFIFO(SPI_T *spi);
void SPI_ClearTxFIFO(SPI_T *spi);
void SPI_DisableAutoSS(SPI_T *spi);
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
void SPI_DisableFIFO(SPI_T *spi);
uint32_t SPI_GetBusClock(SPI_T *spi);
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
/*@}*/ /* end of group Mini58_SPI_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group Mini58_SPI_Driver */
/*@}*/ /* end of group Mini58_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__SPI_H__
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
PAN159/PAN159-Template/Library/StdDriver/inc/sys.h
+462
View File
@@ -0,0 +1,462 @@
/**************************************************************************//**
* @file sys.h
* @version V1.00
* $Revision: 15 $
* $Date: 15/06/04 5:18p $
* @brief Mini58 series SYS driver header file
*
* @note
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SYS_H__
#define __SYS_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
@{
*/
/** @addtogroup Mini58_SYS_Driver SYS Driver
@{
*/
/** @addtogroup Mini58_SYS_EXPORTED_CONSTANTS SYS Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* Module Reset Control Resister constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define ADC_RST ((0x4<<24) | SYS_IPRST1_ADCRST_Pos ) /*!< ADC reset is one of the SYS_ResetModule parameter */
#define ACMP_RST ((0x4<<24) | SYS_IPRST1_ACMPRST_Pos ) /*!< ACMP reset is one of the SYS_ResetModule parameter */
#define PWM0_RST ((0x4<<24) | SYS_IPRST1_PWM0RST_Pos ) /*!< PWM reset is one of the SYS_ResetModule parameter */
#define UART0_RST ((0x4<<24) | SYS_IPRST1_UART0RST_Pos ) /*!< UART0 reset is one of the SYS_ResetModule parameter */
#define UART1_RST ((0x4<<24) | SYS_IPRST1_UART1RST_Pos ) /*!< UART1 reset is one of the SYS_ResetModule parameter */
#define SPI0_RST ((0x4<<24) | SYS_IPRST1_SPI0RST_Pos ) /*!< SPI reset is one of the SYS_ResetModule parameter */
#define I2C0_RST ((0x4<<24) | SYS_IPRST1_I2C0RST_Pos ) /*!< I2C0 reset is one of the SYS_ResetModule parameter */
#define I2C1_RST ((0x4<<24) | SYS_IPRST1_I2C1RST_Pos ) /*!< I2C1 reset is one of the SYS_ResetModule parameter */
#define TMR1_RST ((0x4<<24) | SYS_IPRST1_TMR1RST_Pos ) /*!< TMR1 reset is one of the SYS_ResetModule parameter */
#define TMR0_RST ((0x4<<24) | SYS_IPRST1_TMR0RST_Pos ) /*!< TMR0 reset is one of the SYS_ResetModule parameter */
#define GPIO_RST ((0x4<<24) | SYS_IPRST1_GPIORST_Pos ) /*!< GPIO reset is one of the SYS_ResetModule parameter */
/*---------------------------------------------------------------------------------------------------------*/
/* Brown Out Detector Threshold Voltage Selection constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable */
#define SYS_BODCTL_BOD_INTERRUPT_EN (0UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable */
#define SYS_BODCTL_BODVL_4_4V (3UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 4.4V */
#define SYS_BODCTL_BODVL_3_7V (2UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.7V */
#define SYS_BODCTL_BODVL_2_7V (1UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.7V */
#define SYS_BODCTL_BODVL_2_2V (0UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V */
/*---------------------------------------------------------------------------------------------------------*/
/* Multi-Function constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/
#define SYS_MFP_TYPE_Msk(bit) (1UL << ((bit) +16)) /*!< TYPE mask for Multiple Function Port */
#define SYS_MFP_ALT_Msk(bit) (1UL << ((bit) + 8)) /*!< ALT mask for Multiple Function Port */
#define SYS_MFP_MFP_Msk(bit) (1UL << ((bit) )) /*!< MFP mask for Multiple Function Port */
#define SYS_MFP_P00_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P00_UART0_nCTS 0x00000100UL /*!< Clear to Send input pin for UART0. */
#define SYS_MFP_P00_UART0_TXD 0x00000101UL /*!< Data transmitter output pin for UART0. */
#define SYS_MFP_P00_Msk 0x00000101UL /*!< P0_MFP pin 0 mask */
#define SYS_MFP_P01_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P01_SPI0_SS 0x00000002UL /*!< 1st SPI0 slave select pin. */
#define SYS_MFP_P01_UART0_nRTS 0x00000200UL /*!< Request to Send output pin for UART0. */
#define SYS_MFP_P01_UART0_RXD 0x00000202UL /*!< Data receiver input pin for UART0. */
#define SYS_MFP_P01_Msk 0x00000202UL /*!< P0_MFP pin 1 mask */
#define SYS_MFP_P04_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P04_PWM0_CH5 0x00001010UL /*!< PWM0 channel5 output/capture input. */
#define SYS_MFP_P04_SPI0_SS 0x00001000UL /*!< 1st SPI0 slave select pin. */
#define SYS_MFP_P04_Msk 0x00001010UL /*!< P0_MFP pin 4 mask */
#define SYS_MFP_P05_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P05_PWM0_CH4 0x00002020UL /*!< PWM0 channel4 output/capture input. */
#define SYS_MFP_P05_SPI0_MOSI 0x00002000UL /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. */
#define SYS_MFP_P05_Msk 0x00002020UL /*!< P0_MFP pin 5 mask */
#define SYS_MFP_P06_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P06_PWM0_CH1 0x00004040UL /*!< PWM0 channel1 output/capture input. */
#define SYS_MFP_P06_SPI0_MISO 0x00004000UL /*!< 1st SPI0 MISO (Master In, Slave Out) pin. */
#define SYS_MFP_P06_Msk 0x00004040UL /*!< P0_MFP pin 6 mask */
#define SYS_MFP_P07_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P07_PWM0_CH0 0x00008080UL /*!< PWM0 channel0 output/capture input. */
#define SYS_MFP_P07_SPI0_CLK 0x00008000UL /*!< SPI0 serial clock pin. */
#define SYS_MFP_P07_Msk 0x00008080UL /*!< P0_MFP pin 7 mask */
#define SYS_MFP_P10_ACMP0_P1 0x00000101UL /*!< Analog comparator0 positive input pin. */
#define SYS_MFP_P10_ADC_CH1 0x00000001UL /*!< ADC channel1 analog input. */
#define SYS_MFP_P10_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P10_Msk 0x00000101UL /*!< P1_MFP pin 0 mask */
#define SYS_MFP_P12_ACMP0_P2 0x00000404UL /*!< Analog comparator0 positive input pin. */
#define SYS_MFP_P12_ADC_CH2 0x00000004UL /*!< ADC channel2 analog input. */
#define SYS_MFP_P12_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P12_UART0_RXD 0x00000400UL /*!< Data receiver input pin for UART0. */
#define SYS_MFP_P12_PWM0_CH0 0x04000000UL /*!< PWM0 channel0 output/capture input. */
#define SYS_MFP_P12_Msk 0x04000404UL /*!< P1_MFP pin 2 mask */
#define SYS_MFP_P13_ACMP0_P3 0x00000808UL /*!< Analog comparator0 positive input pin. */
#define SYS_MFP_P13_ADC_CH3 0x00000008UL /*!< ADC channel3 analog input. */
#define SYS_MFP_P13_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P13_UART0_TXD 0x00000800UL /*!< Data transmitter output pin for UART0. */
#define SYS_MFP_P13_PWM0_CH1 0x08000000UL /*!< PWM0 channel1 output/capture input. */
#define SYS_MFP_P13_Msk 0x08000808UL /*!< P1_MFP pin 3 mask */
#define SYS_MFP_P14_ACMP0_N 0x00001010UL /*!< Analog comparator0 negative input pin. */
#define SYS_MFP_P14_ADC_CH4 0x00000010UL /*!< ADC channel4 analog input. */
#define SYS_MFP_P14_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P14_UART1_RXD 0x00001000UL /*!< Data receiver input pin for UART1. */
#define SYS_MFP_P14_PWM0_CH4 0x10000000UL /*!< PWM0 channel4 output/capture input. */
#define SYS_MFP_P14_Msk 0x10001010UL /*!< P1_MFP pin 4 mask */
#define SYS_MFP_P15_ACMP0_P0 0x00002020UL /*!< Analog comparator0 positive input pin. */
#define SYS_MFP_P15_ADC_CH5 0x00000020UL /*!< ADC channel5 analog input. */
#define SYS_MFP_P15_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P15_UART1_TXD 0x00002000UL /*!< Data transmitter output pin for UART1. */
#define SYS_MFP_P15_Msk 0x00002020UL /*!< P1_MFP pin 5 mask */
#define SYS_MFP_P22_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P22_I2C1_SCL 0x00000404UL /*!< I2C1 clock pin. */
#define SYS_MFP_P22_PWM0_CH0 0x00000400UL /*!< PWM0 channel0 output/capture input. */
#define SYS_MFP_P22_Msk 0x00000404UL /*!< P2_MFP pin 2 mask */
#define SYS_MFP_P23_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P23_I2C1_SDA 0x00000808UL /*!< I2C1 data input/output pin. */
#define SYS_MFP_P23_PWM0_CH1 0x00000800UL /*!< PWM0 channel1 output/capture input. */
#define SYS_MFP_P23_Msk 0x00000808UL /*!< P2_MFP pin 3 mask */
#define SYS_MFP_P24_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P24_PWM0_CH2 0x00001000UL /*!< PWM0 channel2 output/capture input. */
#define SYS_MFP_P24_UART1_RXD 0x00000010UL /*!< Data receiver input pin for UART1. */
#define SYS_MFP_P24_Msk 0x00001010UL /*!< P2_MFP pin 4 mask */
#define SYS_MFP_P25_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P25_PWM0_CH3 0x00002000UL /*!< PWM0 channel3 output/capture input. */
#define SYS_MFP_P25_UART1_TXD 0x00000020UL /*!< Data transmitter output pin for UART1. */
#define SYS_MFP_P25_Msk 0x00002020UL /*!< P2_MFP pin 5 mask */
#define SYS_MFP_P26_ACMP1_O 0x00004040UL /*!< Analog ccomparator1 output. */
#define SYS_MFP_P26_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P26_PWM0_CH4 0x00004000UL /*!< PWM0 channel4 output/capture input. */
#define SYS_MFP_P26_Msk 0x00004040UL /*!< P2_MFP pin 6 mask */
#define SYS_MFP_P30_ACMP1_N 0x00000100UL /*!< Analog comparator1 negative input pin. */
#define SYS_MFP_P30_ADC_CH6 0x00000101UL /*!< ADC channel6 analog input. */
#define SYS_MFP_P30_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P30_Msk 0x00000101UL /*!< P3_MFP pin 0 mask */
#define SYS_MFP_P31_ACMP1_P0 0x00000200UL /*!< Analog comparator1 positive input pin. */
#define SYS_MFP_P31_ADC_CH7 0x00000202UL /*!< ADC channel7 analog input. */
#define SYS_MFP_P31_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P31_Msk 0x00000202UL /*!< P3_MFP pin 1 mask */
#define SYS_MFP_P32_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P32_INT0 0x00000004UL /*!< External interrupt0 input pin. */
#define SYS_MFP_P32_STADC 0x00000404UL /*!< ADC external trigger input. */
#define SYS_MFP_P32_TM0_EXT 0x00000400UL /*!< Timer0 external capture input. */
#define SYS_MFP_P32_ACMP1_P1 0x04000000UL /*!< Analog comparator1 positive input pin. */
#define SYS_MFP_P32_Msk 0x04000404UL /*!< P3_MFP pin 2 mask */
#define SYS_MFP_P34_ACMP1_P2 0x00001010UL /*!< Analog comparator1 positive input pin. */
#define SYS_MFP_P34_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P34_I2C0_SDA 0x00001000UL /*!< I2C0 data input/output pin. */
#define SYS_MFP_P34_TM0_CNT_OUT 0x00000010UL /*!< Timer0 event counter input/toggle output. */
#define SYS_MFP_P34_Msk 0x00001010UL /*!< P3_MFP pin 4 mask */
#define SYS_MFP_P35_ACMP1_P3 0x00002020UL /*!< Analog comparator1 positive input pin. */
#define SYS_MFP_P35_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P35_I2C0_SCL 0x00002000UL /*!< I2C0 clock pin. */
#define SYS_MFP_P35_TM1_CNT_OUT 0x00000020UL /*!< Timer1 event counter input/toggle output. */
#define SYS_MFP_P35_Msk 0x00002020UL /*!< P3_MFP pin 5 mask */
#define SYS_MFP_P36_ACMP0_O 0x00004040UL /*!< Analog ccomparator0 output. */
#define SYS_MFP_P36_CLKO 0x00004000UL /*!< Clock output. */
#define SYS_MFP_P36_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P36_TM1_EXT 0x00000040UL /*!< Timer1 external capture input. */
#define SYS_MFP_P36_Msk 0x00004040UL /*!< P3_MFP pin 6 mask */
#define SYS_MFP_P46_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P46_ICE_CLK 0x00000040UL /*!< Serial wired debugger clock pin. */
#define SYS_MFP_P46_UART1_RXD 0x00004000UL /*!< Data receiver input pin for UART1. */
#define SYS_MFP_P46_Msk 0x00004040UL /*!< P4_MFP pin 6 mask */
#define SYS_MFP_P47_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P47_ICE_DAT 0x00000080UL /*!< Serial wired debugger data pin. */
#define SYS_MFP_P47_UART1_TXD 0x00008000UL /*!< Data transmitter output pin for UART1. */
#define SYS_MFP_P47_Msk 0x00008080UL /*!< P4_MFP pin 7 mask */
#define SYS_MFP_P50_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P50_I2C1_SDA 0x00000100UL /*!< I2C1 data input/output pin. */
#define SYS_MFP_P50_UART0_TXD 0x00000101UL /*!< Data transmitter output pin for UART0. */
#define SYS_MFP_P50_XT1_IN 0x00000001UL /*!< External 4~24 MHz (high speed) crystal input pin. */
#define SYS_MFP_P50_Msk 0x00000101UL /*!< P5_MFP pin 0 mask */
#define SYS_MFP_P51_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P51_I2C1_SCL 0x00000200UL /*!< I2C1 clock pin. */
#define SYS_MFP_P51_UART0_RXD 0x00000202UL /*!< Data receiver input pin for UART0. */
#define SYS_MFP_P51_XT1_OUT 0x00000002UL /*!< External 4~24 MHz (high speed) crystal output pin. */
#define SYS_MFP_P51_Msk 0x00000202UL /*!< P5_MFP pin 1 mask */
#define SYS_MFP_P52_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P52_INT1 0x00000004UL /*!< External interrupt1 input pin. */
#define SYS_MFP_P52_Msk 0x00000404UL /*!< P5_MFP pin 2 mask */
#define SYS_MFP_P53_ADC_CH0 0x00000008UL /*!< ADC channel0 analog input. */
#define SYS_MFP_P53_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P53_Msk 0x00000808UL /*!< P5_MFP pin 3 mask */
#define SYS_MFP_P54_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P54_Msk 0x00001010UL /*!< P5_MFP pin 4 mask */
#define SYS_MFP_P55_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
#define SYS_MFP_P55_Msk 0x00002020UL /*!< P5_MFP pin 5 mask */
/*@}*/ /* end of group Mini58_SYS_EXPORTED_CONSTANTS */
/** @addtogroup Mini58_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
@{
*/
/**
* @brief Clear Brown-out detector interrupt flag
* @param None
* @return None
* @details This macro clear Brown-out detector interrupt flag.
*/
#define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
/**
* @brief Set Brown-out detector function to normal mode
* @param None
* @return None
* @details This macro set Brown-out detector to normal mode.
* The register write-protection function should be disabled before using this macro.
*/
#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
/**
* @brief Disable Brown-out detector function
* @param None
* @return None
* @details This macro disable Brown-out detector function.
* The register write-protection function should be disabled before using this macro.
*/
#define SYS_DISABLE_BOD() (SYS->BODCTL = (SYS->BODCTL &~(SYS_BODCTL_BODVL_Msk|SYS_BODCTL_BODEN_Msk))|SYS_BODCTL_BODVL_Msk)
/**
* @brief Enable Brown-out detector function
* @param None
* @return None
* @details This macro enable Brown-out detector function.
* The register write-protection function should be disabled before using this macro.
*/
#define SYS_ENABLE_BOD() (SYS->BODCTL = (SYS->BODCTL | SYS_BODCTL_BODEN_Msk))
/**
* @brief Get Brown-out detector interrupt flag
* @param None
* @retval 0 Brown-out detect interrupt flag is not set.
* @retval >=1 Brown-out detect interrupt flag is set.
* @details This macro get Brown-out detector interrupt flag.
*/
#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
/**
* @brief Get Brown-out detector status
* @param None
* @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
* @retval >=1 System voltage is lower than BOD threshold voltage setting.
* @details This macro get Brown-out detector output status.
* If the BOD function is disabled, this function always return 0.
*/
#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
/**
* @brief Enable Brown-out detector interrupt function
* @param None
* @return None
* @details This macro enable Brown-out detector interrupt function.
* The register write-protection function should be disabled before using this macro.
*/
#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
/**
* @brief Enable Brown-out detector reset function
* @param None
* @return None
* @details This macro enable Brown-out detect reset function.
* The register write-protection function should be disabled before using this macro.
*/
#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
/**
* @brief Set Brown-out detector function low power mode
* @param None
* @return None
* @details This macro set Brown-out detector to low power mode.
* The register write-protection function should be disabled before using this macro.
*/
#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
/**
* @brief Set Brown-out detector voltage level
* @param[in] u32Level is Brown-out voltage level. Including :
* - \ref SYS_BODCTL_BODVL_4_4V
* - \ref SYS_BODCTL_BODVL_3_7V
* - \ref SYS_BODCTL_BODVL_2_7V
* - \ref SYS_BODCTL_BODVL_2_2V
* @return None
* @details This macro set Brown-out detector voltage level.
* The write-protection function should be disabled before using this macro.
*/
#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
/**
* @brief Get reset source is from Brown-out detector reset
* @param None
* @retval 0 Previous reset source is not from Brown-out detector reset
* @retval >=1 Previous reset source is from Brown-out detector reset
* @details This macro get previous reset source is from Brown-out detect reset or not.
*/
#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
/**
* @brief Get reset source is from CPU reset
* @param None
* @retval 0 Previous reset source is not from CPU reset
* @retval >=1 Previous reset source is from CPU reset
* @details This macro get previous reset source is from CPU reset.
*/
#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
/**
* @brief Get reset source is from Power-on Reset
* @param None
* @retval 0 Previous reset source is not from Power-on Reset
* @retval >=1 Previous reset source is from Power-on Reset
* @details This macro get previous reset source is from Power-on Reset.
*/
#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
/**
* @brief Get reset source is from reset pin reset
* @param None
* @retval 0 Previous reset source is not from reset pin reset
* @retval >=1 Previous reset source is from reset pin reset
* @details This macro get previous reset source is from reset pin reset.
*/
#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
/**
* @brief Get reset source is from system reset
* @param None
* @retval 0 Previous reset source is not from system reset
* @retval >=1 Previous reset source is from system reset
* @details This macro get previous reset source is from system reset.
*/
#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
/**
* @brief Get reset source is from window watch dog reset
* @param None
* @retval 0 Previous reset source is not from window watch dog reset
* @retval >=1 Previous reset source is from window watch dog reset
* @details This macro get previous reset source is from window watch dog reset.
*/
#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
/**
* @brief Disable Power-on Reset function
* @param None
* @return None
* @details This macro disable Power-on Reset function.
* The register write-protection function should be disabled before using this macro.
*/
#define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5)
/**
* @brief Enable Power-on Reset function
* @param None
* @return None
* @details This macro enable Power-on Reset function.
* The register write-protection function should be disabled before using this macro.
*/
#define SYS_ENABLE_POR() (SYS->PORCTL = 0)
/**
* @brief Clear reset source flag
* @param[in] u32RstSrc is reset source. Including :
* - \ref SYS_RSTSTS_PORF_Msk
* - \ref SYS_RSTSTS_PINRF_Msk
* - \ref SYS_RSTSTS_WDTRF_Msk
* - \ref SYS_RSTSTS_BODRF_Msk
* - \ref SYS_RSTSTS_SYSRF_Msk
* - \ref SYS_RSTSTS_CPURF_Msk
* - \ref SYS_RSTSTS_CPULKRF_Msk
* @return None
* @details This macro clear reset source flag.
*/
#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
/**
* @brief Disable register write-protection function
* @param None
* @return None
* @details This function disable register write-protection function.
* To unlock the protected register to allow write access.
*/
__STATIC_INLINE void SYS_UnlockReg(void)
{
do
{
SYS->REGLCTL = 0x59;
SYS->REGLCTL = 0x16;
SYS->REGLCTL = 0x88;
}
while(SYS->REGLCTL == 0);
}
/**
* @brief Enable register write-protection function
* @param None
* @return None
* @details This function is used to enable register write-protection function.
* To lock the protected register to forbid write access.
*/
__STATIC_INLINE void SYS_LockReg(void)
{
SYS->REGLCTL = 0;
}
void SYS_ClearResetSrc(uint32_t u32Src);
uint32_t SYS_GetBODStatus(void);
uint32_t SYS_GetResetSrc(void);
uint32_t SYS_IsRegLocked(void);
uint32_t SYS_ReadPDID(void);
void SYS_ResetChip(void);
void SYS_ResetCPU(void);
void SYS_ResetModule(uint32_t u32ModuleIndex);
void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
void SYS_DisableBOD(void);
/*@}*/ /* end of group Mini58_SYS_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group Mini58_SYS_Driver */
/*@}*/ /* end of group Mini58_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__SYS_H__
PAN159/PAN159-Template/Library/StdDriver/inc/timer.h
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/**************************************************************************//**
* @file timer.h
* @version V1.00
* $Revision: 7 $
* $Date: 15/05/27 11:56a $
* @brief Mini58 series TIMER driver header file
*
* @note
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __TIMER_H__
#define __TIMER_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
@{
*/
/** @addtogroup Mini58_TIMER_Driver TIMER Driver
@{
*/
/** @addtogroup Mini58_TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
@{
*/
#define TIMER_ONESHOT_MODE (0UL) /*!< Timer working in one shot mode */
#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode */
#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle mode */
#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous mode */
#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL) /*!< Free counting mode */
#define TIMER_CAPTURE_TRIGGER_COUNTING_MODE (TIMER_EXTCTL_CAPSEL_Msk) /*!< Trigger counting mode */
#define TIMER_CAPTURE_COUNTER_RESET_MODE (TIMER_EXTCTL_CAPFUNCS_Msk) /*!< Counter reset mode */
#define TIMER_CAPTURE_FALLING_EDGE (0UL) /*!< Falling edge trigger timer capture */
#define TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge trigger timer capture */
#define TIMER_CAPTURE_FALLING_THEN_RISING_EDGE (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge then rising edge trigger timer capture */
#define TIMER_CAPTURE_RISING_THEN_FALLING_EDGE (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge then falling edge trigger timer capture */
#define TIMER_COUNTER_RISING_EDGE (TIMER_EXTCTL_CNTPHASE_Msk) /*!< Counter increase on rising edge */
#define TIMER_COUNTER_FALLING_EDGE (0UL) /*!< Counter increase on falling edge */
#define TIMER_TOGGLE_TMX_CNT_OUT (0UL) /*!< Timer use TMx_CNT_OUT, x = 0, 1 pin as toggle output pin */
#define TIMER_TOGGLE_TMX_EXT (TIMER_CTL_TGLPINSEL_Msk) /*!< Timer use TMx_EXT, x = 0, 1 pin as toggle output pin */
/*@}*/ /* end of group Mini58_TIMER_EXPORTED_CONSTANTS */
/** @addtogroup Mini58_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
@{
*/
/**
* @brief This macro is used to set new Timer compared value
* @param[in] timer The base address of Timer module
* @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF
* @return None
* \hideinitializer
*/
#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value))
/**
* @brief This macro is used to set new Timer prescale value
* @param[in] timer The base address of Timer module
* @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF
* @return None
* @note Clock input is divided by (prescale + 1) before it is fed into timer
* \hideinitializer
*/
#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
/**
* @brief This macro is used to check if specify Timer is inactive or active
* @param[in] timer The base address of Timer module
* @return timer is activate or inactivate
* @retval 0 Timer 24-bit up counter is inactive
* @retval 1 Timer 24-bit up counter is active
* \hideinitializer
*/
#define TIMER_IS_ACTIVE(timer) ((timer)->CTL & TIMER_CTL_ACTSTS_Msk ? 1 : 0)
/**
* @brief This macro is used to select Timer toggle output pin
* @param[in] timer The base address of Timer module
* @param[in] u32ToutSel Toggle output pin selection, valid values are
* - \ref TIMER_TOGGLE_TMX_CNT_OUT
* - \ref TIMER_TOGGLE_TMX_EXT
* @return None
* \hideinitializer
*/
#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))
/**
* @brief This function is used to start Timer counting
* @param[in] timer The base address of Timer module
* @return None
*/
__STATIC_INLINE void TIMER_Start(TIMER_T *timer)
{
timer->CTL |= TIMER_CTL_CNTEN_Msk;
}
/**
* @brief This function is used to stop Timer counting
* @param[in] timer The base address of Timer module
* @return None
*/
__STATIC_INLINE void TIMER_Stop(TIMER_T *timer)
{
timer->CTL &= ~TIMER_CTL_CNTEN_Msk;
}
/**
* @brief This function is used to enable the Timer wake-up function
* @param[in] timer The base address of Timer module
* @return None
* @note To wake the system from power down mode, timer clock source must be ether LXT or LIRC
*/
__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer)
{
timer->CTL |= TIMER_CTL_WKEN_Msk;
}
/**
* @brief This function is used to disable the Timer wake-up function
* @param[in] timer The base address of Timer module
* @return None
*/
__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer)
{
timer->CTL &= ~TIMER_CTL_WKEN_Msk;
}
/**
* @brief This function is used to enable the capture pin detection de-bounce function.
* @param[in] timer The base address of Timer module
* @return None
*/
__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
{
timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk;
}
/**
* @brief This function is used to disable the capture pin detection de-bounce function.
* @param[in] timer The base address of Timer module
* @return None
*/
__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
{
timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk;
}
/**
* @brief This function is used to enable the counter pin detection de-bounce function.
* @param[in] timer The base address of Timer module
* @return None
*/
__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
{
timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk;
}
/**
* @brief This function is used to disable the counter pin detection de-bounce function.
* @param[in] timer The base address of Timer module
* @return None
*/
__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
{
timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk;
}
/**
* @brief This function is used to enable the Timer time-out interrupt function.
* @param[in] timer The base address of Timer module
* @return None
*/
__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer)
{
timer->CTL |= TIMER_CTL_INTEN_Msk;
}
/**
* @brief This function is used to disable the Timer time-out interrupt function.
* @param[in] timer The base address of Timer module
* @return None
*/
__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer)
{
timer->CTL &= ~TIMER_CTL_INTEN_Msk;
}
/**
* @brief This function is used to enable the Timer capture trigger interrupt function.
* @param[in] timer The base address of Timer module
* @return None
*/
__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
{
timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk;
}
/**
* @brief This function is used to disable the Timer capture trigger interrupt function.
* @param[in] timer The base address of Timer module
* @return None
*/
__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
{
timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk;
}
/**
* @brief This function indicates Timer time-out interrupt occurred or not.
* @param[in] timer The base address of Timer module
* @return Timer time-out interrupt occurred or not
* @retval 0 Timer time-out interrupt did not occur
* @retval 1 Timer time-out interrupt occurred
*/
__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
{
return(timer->INTSTS & TIMER_INTSTS_TIF_Msk ? 1 : 0);
}
/**
* @brief This function clears the Timer time-out interrupt flag.
* @param[in] timer The base address of Timer module
* @return None
*/
__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
{
timer->INTSTS = TIMER_INTSTS_TIF_Msk;
}
/**
* @brief This function indicates Timer capture interrupt occurred or not.
* @param[in] timer The base address of Timer module
* @return Timer capture interrupt occurred or not
* @retval 0 Timer capture interrupt did not occur
* @retval 1 Timer capture interrupt occurred
*/
__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
{
return timer->EINTSTS;
}
/**
* @brief This function clears the Timer capture interrupt flag.
* @param[in] timer The base address of Timer module
* @return None
*/
__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
{
timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk;
}
/**
* @brief This function indicates Timer has waked up system or not.
* @param[in] timer The base address of Timer module
* @return Timer has waked up system or not
* @retval 0 Timer did not wake up system
* @retval 1 Timer wake up system
*/
__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
{
return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1 : 0);
}
/**
* @brief This function clears the Timer wakeup interrupt flag.
* @param[in] timer The base address of Timer module
* @return None
*/
__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
{
timer->INTSTS = TIMER_INTSTS_TWKF_Msk;
}
/**
* @brief This function gets the Timer capture data.
* @param[in] timer The base address of Timer module
* @return Timer capture data value
*/
__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
{
return timer->CAP;
}
/**
* @brief This function reports the current timer counter value.
* @param[in] timer The base address of Timer module
* @return Timer counter value
*/
__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
{
return timer->CNT;
}
uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
void TIMER_Close(TIMER_T *timer);
void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
void TIMER_DisableCapture(TIMER_T *timer);
void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
void TIMER_DisableEventCounter(TIMER_T *timer);
uint32_t TIMER_GetModuleClock(TIMER_T *timer);
/*@}*/ /* end of group Mini58_TIMER_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group Mini58_TIMER_Driver */
/*@}*/ /* end of group Mini58_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__TIMER_H__
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
PAN159/PAN159-Template/Library/StdDriver/inc/uart.h
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/**************************************************************************//**
* @file UART.h
* @version V1.00
* $Revision: 3 $
* $Date: 15/05/28 4:34p $
* @brief Mini58 series UART driver header file
*
* @note
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __UART_H__
#define __UART_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
@{
*/
/** @addtogroup Mini58_UART_Driver UART Driver
@{
*/
/** @addtogroup Mini58_UART_EXPORTED_CONSTANTS UART Exported Constants
@{
*/
/*---------------------------------------------------------------------------------------------------------*/
/* UART_FIFO constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 bit */
#define UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bits */
#define UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bits */
#define UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bits */
#define UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 1 bit */
#define UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 4 bits */
#define UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 8 bits */
#define UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 14 bits */
/*---------------------------------------------------------------------------------------------------------*/
/* UART_LINE constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_WORD_LEN_5 (0) /*!< UART_LINE setting to set UART word length to 5 bits */
#define UART_WORD_LEN_6 (1) /*!< UART_LINE setting to set UART word length to 6 bits */
#define UART_WORD_LEN_7 (2) /*!< UART_LINE setting to set UART word length to 7 bits */
#define UART_WORD_LEN_8 (3) /*!< UART_LINE setting to set UART word length to 8 bits */
#define UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity */
#define UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity */
#define UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity */
#define UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' */
#define UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' */
#define UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit */
#define UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length */
#define UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length */
/*---------------------------------------------------------------------------------------------------------*/
/* UART RTS LEVEL TRIGGER constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Trigger */
#define UART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Trigger */
/*---------------------------------------------------------------------------------------------------------*/
/* UA_FUNC_SEL constants definitions */
/*---------------------------------------------------------------------------------------------------------*/
#define UART_FUNC_SEL_UART (0x0 << UART_FUNSEL_FUN_SEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) */
#define UART_FUNC_SEL_IrDA (0x2 << UART_FUNSEL_FUN_SEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function */
#define UART_FUNC_SEL_RS485 (0x3 << UART_FUNSEL_FUN_SEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function */
/*@}*/ /* end of group Mini58_UART_EXPORTED_CONSTANTS */
/** @addtogroup Mini58_UART_EXPORTED_FUNCTIONS UART Exported Functions
@{
*/
/**
* @brief Calculate UART baudrate mode0 divider
*
* @param None
*
* @return UART baudrate mode0 register setting value
*
*/
#define UART_BAUD_MODE0 (0)
/**
* @brief Calculate UART baudrate mode0 divider
*
* @param None
*
* @return UART baudrate mode2 register setting value
*
*/
#define UART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk)
/**
* @brief Calculate UART baudrate mode0 divider
*
* @param[in] u32SrcFreq UART clock frequency
* @param[in] u32BaudRate Baudrate of UART module
*
* @return UART baudrate mode0 divider
*
*/
#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)
/**
* @brief Calculate UART baudrate mode2 divider
*
* @param[in] u32SrcFreq UART clock frequency
* @param[in] u32BaudRate Baudrate of UART module
*
* @return UART baudrate mode2 divider
*/
#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)
/**
* @brief Write Data to Tx data register
*
* @param[in] uart The base address of UART module.
* @param[in] u8Data Data byte to transmit
*
* @return None
*/
#define UART_WRITE(uart, u8Data) (uart->DAT = (u8Data))
/**
* @brief Read Rx data register
*
* @param[in] uart The base address of UART module.
*
* @return The oldest data byte in RX FIFO
*/
#define UART_READ(uart) (uart->DAT)
/**
* @brief Get Tx empty register value.
*
* @param[in] uart The base address of UART module
*
* @return Tx empty register value.
*/
#define UART_GET_TX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk)
/**
* @brief Get Rx empty register value.
*
* @param[in] uart The base address of UART module
*
* @return Rx empty register value.
*/
#define UART_GET_RX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
/**
* @brief Check specified uart port transmission is over.
*
* @param[in] uart The base address of UART module
*
* @return TE_Flag.
*/
#define UART_IS_TX_EMPTY(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
/**
* @brief Wait specified uart port transmission is over
*
* @param[in] uart The base address of UART module
*
* @return None
*/
#define UART_WAIT_TX_EMPTY(uart) while(!(((uart->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
/**
* @brief Check RDA_IF is set or not
*
* @param[in] uart The base address of UART module
*
* @return
* 0 : The number of bytes in the RX FIFO is less than the RFITL
* 1 : The number of bytes in the RX FIFO equals or larger than RFITL
*/
#define UART_IS_RX_READY(uart) ((uart->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
/**
* @brief Check TX FIFO is full or not
*
* @param[in] uart The base address of UART module
*
* @return
* 1 = TX FIFO is full
* 0 = TX FIFO is not full
*/
#define UART_IS_TX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
/**
* @brief Check RX FIFO is full or not
*
* @param[in] uart The base address of UART module
*
* @return
* 1 = RX FIFO is full
* 0 = RX FIFO is not full
*
*/
#define UART_IS_RX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
/**
* @brief Get Tx full register value
*
* @param[in] uart The base address of UART module
*
* @return Tx full register value
*/
#define UART_GET_TX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
/**
* @brief Get Rx full register value
*
* @param[in] uart The base address of UART module
*
* @return Rx full register value
*/
#define UART_GET_RX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
/**
* @brief Enable specified interrupt
*
* @param[in] uart The base address of UART module
* @param[in] u32eIntSel Interrupt type select
* - \ref UART_INTEN_TOCNTEN_Msk : Rx Time Out interrupt
* - \ref UART_INTEN_WKCTSIEN_Msk : Wakeup interrupt
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
* - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
* - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
*
* @return None
*/
#define UART_ENABLE_INT(uart, u32eIntSel) (uart->INTEN |= (u32eIntSel))
/**
* @brief Disable specified interrupt
*
* @param[in] uart The base address of UART module
* @param[in] u32eIntSel Interrupt type select
* - \ref UART_INTEN_TOCNTEN_Msk : Rx Time Out interrupt
* - \ref UART_INTEN_WKCTSIEN_Msk : Wakeup interrupt
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
* - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
* - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
* @return None
*/
#define UART_DISABLE_INT(uart, u32eIntSel) (uart->INTEN &= ~ (u32eIntSel))
/**
* @brief Get specified interrupt flag/status
*
* @param[in] uart The base address of UART module
* @param[in] u32eIntTypeFlag Interrupt Type Flag,should be
* - \ref UART_INTSTS_CTSWKIF_Msk : nCTS Wake-Up Interrupt Flag
* - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator
* - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator
* - \ref UART_INTSTS_MODEMINT_Msk : MODEM Status Interrupt Indicator
* - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt
* - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator
* - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator
* - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag
* - \ref UART_INTSTS_RXTOIF_Msk : Rx time-out interrupt Flag
* - \ref UART_INTSTS_MODEMIF_Msk : Modem interrupt Flag
* - \ref UART_INTSTS_RLSIF_Msk : Rx Line status interrupt Flag
* - \ref UART_INTSTS_THREIF_Msk : Tx empty interrupt Flag
* - \ref UART_INTSTS_RDAIF_Msk : Rx ready interrupt Flag
*
* @return
* 0 = The specified interrupt is not happened.
* 1 = The specified interrupt is happened.
*/
#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->INTSTS & (u32eIntTypeFlag))?1:0)
/**
* @brief Set RTS pin is low
*
* @param[in] uart The base address of UART module
* @return None
*/
__INLINE void UART_CLEAR_RTS(UART_T* uart)
{
uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
uart->MODEM &= ~UART_MODEM_RTS_Msk;
}
/**
* @brief Set RTS pin is high
*
* @param[in] uart The base address of UART module
* @return None
*/
__INLINE void UART_SET_RTS(UART_T* uart)
{
uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;
}
/**
* @brief Clear RS-485 Address Byte Detection Flag
*
* @param[in] uart The base address of UART module
* @return None
*/
#define UART_RS485_CLEAR_ADDR_FLAG(uart) (uart->FIFOSTS |= UART_FIFOSTS_ADDRDETF_Msk)
/**
* @brief Get RS-485 Address Byte Detection Flag
*
* @param[in] uart The base address of UART module
* @return RS-485 Address Byte Detection Flag
*/
#define UART_RS485_GET_ADDR_FLAG(uart) ((uart->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag);
void UART_Close(UART_T* uart );
void UART_DisableFlowCtrl(UART_T* uart );
void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag );
void UART_EnableFlowCtrl(UART_T* uart );
void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag );
void UART_Open(UART_T* uart, uint32_t u32baudrate);
uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
uint32_t UART_Write(UART_T* uart,uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
/*@}*/ /* end of group Mini58_UART_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group Mini58_UART_Driver */
/*@}*/ /* end of group Mini58_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__UART_H__
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
PAN159/PAN159-Template/Library/StdDriver/inc/wdt.h
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/**************************************************************************//**
* @file wdt.h
* @version V1.00
* $Revision: 2 $
* $Date: 15/05/28 1:16p $
* @brief Mini58 series WDT driver header file
*
* @note
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WDT_H__
#define __WDT_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
@{
*/
/** @addtogroup Mini58_WDT_Driver WDT Driver
@{
*/
/** @addtogroup Mini58_WDT_EXPORTED_CONSTANTS WDT Exported Constants
@{
*/
#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^4 * WDT clocks */
#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^6 * WDT clocks */
#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^8 * WDT clocks */
#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^10 * WDT clocks */
#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^12 * WDT clocks */
#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^14 * WDT clocks */
#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^16 * WDT clocks */
#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^18 * WDT clocks */
#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT setting reset delay to 3 WDT clocks */
#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT setting reset delay to 18 WDT clocks */
#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT setting reset delay to 130 WDT clocks */
#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT setting reset delay to 1026 WDT clocks */
/*@}*/ /* end of group Mini58_WDT_EXPORTED_CONSTANTS */
/** @addtogroup Mini58_WDT_EXPORTED_FUNCTIONS WDT Exported Functions
@{
*/
/**
* @brief This macro clear WDT time-out reset system flag.
* \hideinitializer
*/
#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
/**
* @brief This macro clear WDT time-out interrupt flag.
* \hideinitializer
*/
#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
/**
* @brief This macro clear WDT time-out wake-up system flag.
* \hideinitializer
*/
#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
/**
* @brief This macro indicate WDT time-out to reset system or not.
* @return WDT reset system or not
* @retval 0 WDT did not cause system reset
* @retval 1 WDT caused system reset
* \hideinitializer
*/
#define WDT_GET_RESET_FLAG() (WDT->CTL & WDT_CTL_RSTF_Msk ? 1 : 0)
/**
* @brief This macro indicate WDT time-out interrupt occurred or not.
* @return WDT time-out interrupt occurred or not
* @retval 0 WDT time-out interrupt did not occur
* @retval 1 WDT time-out interrupt occurred
* \hideinitializer
*/
#define WDT_GET_TIMEOUT_INT_FLAG() (WDT->CTL & WDT_CTL_IF_Msk ? 1 : 0)
/**
* @brief This macro indicate WDT time-out waked system up or not
* @return WDT time-out waked system up or not
* @retval 0 WDT did not wake up system
* @retval 1 WDT waked up system
* \hideinitializer
*/
#define WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->CTL & WDT_CTL_WKF_Msk ? 1 : 0)
/**
* @brief This macro is used to reset 18-bit WDT counter.
* @details If WDT is activated and enabled to reset system, software must reset WDT counter
* before WDT time-out plus reset delay reached. Or WDT generate a reset signal.
* \hideinitializer
*/
#define WDT_RESET_COUNTER() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)
void WDT_Open(uint32_t u32TimeoutInterval,
uint32_t u32ResetDelay,
uint32_t u32EnableReset,
uint32_t u32EnableWakeup);
void WDT_Close(void);
void WDT_EnableInt(void);
void WDT_DisableInt(void);
/*@}*/ /* end of group Mini58_WDT_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group Mini58_WDT_Driver */
/*@}*/ /* end of group Mini58_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__WDT_H__
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
PAN159/PAN159-Template/Library/StdDriver/inc/wwdt.h
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/**************************************************************************//**
* @file wwdt.h
* @version V1.00
* $Revision: 1 $
* $Date: 15/02/02 3:19p $
* @brief Mini58 series WWDT driver header file
*
* @note
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __WWDT_H__
#define __WWDT_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
@{
*/
/** @addtogroup Mini58_WWDT_Driver WWDT Driver
@{
*/
/** @addtogroup Mini58_WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
@{
*/
#define WWDT_PRESCALER_1 (0UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 1 \hideinitializer
#define WWDT_PRESCALER_2 (1UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 2 \hideinitializer
#define WWDT_PRESCALER_4 (2UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 4 \hideinitializer
#define WWDT_PRESCALER_8 (3UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 8 \hideinitializer
#define WWDT_PRESCALER_16 (4UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 16 \hideinitializer
#define WWDT_PRESCALER_32 (5UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 32 \hideinitializer
#define WWDT_PRESCALER_64 (6UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 64 \hideinitializer
#define WWDT_PRESCALER_128 (7UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 128 \hideinitializer
#define WWDT_PRESCALER_192 (8UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 192 \hideinitializer
#define WWDT_PRESCALER_256 (9UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 256 \hideinitializer
#define WWDT_PRESCALER_384 (0xAUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 384 \hideinitializer
#define WWDT_PRESCALER_512 (0xBUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 512 \hideinitializer
#define WWDT_PRESCALER_768 (0xCUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 768 \hideinitializer
#define WWDT_PRESCALER_1024 (0xDUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 1024 \hideinitializer
#define WWDT_PRESCALER_1536 (0xEUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 1536 \hideinitializer
#define WWDT_PRESCALER_2048 (0xFUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 2048 \hideinitializer
#define WWDT_RELOAD_WORD (0x00005AA5) ///< Fill this value to RLD register to reload WWDT counter \hideinitializer
/*@}*/ /* end of group Mini58_WWDT_EXPORTED_CONSTANTS */
/** @addtogroup Mini58_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
@{
*/
/**
* @brief This macro clear WWDT time-out reset system flag.
* @param None
* @return None
* \hideinitializer
*/
#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
/**
* @brief This macro clear WWDT compare match interrupt flag.
* @param None
* @return None
* \hideinitializer
*/
#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
/**
* @brief This macro is use to get WWDT time-out reset system flag.
* @return WWDT reset system or not
* @retval 0 WWDT did not cause system reset
* @retval 1 WWDT caused system reset
* \hideinitializer
*/
#define WWDT_GET_RESET_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk ? 1 : 0)
/**
* @brief This macro is used to indicate WWDT compare match interrupt flag.
* @return WWDT compare match interrupt occurred or not
* @retval 0 WWDT compare match interrupt did not occur
* @retval 1 WWDT compare match interrupt occurred
* \hideinitializer
*/
#define WWDT_GET_INT_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk ? 1 : 0)
/**
* @brief This macro to reflects current WWDT counter value
* @param None
* @return Return current WWDT counter value
* \hideinitializer
*/
#define WWDT_GET_COUNTER() (WWDT->CNT)
/**
* @brief This macro is used to reload the WWDT counter value to 0x3F.
* @param None
* @return None
* @details After WWDT enabled, application must reload WWDT counter while
* current counter is less than compare value and larger than 0,
* otherwise WWDT will cause system reset.
* \hideinitializer
*/
#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)
void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
/*@}*/ /* end of group Mini58_WWDT_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group Mini58_WWDT_Driver */
/*@}*/ /* end of group Mini58_Device_Driver */
#ifdef __cplusplus
}
#endif
#endif //__WWDT_H__
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/