添加PAN159资料
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/*******************************************************************************
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* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
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* All rights reserved.
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*
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* @file lib_driver_adc_pan159.c
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* @brief
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*
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* ADC对应的IO口:
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* ---------+-----------
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* ADC_CH0 | P5.3(5)
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* ---------+-----------
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* ADC_CH1 | P1.0(7)
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* ---------+-----------
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* ADC_CH2 | P1.2(8)
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* ---------+-----------
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* ADC_CH3 | P1.3(9)
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* ---------+-----------
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* ADC_CH4 | P1.4(10)
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* ---------+-----------
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* ADC_CH5 | P1.5(11)
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* ---------+-----------
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* ADC_CH6 | P3.0(13)
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* ---------+-----------
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* ADC_CH7 | P3.1(17)
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* ---------+-----------
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*
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* @history - V1.0, 2017-09-18, xiaoguolin, first implementation.
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*******************************************************************************/
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#include "lib_driver_adc_pan159.h"
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const static uint8_t adc_chns_table[] = {
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#if ADC_ENABLE_CH0_P53 != 0
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ADC_PAN159_CH0_P53,
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#endif
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#if ADC_ENABLE_CH1_P10 != 0
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ADC_PAN159_CH1_P10,
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#endif
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#if ADC_ENABLE_CH2_P12 != 0
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ADC_PAN159_CH2_P12,
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#endif
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#if ADC_ENABLE_CH3_P13 != 0
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ADC_PAN159_CH3_P13,
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#endif
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#if ADC_ENABLE_CH4_P14 != 0
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ADC_PAN159_CH4_P14,
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#endif
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#if ADC_ENABLE_CH5_P15 != 0
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ADC_PAN159_CH5_P15,
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#endif
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#if ADC_ENABLE_CH6_P30 != 0
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ADC_PAN159_CH6_P30,
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#endif
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#if ADC_ENABLE_CH7_P31 != 0
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ADC_PAN159_CH7_P31,
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#endif
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0x00
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};
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#define ADC_CHN_NUM_COUNT (sizeof(adc_chns_table)-1)
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static int8_t adc_cur_chn_index = 0;
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void adc_pan159_init(void)
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{
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ADC_POWER_ON(ADC);
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if(ADC_ENABLE_CH0_P53){
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SYS->P5_MFP &= ~SYS_MFP_P53_Msk;
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SYS->P5_MFP |= SYS_MFP_P53_ADC_CH0;
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GPIO_DISABLE_DIGITAL_PATH(P5,BIT3);
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}
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if(ADC_ENABLE_CH1_P10){
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SYS->P1_MFP &= ~SYS_MFP_P10_Msk;
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SYS->P1_MFP |= SYS_MFP_P10_ADC_CH1;
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GPIO_DISABLE_DIGITAL_PATH(P1,BIT0);
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}
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if(ADC_ENABLE_CH2_P12){
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SYS->P1_MFP &= ~SYS_MFP_P12_Msk;
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SYS->P1_MFP |= SYS_MFP_P12_ADC_CH2;
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GPIO_DISABLE_DIGITAL_PATH(P1,BIT2);
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}
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if(ADC_ENABLE_CH3_P13){
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SYS->P1_MFP &= ~SYS_MFP_P13_Msk;
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SYS->P1_MFP |= SYS_MFP_P13_ADC_CH3;
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GPIO_DISABLE_DIGITAL_PATH(P1,BIT3);
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}
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if(ADC_ENABLE_CH4_P14){
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SYS->P1_MFP &= ~SYS_MFP_P14_Msk;
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SYS->P1_MFP |= SYS_MFP_P14_ADC_CH4;
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GPIO_DISABLE_DIGITAL_PATH(P1,BIT4);
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}
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if(ADC_ENABLE_CH5_P15){
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SYS->P1_MFP &= ~SYS_MFP_P15_Msk;
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SYS->P1_MFP |= SYS_MFP_P15_ADC_CH5;
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GPIO_DISABLE_DIGITAL_PATH(P1,BIT5);
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}
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if(ADC_ENABLE_CH6_P30){
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SYS->P3_MFP &= ~SYS_MFP_P30_Msk;
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SYS->P3_MFP |= SYS_MFP_P30_ADC_CH6;
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GPIO_DISABLE_DIGITAL_PATH(P3,BIT0);
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}
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if(ADC_ENABLE_CH7_P31){
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SYS->P3_MFP &= ~SYS_MFP_P31_Msk;
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SYS->P3_MFP |= SYS_MFP_P31_ADC_CH7;
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GPIO_DISABLE_DIGITAL_PATH(P3,BIT1);
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}
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}
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void adc_pan159_samp2(uint16_t *buf)
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{
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/* 获取当前通道 */
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//uint8_t curr_index = adc_cur_chn_index;
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//int16_t curr_chn = adc_chns_table[curr_index];
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//adc_pan159_start(adc_chns_table[adc_cur_chn_index],6);
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ADC->CHEN = adc_chns_table[adc_cur_chn_index];
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ADC->EXTSMPT = (ADC->EXTSMPT & ~ADC_EXTSMPT_EXTSMPT_Msk) | 6;
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ADC_START_CONV(ADC);
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while(adc_pan159_is_busy());
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/* 读取ADC转换结果 */
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buf[adc_cur_chn_index] = adc_pan159_value();
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/* 计算下一个通道 */
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if(adc_cur_chn_index < ADC_CHN_NUM_COUNT-1){
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adc_cur_chn_index++;
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}
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else{
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adc_cur_chn_index = 0;
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}
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}
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void adc_pan159_samp1(uint16_t *buf)
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{
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ADC->CHEN = ADC_PAN159_CH3_P13;
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//ADC->CHEN = ADC_PAN159_CH1_P10 ;
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ADC->EXTSMPT = (ADC->EXTSMPT & ~ADC_EXTSMPT_EXTSMPT_Msk) | 6;
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ADC_START_CONV(ADC);
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while(adc_pan159_is_busy());
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/* 读取ADC转换结果 */
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buf[0] = adc_pan159_value();
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}
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@@ -0,0 +1,67 @@
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/*******************************************************************************
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* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
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* All rights reserved.
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*
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* @file lib_driver_adc_pan159.h
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* @brief
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*
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* ADC¶ÔÓ¦µÄIO¿Ú:
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* ---------+-----------
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* ADC_CH0 | P5.3(5)
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* ---------+-----------
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* ADC_CH1 | P1.0(7)
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* ---------+-----------
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* ADC_CH2 | P1.2(8)
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* ---------+-----------
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* ADC_CH3 | P1.3(9)
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* ---------+-----------
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* ADC_CH4 | P1.4(10)
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* ---------+-----------
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* ADC_CH5 | P1.5(11)
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* ---------+-----------
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* ADC_CH6 | P3.0(13)
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* ---------+-----------
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* ADC_CH7 | P3.1(17)
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* ---------+-----------
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*
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* @history - V1.0, 2017-09-18, xiaoguolin, first implementation.
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*******************************************************************************/
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#ifndef __LIB_DIRVER_ADC_PAN159_H
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#define __LIB_DIRVER_ADC_PAN159_H
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#ifdef __cplusplus
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extern "C"{
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#endif
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#include "Mini58Series.h"
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#define ADC_ENABLE_CH0_P53 0
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#define ADC_ENABLE_CH1_P10 0
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#define ADC_ENABLE_CH2_P12 0
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#define ADC_ENABLE_CH3_P13 1
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#define ADC_ENABLE_CH4_P14 0
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#define ADC_ENABLE_CH5_P15 0
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#define ADC_ENABLE_CH6_P30 0
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#define ADC_ENABLE_CH7_P31 0
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#define ADC_PAN159_CH0_P53 (1<<0)
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#define ADC_PAN159_CH1_P10 (1<<1)
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#define ADC_PAN159_CH2_P12 (1<<2)
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#define ADC_PAN159_CH3_P13 (1<<3)
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#define ADC_PAN159_CH4_P14 (1<<4)
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#define ADC_PAN159_CH5_P15 (1<<5)
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#define ADC_PAN159_CH6_P30 (1<<6)
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#define ADC_PAN159_CH7_P31 (1<<7)
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void adc_pan159_init(void);
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void adc_pan159_start(uint8_t chn, uint8_t smplclks);
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void adc_pan159_samp2(uint16_t *buf);
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void adc_pan159_samp1(uint16_t *buf);
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#define adc_pan159_value() ADC_GET_CONVERSION_DATA(ADC,NULL)
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#define adc_pan159_is_busy() ADC_IS_BUSY(ADC)
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#ifdef __cplusplus
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}
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#endif
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#endif //__LIB_DIRVER_ADC_PAN159_H
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@@ -0,0 +1,18 @@
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/*******************************************************************************
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* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
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* All rights reserved.
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*
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* @file lib_driver_delay_pan159.c
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* @brief PAN159 delay
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*
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* @history - V1.0, 2017-09-12, xiaoguolin, first implementation.
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*******************************************************************************/
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#include "lib_driver_delay_pan159.h"
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__ASM void __delay_pan159(uint32_t cycle)
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{
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__delay_pan159_loop
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SUBS r0,r0,#1
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BCS __delay_pan159_loop
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BX lr
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}
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@@ -0,0 +1,32 @@
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/*******************************************************************************
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* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
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* All rights reserved.
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*
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* @file lib_driver_delay_pan159_v1p0.h
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* @brief PAN159 delay
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* 注意：该延时函数在系统时钟为48MHz时准确
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*
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* @history - V1.0, 2017-09-12, xiaoguolin, first implementation.
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*******************************************************************************/
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#ifndef __DRIVER_DELAY_PAN159_H
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#define __DRIVER_DELAY_PAN159_H
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#ifdef __cplusplus
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extern "C"{
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#endif
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#include "Mini58Series.h"
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void __delay_pan159(uint32_t cycle);
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#define delay_pan159_us(us) do{if((us)){__delay_pan159((us)*12);}}while(0)
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#define delay_pan159_ms(ms) do{uint32_t cnt=(ms);while(cnt--){delay_pan159_us(2070);}}while(0)
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#define delay_us delay_pan159_us
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#define delay_ms delay_pan159_ms
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#ifdef __cplusplus
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}
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#endif
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#endif // __DRIVER_DELAY_PAN159_H
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@@ -0,0 +1,136 @@
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/*******************************************************************************
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* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
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* All rights reserved.
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*
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* @file drv_flash.c
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* @brief FLASH读写
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*
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* @history - V1.0, 2017-03-10, xiaoguolin, first implementation.
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*******************************************************************************/
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#include "lib_driver_flash_pan159.h"
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/*******************************************************************************
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* @brief FLASH擦除扇区(512字节)
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* @param[in] addr - 起始地址(512字节对齐)
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* sectors - 要擦除的连续扇区数目
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* @param[out] 无
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* @return 无
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* @history - V1.0, 2017-03-13, xiaoguolin, first implementation.
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*******************************************************************************/
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void flash_pan159_erase(uint32_t addr, uint16_t sectors)
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{
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SYS_UnlockReg();
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FMC_Open();
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FMC_ENABLE_SP_UPDATE();
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while(sectors != 0)
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{
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FMC_Erase(addr);
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addr += 128;
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sectors--;
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}
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FMC_DISABLE_SP_UPDATE();
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FMC_Close();
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SYS_LockReg();
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}
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/*******************************************************************************
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* @brief FLASH数据写入
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* @param[in] addr - 写入起始地址，要求4字节对齐
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* p_addr - 数据指针
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* len - 数据长度(字节为单位)
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* @param[out] 无
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* @return 无
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* @history - V1.0, 2017-03-13, xiaoguolin, first implementation.
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*******************************************************************************/
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void flash_pan159_write(uint32_t addr, void* p_data, uint16_t len)
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{
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#define PTR32 ((uint32_t*)p_data)
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#define PTR8 ((uint8_t*)p_data)
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uint16_t i;
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union{
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uint32_t u32;
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struct{
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uint8_t x0;
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uint8_t x1;
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uint8_t x2;
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uint8_t x3;
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}u8;
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}tmp;
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tmp.u32 = 0xFFFFFFFF;
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SYS_UnlockReg();
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FMC_Open();
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FMC_ENABLE_SP_UPDATE();
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for(i = 0; i < (len>>2); i++)
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{
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FMC_Write(addr,PTR32[i]);
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addr += 4;
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}
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i <<= 2;
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if(i < len)
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{
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tmp.u8.x0 = PTR8[i++];
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if(i < len)
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{
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tmp.u8.x1 = PTR8[i++];
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if(i < len)
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{
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tmp.u8.x2 = PTR8[i];
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}
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}
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FMC_Write(addr,tmp.u32);
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}
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FMC_DISABLE_SP_UPDATE();
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FMC_Close();
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SYS_LockReg();
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#undef PTR8
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#undef PTR32
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}
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/*******************************************************************************
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* @brief FLASH数据读取
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* @param[in] addr - 读取起始地址，要求4字节对齐
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* len - 数据长度(字节为单位)
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* @param[out] p_data - 数据缓冲区指针，帯回数据
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* @return 无
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* @history - V1.0, 2017-03-13, xiaoguolin, first implementation.
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*******************************************************************************/
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void flash_pan159_read(uint32_t addr, void* p_data, uint16_t len)
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{
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#define PTR32 ((uint32_t*)p_data)
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#define PTR8 ((uint8_t*)p_data)
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#define TMP (*((uint32_t*)tmp))
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uint16_t i;
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uint8_t tmp[4];
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SYS_UnlockReg();
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FMC_Open();
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FMC_ENABLE_SP_UPDATE();
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for(i = 0; i < (len>>2); i++)
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{
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PTR32[i] = FMC_Read(addr);
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addr += 4;
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}
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i <<= 2;
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if(i < len)
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{
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TMP = FMC_Read(addr);
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PTR8[i++] = tmp[0];
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if(i < len)
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{
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PTR8[i++] = tmp[1];
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if(i < len)
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{
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PTR8[i] = tmp[2];
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}
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}
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}
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FMC_DISABLE_SP_UPDATE();
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FMC_Close();
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SYS_LockReg();
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#undef TMP
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#undef PTR8
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#undef PTR32
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}
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@@ -0,0 +1,26 @@
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/*******************************************************************************
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* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
|
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* All rights reserved.
|
||||
*
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* @file drv_flash.h
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* @brief FLASH¶Áд
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*
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* @history - V1.0, 2017-03-10, xiaoguolin, first implementation.
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*******************************************************************************/
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#ifndef __DRV_FLASH_H
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#define __DRV_FLASH_H
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#ifdef __cplusplus
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extern "C"{
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#endif
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#include "Mini58Series.h"
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void flash_pan159_erase(uint32_t addr, uint16_t sectors);
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void flash_pan159_write(uint32_t addr, void* p_data, uint16_t len);
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void flash_pan159_read(uint32_t addr, void* p_data, uint16_t len);
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#ifdef __cplusplus
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}
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#endif
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#endif // __DRV_FLASH_H
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@@ -0,0 +1,51 @@
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/*******************************************************************************
|
||||
* @note Copyright (C) 2018 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file lib_driver_gpio_pan159.c
|
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* @brief PAN159 hardware gpioÇý¶¯
|
||||
*
|
||||
* @history - V1.0, 2018-01-19, huoweibin, first implementation.
|
||||
*******************************************************************************/
|
||||
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#include "lib_driver_gpio_pan159.h"
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typedef void (*TCallback)(void);
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static void (*__s_lib_driver_EINT1_pan159_irq_handler)(void) = NULL;
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static void (*__s_lib_driver_EINT0_pan159_irq_handler)(void) = NULL;
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void gpio_ext1_int_init(TCallback cbk)
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{
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if(cbk){
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GPIO_EnableEINT1(P5, 2, GPIO_INT_FALLING);
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NVIC_EnableIRQ(EINT1_IRQn);
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}
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__s_lib_driver_EINT1_pan159_irq_handler = cbk;
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}
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void gpio_ext0_int_init(TCallback cbk)
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{
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GPIO_SetMode(P3, BIT2, GPIO_MODE_INPUT);
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if(cbk){
|
||||
GPIO_EnableEINT1(P3, 2, GPIO_INT_FALLING);
|
||||
NVIC_EnableIRQ(EINT0_IRQn);
|
||||
}
|
||||
__s_lib_driver_EINT0_pan159_irq_handler = cbk;
|
||||
}
|
||||
|
||||
void EINT0_IRQHandler(void)
|
||||
{
|
||||
/* For P3.2, clear the INT flag */
|
||||
P3->INTSRC = BIT2;
|
||||
if(__s_lib_driver_EINT0_pan159_irq_handler){
|
||||
__s_lib_driver_EINT0_pan159_irq_handler();
|
||||
}
|
||||
|
||||
}
|
||||
void EINT1_IRQHandler(void)
|
||||
{
|
||||
/* For P5.2, clear the INT flag */
|
||||
P5->INTSRC = BIT2;
|
||||
if(__s_lib_driver_EINT1_pan159_irq_handler){
|
||||
__s_lib_driver_EINT1_pan159_irq_handler();
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
@@ -0,0 +1,26 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2018 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file lib_driver_gpio_pan159.c
|
||||
* @brief PAN159 hardware gpioÇý¶¯
|
||||
*
|
||||
* @history - V1.0, 2018-01-19, huoweibin, first implementation.
|
||||
*******************************************************************************/
|
||||
#ifndef __LIB_DRIVER_GPIO_PAN159_H
|
||||
#define __LIB_DRIVER_GPIO_PAN159_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
#include "Mini58Series.h"
|
||||
typedef void (*TCallback)(void);
|
||||
void gpio_ext1_int_init(TCallback cbk);
|
||||
void gpio_ext0_int_init(TCallback cbk);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__LIB_DRIVER_GPIO_PAN159_H
|
||||
@@ -0,0 +1,216 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2018 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file lib_driver_iic_pan159.c
|
||||
* @brief PAN159 hardware IICÇý¶¯
|
||||
*
|
||||
* @history - V1.0, 2018-01-19, huoweibin, first implementation.
|
||||
*******************************************************************************/
|
||||
#include "lib_driver_iic_pan159.h"
|
||||
//#include <string.h>
|
||||
|
||||
uint8_t g_u8DeviceAddr;
|
||||
uint8_t g_u8RegAddr;
|
||||
//uint8_t g_au8TxData[64];
|
||||
//uint8_t g_u8RxData[64];
|
||||
uint8_t g_u8DataLen;
|
||||
uint8_t g_u8DataLenMax;
|
||||
uint8_t __IO g_u8EndFlag = 0;
|
||||
typedef void (*TCallback)(void);
|
||||
typedef void (*I2C_FUNC)(uint32_t u32Status,uint8_t *buf,TCallback cbk, TCallback fail_cbk);
|
||||
|
||||
I2C_FUNC __IO s_I2CHandlerFn = NULL;
|
||||
TCallback __IO cbk_success = NULL;
|
||||
TCallback __IO cbk_failed = NULL;
|
||||
uint8_t* buf_addr = NULL;
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* I2C IRQ Handler */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
void I2C0_IRQHandler(void)
|
||||
{
|
||||
uint32_t u32Status;
|
||||
|
||||
u32Status = I2C_GET_STATUS(I2C0);
|
||||
|
||||
if (I2C_GET_TIMEOUT_FLAG(I2C0)) {
|
||||
/* Clear I2C Timeout Flag */
|
||||
I2C_ClearTimeoutFlag(I2C0);
|
||||
}
|
||||
else {
|
||||
if (s_I2CHandlerFn != NULL)
|
||||
s_I2CHandlerFn(u32Status,buf_addr,cbk_success,cbk_failed);
|
||||
}
|
||||
}
|
||||
|
||||
void iic_pan159_init(void)
|
||||
{
|
||||
//uint32_t u32Div;
|
||||
|
||||
CLK_EnableModuleClock(I2C0_MODULE);
|
||||
SYS->P3_MFP &= ~SYS_MFP_P34_Msk;
|
||||
SYS->P3_MFP |= SYS_MFP_P34_I2C0_SDA;
|
||||
SYS->P3_MFP &= ~SYS_MFP_P35_Msk;
|
||||
SYS->P3_MFP |= SYS_MFP_P35_I2C0_SCL;
|
||||
|
||||
SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk;
|
||||
SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk;
|
||||
|
||||
I2C_Open(I2C0,400000);
|
||||
// u32Div = (uint32_t) (((SystemCoreClock * 10)/(400000 * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
|
||||
// I2C0->CLKDIV = u32Div;
|
||||
// I2C0->CTL |= I2C_CTL_I2CEN_Msk;
|
||||
|
||||
I2C0->CTL |= I2C_CTL_INTEN_Msk;
|
||||
NVIC_EnableIRQ(I2C0_IRQn);
|
||||
|
||||
}
|
||||
|
||||
void iic_master_tx(uint32_t u32Status ,uint8_t *buf, TCallback cbk, TCallback fail_cbk)
|
||||
{
|
||||
if (u32Status == 0x08) { /* START has been transmitted */
|
||||
I2C_SET_DATA(I2C0, g_u8DeviceAddr << 1); /* Write SLA+W to Register I2CDAT */
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_SI);
|
||||
}
|
||||
else if (u32Status == 0x18) { /* SLA+W has been transmitted and ACK has been received */
|
||||
I2C_SET_DATA(I2C0, g_u8RegAddr);
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_SI);
|
||||
}
|
||||
else if (u32Status == 0x20) { /* SLA+W has been transmitted and NACK has been received */
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_STO | I2C_SI);
|
||||
}
|
||||
else if (u32Status == 0x28) { /* DATA has been transmitted and ACK has been received */
|
||||
if (g_u8DataLen != g_u8DataLenMax) {
|
||||
I2C_SET_DATA(I2C0, buf[g_u8DataLen++]);
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_SI);
|
||||
} else {
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_STO | I2C_SI);
|
||||
g_u8EndFlag = 1;
|
||||
if(cbk != NULL)
|
||||
{
|
||||
cbk();
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
if(fail_cbk != NULL)
|
||||
{
|
||||
fail_cbk();
|
||||
}
|
||||
//I2C_STOP(I2C0);
|
||||
//(I2C0)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk);
|
||||
/* TO DO */
|
||||
// printf("Status 0x%x is NOT processed\n", u32Status);
|
||||
}
|
||||
}
|
||||
void iic_master_rx(uint32_t u32Status ,uint8_t *buf,TCallback cbk, TCallback fail_cbk){
|
||||
if (u32Status == 0x08) { /* START has been transmitted and prepare SLA+W */
|
||||
I2C_SET_DATA(I2C0, g_u8DeviceAddr << 1); /* Write SLA+W to Register I2CDAT */
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_SI);
|
||||
}
|
||||
else if (u32Status == 0x18) { /* SLA+W has been transmitted and ACK has been received */
|
||||
I2C_SET_DATA(I2C0, g_u8RegAddr);
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_SI);
|
||||
}
|
||||
else if (u32Status == 0x20) { /* SLA+W has been transmitted and NACK has been received */
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_STO | I2C_SI);
|
||||
}
|
||||
else if (u32Status == 0x28) { /* DATA has been transmitted and ACK has been received */
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_STA | I2C_SI);
|
||||
}
|
||||
else if (u32Status == 0x10) { /* Repeat START has been transmitted and prepare SLA+R */
|
||||
I2C_SET_DATA(I2C0, ((g_u8DeviceAddr << 1) | 0x01)); /* Write SLA+R to Register I2CDAT */
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_SI);
|
||||
}
|
||||
else if (u32Status == 0x40) { /* SLA+R has been transmitted and ACK has been received */
|
||||
if(g_u8DataLenMax== 1)
|
||||
{
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_SI );
|
||||
}
|
||||
else{
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_SI | I2C_AA );
|
||||
}
|
||||
}
|
||||
else if (u32Status == 0x50) { /* DATA has been received and ACK has been returned */
|
||||
if(g_u8DataLen != g_u8DataLenMax-2){
|
||||
buf[g_u8DataLen++] = I2C_GET_DATA(I2C0);
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_SI | I2C_AA);
|
||||
}
|
||||
else{
|
||||
buf[g_u8DataLen++] = I2C_GET_DATA(I2C0);
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_SI );
|
||||
}
|
||||
}
|
||||
else if (u32Status == 0x58) { /* DATA has been received and NACK has been returned */
|
||||
buf[g_u8DataLen++] = I2C_GET_DATA(I2C0);
|
||||
I2C_SET_CONTROL_REG(I2C0, I2C_STO | I2C_SI);
|
||||
g_u8EndFlag = 1;
|
||||
if(cbk != NULL)
|
||||
{
|
||||
cbk();
|
||||
}
|
||||
}
|
||||
else {
|
||||
if(fail_cbk != NULL)
|
||||
{
|
||||
fail_cbk();
|
||||
}
|
||||
//(I2C0)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk);
|
||||
//I2C_STOP(I2C0);
|
||||
/* TO DO */
|
||||
//printf("Status 0x%x is NOT processed\n", u32Status);
|
||||
}
|
||||
}
|
||||
|
||||
void iic_start_send_bytes(uint16_t devAddr,uint8_t regAddr, uint8_t *buf, uint8_t len,TCallback cbk, TCallback fail_cbk)
|
||||
{
|
||||
I2C0->CTL |= I2C_CTL_I2CEN_Msk;
|
||||
|
||||
I2C0->CTL |= I2C_CTL_INTEN_Msk;
|
||||
g_u8DataLenMax = len;
|
||||
g_u8DeviceAddr = devAddr;
|
||||
|
||||
g_u8RegAddr = regAddr;
|
||||
|
||||
g_u8DataLen = 0;
|
||||
g_u8EndFlag = 0;
|
||||
/* I2C function to write data to slave */
|
||||
s_I2CHandlerFn = (I2C_FUNC)iic_master_tx;
|
||||
cbk_success = cbk;
|
||||
cbk_failed = fail_cbk;
|
||||
buf_addr = buf;
|
||||
/* I2C as master sends START signal */
|
||||
I2C_START(I2C0);
|
||||
|
||||
|
||||
}
|
||||
|
||||
void iic_start_read_bytes(uint16_t devAddr,uint8_t regAddr, uint8_t *buf, uint8_t len,TCallback cbk, TCallback fail_cbk)
|
||||
{
|
||||
I2C0->CTL |= I2C_CTL_I2CEN_Msk;
|
||||
|
||||
I2C0->CTL |= I2C_CTL_INTEN_Msk;
|
||||
g_u8DataLenMax = len;
|
||||
g_u8DeviceAddr = devAddr;
|
||||
g_u8RegAddr = regAddr;
|
||||
g_u8DataLen = 0;
|
||||
g_u8EndFlag = 0;
|
||||
s_I2CHandlerFn = (I2C_FUNC)iic_master_rx;
|
||||
cbk_success = cbk;
|
||||
cbk_failed = fail_cbk;
|
||||
buf_addr = buf;
|
||||
//CLK_SysTickDelay(5000);
|
||||
/* I2C as master sends START signal */
|
||||
I2C_START(I2C0);
|
||||
//while (g_u8EndFlag == 0);
|
||||
}
|
||||
|
||||
uint8_t is_iic_busy(void)
|
||||
{
|
||||
if(g_u8EndFlag){
|
||||
return 0;
|
||||
}
|
||||
else{
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,27 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2018 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file lib_driver_iic_pan159.c
|
||||
* @brief PAN159 hardware IICÇý¶¯
|
||||
*
|
||||
* @history - V1.0, 2018-01-19, huoweibin, first implementation.
|
||||
*******************************************************************************/
|
||||
#ifndef __LIB_DIRVER_IIC_PAN159_H
|
||||
#define __LIB_DIRVER_IIC_PAN159_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
#include "Mini58Series.h"
|
||||
typedef void (*TCallback)(void);
|
||||
void iic_pan159_init(void);
|
||||
void iic_start_send_bytes(uint16_t devAddr,uint8_t regAddr, uint8_t *buf, uint8_t len,TCallback cbk, TCallback fail_cbk);
|
||||
void iic_start_read_bytes(uint16_t devAddr,uint8_t regAddr, uint8_t *buf, uint8_t len,TCallback cbk, TCallback fail_cbk);
|
||||
uint8_t is_iic_busy(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __LIB_DIRVER_IIC_PAN159_H
|
||||
@@ -0,0 +1,166 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file drv_pwm.c
|
||||
* @brief PWM驱动
|
||||
* ----------+----------+----------+----------
|
||||
* PWM0_CH0 | | P1.2(8) | P2.2(24)
|
||||
* ----------+----------+----------+----------
|
||||
* PWM0_CH1 | | P1.3(9) | P2.3(25)
|
||||
* ----------+----------+----------+----------
|
||||
* PWM0_CH2 | | | P2.4(26)
|
||||
* ----------+----------+----------+----------
|
||||
* PWM0_CH3 | | | P2.5(27)
|
||||
* ----------+----------+----------+----------
|
||||
* PWM0_CH4 | | P1.4(10) | P2.6(28)
|
||||
* ----------+----------+----------+----------
|
||||
* PWM0_CH5 | P0.4(15) | |
|
||||
* ----------+----------+----------+----------
|
||||
*
|
||||
* @history - V1.0, 2017-04-20, xiaoguolin, first implementation.
|
||||
* @history - V1.1, 2018-01-18, huoweibin, add pwm_pan159_setDuty.
|
||||
*******************************************************************************/
|
||||
#include "lib_driver_pwm_pan159.h"
|
||||
|
||||
// <0x50=>PWM0_CH0_P12 (CHIP_PIN_8)
|
||||
// <0x90=>PWM0_CH0_P22 (CHIP_PIN_24)
|
||||
// <0x59=>PWM0_CH1_P13 (CHIP_PIN_9)
|
||||
// <0x99=>PWM0_CH1_P23 (CHIP_PIN_25)
|
||||
// <0xA2=>PWM0_CH2_P24 (CHIP_PIN_26)
|
||||
// <0xAB=>PWM0_CH3_P25 (CHIP_PIN_27)
|
||||
// <0x64=>PWM0_CH4_P14 (CHIP_PIN_10)
|
||||
// <0xB4=>PWM0_CH4_P26 (CHIP_PIN_28)
|
||||
// <0x25=>PWM0_CH5_P04 (CHIP_PIN_15)
|
||||
//#define __PWM_PAN159_M0 0xA2 //P24
|
||||
//#define __PWM_PAN159_M1 0x99 //P23
|
||||
//#define __PWM_PAN159_M2 0x90 //P22
|
||||
//#define __PWM_PAN159_M3 0xAB //P25
|
||||
/*******************************************************************************
|
||||
* @brief PWM初始化
|
||||
* @param[in]
|
||||
* @return 1 - 成功
|
||||
* 0 - 失败
|
||||
* @history - V1.0, 2017-09-12, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
void pwm_pan159_init(uint8_t psc)
|
||||
{
|
||||
//const uint32_t pwmch_module[] = {PWMCH01_MODULE,PWMCH23_MODULE,PWMCH45_MODULE};
|
||||
SYS_UnlockReg();
|
||||
CLK_EnableModuleClock(PWMCH01_MODULE); //moudle clk enable ch01
|
||||
CLK_EnableModuleClock(PWMCH23_MODULE); //moudle clk enable ch23
|
||||
// CLK_SetModuleClock(PWMCH01_MODULE,CLK_CLKSEL1_PWMCH01SEL_HCLK,0);//时钟1分频
|
||||
// CLK_SetModuleClock(PWMCH23_MODULE,CLK_CLKSEL1_PWMCH23SEL_HCLK,0);//时钟1分频
|
||||
//CLK_EnableModuleClock(PWMCH45_MODULE); //moudle clk enable ch45
|
||||
// CLK_EnableModuleClock(pwmch_module[0x03 >> 1]); //moudle clk enable ch3
|
||||
SystemCoreClockUpdate();
|
||||
SYS_LockReg();
|
||||
//P22
|
||||
SYS->P2_MFP &= ~SYS_MFP_P22_Msk;
|
||||
SYS->P2_MFP |= SYS_MFP_P22_PWM0_CH0;
|
||||
PWM->CTL |= PWM_CTL_CNTEN0_Msk | PWM_CTL_CNTMODE0_Msk;
|
||||
//P23
|
||||
SYS->P2_MFP &= ~SYS_MFP_P23_Msk;
|
||||
SYS->P2_MFP |= SYS_MFP_P23_PWM0_CH1;
|
||||
PWM->CTL |= PWM_CTL_CNTEN1_Msk | PWM_CTL_CNTMODE1_Msk;
|
||||
//P24
|
||||
SYS->P2_MFP &= ~SYS_MFP_P24_Msk;
|
||||
SYS->P2_MFP |= SYS_MFP_P24_PWM0_CH2;
|
||||
PWM->CTL |= PWM_CTL_CNTEN2_Msk | PWM_CTL_CNTMODE2_Msk;
|
||||
//P25
|
||||
SYS->P2_MFP &= ~SYS_MFP_P25_Msk;
|
||||
SYS->P2_MFP |= SYS_MFP_P25_PWM0_CH3;
|
||||
PWM->CTL |= PWM_CTL_CNTEN3_Msk | PWM_CTL_CNTMODE3_Msk;
|
||||
|
||||
PWM_SET_PRESCALER(PWM,0x02,psc);
|
||||
PWM_SET_DIVIDER(PWM,0x02,PWM_CLK_DIV_1);
|
||||
//PWM_SET_ALIGNED_TYPE(PWM,0x02,0x80000000);//中心对齐
|
||||
PWM_SET_ALIGNED_TYPE(PWM,0x02,PWM_EDGE_ALIGNED);//边沿对齐
|
||||
PWM_SET_CMR(PWM,0x02,0);
|
||||
PWM_SET_CNR(PWM,0x02,1000);//PWM RANGE setting
|
||||
//PWM->CTL |= 1 << (PWM_CTL_PINV0_Pos + (((uint32_t)(0x02)) << 2));//输出取反
|
||||
|
||||
PWM_SET_PRESCALER(PWM,0x01,psc);
|
||||
PWM_SET_DIVIDER(PWM,0x01,PWM_CLK_DIV_1);
|
||||
PWM_SET_ALIGNED_TYPE(PWM,0x01,PWM_EDGE_ALIGNED);
|
||||
PWM_SET_CMR(PWM,0x01,0);
|
||||
PWM_SET_CNR(PWM,0x01,1000);//PWM RANGE setting
|
||||
//PWM->CTL |= 1 << (PWM_CTL_PINV0_Pos + (((uint32_t)(0x01)) << 2));//输出取反
|
||||
|
||||
PWM_SET_PRESCALER(PWM,0x00,psc);
|
||||
PWM_SET_DIVIDER(PWM,0x00,PWM_CLK_DIV_1);
|
||||
PWM_SET_ALIGNED_TYPE(PWM,0x00,PWM_EDGE_ALIGNED);
|
||||
PWM_SET_CMR(PWM,0x00,0);
|
||||
PWM_SET_CNR(PWM,0x00,1000);//PWM RANGE setting
|
||||
//PWM->CTL |= 1 << (PWM_CTL_PINV0_Pos + (((uint32_t)(0x00)) << 2));//输出取反
|
||||
|
||||
PWM_SET_PRESCALER(PWM,0x03,psc);
|
||||
PWM_SET_DIVIDER(PWM,0x03,PWM_CLK_DIV_1);
|
||||
PWM_SET_ALIGNED_TYPE(PWM,0x03,PWM_EDGE_ALIGNED);
|
||||
PWM_SET_CMR(PWM,0x03,0);
|
||||
PWM_SET_CNR(PWM,0x03,1000);//PWM RANGE setting
|
||||
//PWM->CTL |= 1 << (PWM_CTL_PINV0_Pos + (((uint32_t)(0x03)) << 2));//输出取反
|
||||
|
||||
/* 开启PWM */
|
||||
PWM->CTL |= PWM_CTL_CNTEN0_Msk << (((uint32_t)0x00) << 2);
|
||||
PWM->CTL |= PWM_CTL_CNTEN0_Msk << (((uint32_t)0x01) << 2);
|
||||
PWM->CTL |= PWM_CTL_CNTEN0_Msk << (((uint32_t)0x02) << 2);
|
||||
PWM->CTL |= PWM_CTL_CNTEN0_Msk << (((uint32_t)0x03) << 2);
|
||||
|
||||
PWM_PAN159_CHN_OUT(0x00,0);
|
||||
PWM_PAN159_CHN_OUT(0x01,0);
|
||||
PWM_PAN159_CHN_OUT(0x02,0);
|
||||
PWM_PAN159_CHN_OUT(0x03,0);
|
||||
//PWM_PAN159_CHN_UNLOCK(1<<chn);
|
||||
|
||||
|
||||
// return pwm_port;
|
||||
}
|
||||
/*******************************************************************************
|
||||
* @brief PWM输出
|
||||
* @param[in]
|
||||
* @return
|
||||
* @history - V1.0, 2018-01-18, huoweibin, first implementation.
|
||||
*******************************************************************************/
|
||||
void pwm_pan159_setDuty(uint16_t *duty)
|
||||
{
|
||||
register uint8_t lock = 0x00;
|
||||
register uint8_t unlock = 0x00;
|
||||
/*M1 - CH1 PWM out*/
|
||||
PWM_PAN159_CHN_OUT(0x01,duty[0]);
|
||||
if(duty[0] == 0){
|
||||
lock |= 1 << 0x01;
|
||||
}
|
||||
else{
|
||||
unlock |= 1 << 0x01;
|
||||
}
|
||||
/*M2 - CH3 PWM out*/
|
||||
PWM_PAN159_CHN_OUT(0x03,duty[1]);
|
||||
if(duty[1] == 0){
|
||||
lock |= 1 << 0x03;
|
||||
}
|
||||
else{
|
||||
unlock |= 1 << 0x03;
|
||||
}
|
||||
/*M3 - CH2 PWM out*/
|
||||
PWM_PAN159_CHN_OUT(0x02,duty[2]);
|
||||
if(duty[2] == 0){
|
||||
lock |= 1 << 0x02;
|
||||
}
|
||||
else{
|
||||
unlock |= 1 << 0x02;
|
||||
}
|
||||
/*M4 - CH0 PWM out*/
|
||||
PWM_PAN159_CHN_OUT(0x00,duty[3]);
|
||||
if(duty[3] == 0){
|
||||
lock |= 1 << 0x00;
|
||||
}
|
||||
else{
|
||||
unlock |= 1 << 0x00;
|
||||
}
|
||||
PWM_PAN159_CHN_LOCK(lock);
|
||||
PWM_PAN159_CHN_UNLOCK(unlock);
|
||||
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,76 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file drv_pwm.h
|
||||
* @brief PWM驱动
|
||||
* 机体坐标系(z朝下,x为机头,y为右侧)：
|
||||
*
|
||||
* PWM对应的IO口:
|
||||
* ----------+----------+----------+----------
|
||||
* PWM0_CH0 | | P1.2(8) | P2.2(24)
|
||||
* ----------+----------+----------+----------
|
||||
* PWM0_CH1 | | P1.3(9) | P2.3(25)
|
||||
* ----------+----------+----------+----------
|
||||
* PWM0_CH2 | | | P2.4(26)
|
||||
* ----------+----------+----------+----------
|
||||
* PWM0_CH3 | | | P2.5(27)
|
||||
* ----------+----------+----------+----------
|
||||
* PWM0_CH4 | | P1.4(10) | P2.6(28)
|
||||
* ----------+----------+----------+----------
|
||||
* PWM0_CH5 | P0.4(15) | |
|
||||
* ----------+----------+----------+----------
|
||||
*
|
||||
* @history - V1.0, 2017-04-20, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
#ifndef __LIB_DIRVER_PWM_PAN159_H
|
||||
#define __LIB_DIRVER_PWM_PAN159_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
#include "Mini58Series.h"
|
||||
|
||||
#define __PWM_PAN159_PORT(P) ((P)<<6)
|
||||
#define __PWM_PAN159_PIN(B) ((B)<<3)
|
||||
#define __PWM_PAN159_CHN(C) ((C)<<0)
|
||||
|
||||
#define PWM_PAN159_PWM0_CH0_P12 (__PWM_PAN159_CHN(0)|__PWM_PAN159_PORT(1)|__PWM_PAN159_PIN(2)) /* 01 010 000 = 0x50 */
|
||||
#define PWM_PAN159_PWM0_CH0_P22 (__PWM_PAN159_CHN(0)|__PWM_PAN159_PORT(2)|__PWM_PAN159_PIN(2)) /* 10 010 000 = 0x90 */
|
||||
#define PWM_PAN159_PWM0_CH1_P13 (__PWM_PAN159_CHN(1)|__PWM_PAN159_PORT(1)|__PWM_PAN159_PIN(3)) /* 01 011 001 = 0x59 */
|
||||
#define PWM_PAN159_PWM0_CH1_P23 (__PWM_PAN159_CHN(1)|__PWM_PAN159_PORT(2)|__PWM_PAN159_PIN(3)) /* 10 011 001 = 0x99 */
|
||||
#define PWM_PAN159_PWM0_CH2_P24 (__PWM_PAN159_CHN(2)|__PWM_PAN159_PORT(2)|__PWM_PAN159_PIN(4)) /* 10 100 010 = 0xA2 */
|
||||
#define PWM_PAN159_PWM0_CH3_P25 (__PWM_PAN159_CHN(3)|__PWM_PAN159_PORT(2)|__PWM_PAN159_PIN(5)) /* 10 101 011 = 0xAB */
|
||||
#define PWM_PAN159_PWM0_CH4_P14 (__PWM_PAN159_CHN(4)|__PWM_PAN159_PORT(1)|__PWM_PAN159_PIN(4)) /* 01 100 100 = 0x64 */
|
||||
#define PWM_PAN159_PWM0_CH4_P26 (__PWM_PAN159_CHN(4)|__PWM_PAN159_PORT(2)|__PWM_PAN159_PIN(6)) /* 10 110 100 = 0xB4 */
|
||||
#define PWM_PAN159_PWM0_CH5_P04 (__PWM_PAN159_CHN(5)|__PWM_PAN159_PORT(0)|__PWM_PAN159_PIN(4)) /* 00 100 101 = 0x25 */
|
||||
|
||||
#define PWM_PAN159_PORT_MSK __PWM_PAN159_PORT(0x03)
|
||||
#define PWM_PAN159_PIN_MSK __PWM_PAN159_PIN(0x07)
|
||||
#define PWM_PAN159_CHN_MSK __PWM_PAN159_CHN(0x07)
|
||||
|
||||
#define PWM_PAN159_PORT(PWMx) ((PWMx)>>6)
|
||||
#define PWM_PAN159_PIN(PWMx) (((PWMx)&PWM_PAN159_PIN_MSK)>>3)
|
||||
#define PWM_PAN159_CHN(PWMx) ((PWMx)&PWM_PAN159_CHN_MSK)
|
||||
|
||||
#define PWM_PAN159_CMPDAT ((volatile uint32_t*)(0x40040000+0x24))
|
||||
#define PWM_PAN159_OEN (*(volatile uint32_t*)(0x40040000+0x5C))
|
||||
|
||||
#define PWM_PAN159_CHN_ISLOCKED(CHN_BITS) (PWM_PAN159_OEN&(CHN_BITS))
|
||||
#define PWM_PAN159_CHN_LOCK(CHN_BITS) (PWM_PAN159_OEN&=~(CHN_BITS))
|
||||
#define PWM_PAN159_CHN_UNLOCK(CHN_BITS) (PWM_PAN159_OEN|=(CHN_BITS))
|
||||
#define PWM_PAN159_CHN_OUT(CHN,VAL) (PWM_PAN159_CMPDAT[(CHN)]=(VAL))
|
||||
|
||||
#define pwm_pan159_islocked(pwm_port) PWM_PAN159_CHN_ISLOCK(1<<PWM_PAN159_CHN((pwm_port)))
|
||||
#define pwm_pan159_lock(pwm_port) PWM_PAN159_CHN_LOCK(1<<PWM_PAN159_CHN((pwm_port)))
|
||||
#define pwm_pan159_unlock(pwm_port) PWM_PAN159_CHN_UNLOCK(1<<PWM_PAN159_CHN((pwm_port)))
|
||||
#define pwm_pan159_out(pwm_port,val) PWM_PAN159_CHN_OUT(PWM_PAN159_CHN((pwm_port)),val)
|
||||
//uint8_t pwm_pan159_init(uint8_t pwm_port,uint8_t psc,uint8_t div,uint32_t align,uint32_t cnt,uint8_t inv);
|
||||
void pwm_pan159_init(uint8_t psc);
|
||||
void pwm_pan159_setDuty(uint16_t *duty);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __LIB_DIRVER_PWM_PAN159_H
|
||||
@@ -0,0 +1,70 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file drv_spi.c
|
||||
* @brief SPI?y?ˉ
|
||||
*
|
||||
* @history - V1.0, 2017-03-06, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
#include "lib_driver_rfspi_pan159.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief SPI初始化
|
||||
* @param[in] 无
|
||||
* @param[out] 无
|
||||
* @return 无
|
||||
******************************************************************************/
|
||||
void rfspi_pan159_init(void)
|
||||
{
|
||||
SYS->P0_MFP |= SYS_MFP_P01_GPIO; // P01->RF_CSN
|
||||
SYS->P0_MFP |= SYS_MFP_P07_SPI0_CLK|SYS_MFP_P05_SPI0_MOSI|SYS_MFP_P06_SPI0_MISO ;
|
||||
SYS->P5_MFP |= SYS_MFP_P52_GPIO; //P20->RF_IRQ
|
||||
|
||||
CLK_EnableModuleClock(SPI0_MODULE);//使能SPI时钟
|
||||
CLK_SetModuleClock(SPI0_MODULE,CLK_CLKSEL1_SPISEL_HCLK,1);//时钟1分频
|
||||
|
||||
GPIO_SetMode(P0, BIT1, GPIO_MODE_OUTPUT); //RF_CSN
|
||||
GPIO_SetMode(P5, BIT2, GPIO_MODE_INPUT); //RF_IRQ
|
||||
|
||||
SYS->P0_MFP |= SYS_MFP_P05_SPI0_MOSI | SYS_MFP_P06_SPI0_MISO | SYS_MFP_P07_SPI0_CLK;//设置IO复用功能
|
||||
SPI_Open(SPI0, SPI_MASTER, SPI_MODE_0,8,2000000);//主设备，模式0,8位宽度，2M速率
|
||||
SPI_DisableAutoSS(SPI0);//禁止硬件SS脚
|
||||
SPI_WRITE_TX(SPI0, 0);//清除SPI数据
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief SPI字节读写
|
||||
* @param[in] dat - 待写入数据
|
||||
* @param[out] 无
|
||||
* @return 读取到的字节
|
||||
******************************************************************************/
|
||||
uint8_t rfspi_pan159_rwc(uint8_t dat)
|
||||
{
|
||||
SPI_WRITE_TX(SPI0, dat);
|
||||
SPI_TRIGGER(SPI0);
|
||||
while(SPI_IS_BUSY(SPI0));
|
||||
return SPI0->RX;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief SPI读写数据块
|
||||
* @param[in] p_dat - 数据指针
|
||||
* len - 数据长度
|
||||
* @param[out] 无
|
||||
* @return 读取到的数据块，与p_dat共缓冲区
|
||||
* @history - V1.0, 2017-03-06, xiaoguolin, first implementation.
|
||||
******************************************************************************/
|
||||
uint8_t* rfspi_pan159_rws(uint8_t* p_dat, uint16_t len)
|
||||
{
|
||||
uint8_t i = 0;
|
||||
while(i < len)
|
||||
{
|
||||
SPI_WRITE_TX(SPI0, p_dat[i]);
|
||||
SPI_TRIGGER(SPI0);
|
||||
while(SPI_IS_BUSY(SPI0));
|
||||
p_dat[i] = SPI0->RX;
|
||||
i++;
|
||||
}
|
||||
return p_dat;
|
||||
}
|
||||
@@ -0,0 +1,36 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file drv_spi.h
|
||||
* @brief SPIÇý¶¯
|
||||
*
|
||||
* @history - V1.0, 2017-03-06, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
#ifndef __DRV_SPI_H
|
||||
#define __DRV_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
#include "Mini58Series.h"
|
||||
|
||||
#define rfspi_pan159_irq() P52
|
||||
#define rfspi_pan159_cs(level) (P01=(level))
|
||||
void rfspi_pan159_init(void);
|
||||
uint8_t rfspi_pan159_rwc(uint8_t dat);
|
||||
uint8_t* rfspi_pan159_rws(uint8_t* p_dat, uint16_t len);
|
||||
|
||||
#define rfspi_ce(v) xn297l_write_reg(CE_FSPI_ON|(v), 0)
|
||||
#define rfspi_irq rfspi_pan159_irq
|
||||
#define rfspi_cs rfspi_pan159_cs
|
||||
#define rfspi_init rfspi_pan159_init
|
||||
#define rfspi_rwc rfspi_pan159_rwc
|
||||
#define rfspi_rws rfspi_pan159_rws
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRV_SPI_H
|
||||
@@ -0,0 +1,379 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file driver_swiic_pan159.c
|
||||
* @brief PAN159 GPIO IIC通用驱动
|
||||
*
|
||||
* @history - V1.0, 2017-08-25, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
#include "lib_driver_swiic_pan159.h"
|
||||
#include "string.h"
|
||||
|
||||
#define __swiic_pan159_delay __delay_pan159
|
||||
|
||||
#define __swiic_pan159_mutex_lock(hiic) __disable_irq()
|
||||
#define __swiic_pan159_mutex_unlock(hiic) __enable_irq()
|
||||
|
||||
#define __swiic_pan159_read_sda(hiic) (*((hiic)->sda))
|
||||
#define __swiic_pan159_write_sda(hiic,val) (*((hiic)->sda)=(val))
|
||||
#define __swiic_pan159_write_scl(hiic,val) (*((hiic)->scl)=(val))
|
||||
|
||||
#define __swiic_pan159_set_speed(hiic,spd) ((hiic)->speed.code=(spd))
|
||||
#define __swiic_pan159_get_speed(hiic) ((hiic)->speed.code)
|
||||
|
||||
//#define __swiic_pan159_echo_wclk(hiic) \
|
||||
// do{ \
|
||||
// __swiic_pan159_delay((hiic)->speed.scl_tim_code.l); \
|
||||
// __swiic_pan159_write_scl((hiic),1); \
|
||||
// __swiic_pan159_delay((hiic)->scl_tim_code_h); \
|
||||
// __swiic_pan159_write_scl((hiic),0); \
|
||||
// __swiic_pan159_delay((hiic)->speed.scl_tim_code.l); \
|
||||
// }while(0)
|
||||
void __swiic_pan159_echo_wclk(const swiic_pan159_t* hiic)
|
||||
{
|
||||
__swiic_pan159_delay(hiic->speed.scl_tim_code.l);
|
||||
__swiic_pan159_write_scl(hiic,1);
|
||||
__swiic_pan159_delay(hiic->speed.scl_tim_code.h);
|
||||
__swiic_pan159_write_scl(hiic,0);
|
||||
__swiic_pan159_delay(hiic->speed.scl_tim_code.l);
|
||||
}
|
||||
|
||||
#define __swiic_pan159_echo_rclk(hiic,pret) \
|
||||
do{ \
|
||||
__swiic_pan159_delay((hiic)->speed.scl_tim_code.l); \
|
||||
__swiic_pan159_write_scl((hiic),1); \
|
||||
__swiic_pan159_delay((hiic)->speed.scl_tim_code.l); \
|
||||
*(pret) = __swiic_pan159_read_sda((hiic)); \
|
||||
__swiic_pan159_write_scl((hiic),0); \
|
||||
__swiic_pan159_delay((hiic)->speed.scl_tim_code.l); \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* IIC START SIGNAL:
|
||||
* ___
|
||||
* SDA \_______
|
||||
* ______
|
||||
* SCL / \___
|
||||
*/
|
||||
//#define __swiic_pan159_start(hiic) \
|
||||
// do{ \
|
||||
// __swiic_pan159_write_sda((hiic),1); \
|
||||
// __swiic_pan159_write_scl((hiic),1); \
|
||||
// __swiic_pan159_delay((hiic)->speed.scl_tim_code.l); \
|
||||
// __swiic_pan159_write_sda((hiic),0); \
|
||||
// __swiic_pan159_delay((hiic)->speed.scl_tim_code.l); \
|
||||
// __swiic_pan159_write_scl((hiic),0); \
|
||||
// __swiic_pan159_delay((hiic)->speed.scl_tim_code.l); \
|
||||
// }while(0)
|
||||
void __swiic_pan159_start(const swiic_pan159_t* hiic)
|
||||
{
|
||||
__swiic_pan159_write_sda(hiic,1);
|
||||
__swiic_pan159_write_scl(hiic,1);
|
||||
__swiic_pan159_delay(hiic->speed.scl_tim_code.l);
|
||||
__swiic_pan159_write_sda(hiic,0);
|
||||
__swiic_pan159_delay(hiic->speed.scl_tim_code.l);
|
||||
__swiic_pan159_write_scl(hiic,0);
|
||||
__swiic_pan159_delay(hiic->speed.scl_tim_code.l);
|
||||
}
|
||||
|
||||
/**
|
||||
* IIC STOP SIGNAL:
|
||||
* ___
|
||||
* SDA ___/
|
||||
* ______
|
||||
* SCL /
|
||||
*/
|
||||
//#define __swiic_pan159_stop(hiic) \
|
||||
// do{ \
|
||||
// __swiic_pan159_write_sda((hiic),0); \
|
||||
// __swiic_pan159_write_scl((hiic),1); \
|
||||
// __swiic_pan159_delay((hiic)->scl_tim_code_l); \
|
||||
// __swiic_pan159_write_sda((hiic),1); \
|
||||
// }while(0)
|
||||
void __swiic_pan159_stop(const swiic_pan159_t* hiic)
|
||||
{
|
||||
__swiic_pan159_write_sda(hiic,0);
|
||||
__swiic_pan159_write_scl(hiic,1);
|
||||
__swiic_pan159_delay(hiic->speed.scl_tim_code.l);
|
||||
__swiic_pan159_write_sda(hiic,1);
|
||||
}
|
||||
|
||||
/**
|
||||
* IIC ACK SIGNAL:
|
||||
* _
|
||||
* SDA \___________/
|
||||
* ____
|
||||
* SCL ___/ \_____
|
||||
*/
|
||||
#define __swiic_pan159_write_ack(hiic) \
|
||||
do{ \
|
||||
__swiic_pan159_write_sda((hiic),0); \
|
||||
__swiic_pan159_echo_wclk((hiic)); \
|
||||
__swiic_pan159_write_sda((hiic),1); \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* IIC NACK SIGNAL:
|
||||
* ____________
|
||||
* SDA
|
||||
* ____
|
||||
* SCL ___/ \___
|
||||
*/
|
||||
#define __swiic_pan159_write_nack(hiic) \
|
||||
do{ \
|
||||
__swiic_pan159_write_sda((hiic),1); \
|
||||
__swiic_pan159_echo_wclk((hiic)); \
|
||||
}while(0)
|
||||
|
||||
void __swiic_pan159_write_byte(const swiic_pan159_t *hiic, uint8_t _ubyte)
|
||||
{
|
||||
register uint8_t ubyte = _ubyte;
|
||||
register uint8_t i;
|
||||
for(i = 0; i < 8; i++){
|
||||
__swiic_pan159_write_sda(hiic,((ubyte & 0x80) ? 1 : 0));
|
||||
__swiic_pan159_echo_wclk(hiic);
|
||||
ubyte <<= 1;
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t __swiic_pan159_read_byte(const swiic_pan159_t* hiic)
|
||||
{
|
||||
register uint8_t ubyte = 0;
|
||||
register uint8_t i;
|
||||
for(i = 0; i < 8; i++){
|
||||
ubyte <<= 1;
|
||||
__swiic_pan159_delay(hiic->speed.scl_tim_code.l);
|
||||
__swiic_pan159_write_scl(hiic,1);
|
||||
__swiic_pan159_delay(hiic->speed.scl_tim_code.l);
|
||||
ubyte |= __swiic_pan159_read_sda(hiic);
|
||||
__swiic_pan159_write_scl(hiic,0);
|
||||
__swiic_pan159_delay(hiic->speed.scl_tim_code.l);
|
||||
}
|
||||
return ubyte;
|
||||
}
|
||||
|
||||
uint8_t __swiic_pan159_read_ack(const swiic_pan159_t* hiic)
|
||||
{
|
||||
uint8_t ret;
|
||||
__swiic_pan159_write_sda(hiic,1);
|
||||
__swiic_pan159_echo_rclk(hiic,&ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief GPIO IIC初始化
|
||||
* @param[in] hiic - IIC设备句柄
|
||||
* iic_speed - IIC速率
|
||||
* sda_port_n - SDA端口号
|
||||
* sda_pin_n - SDA引脚号
|
||||
* scl_port_n - SCL端口号
|
||||
* scl_pin_n - SCL引脚号
|
||||
* @return 1 - 成功, 0 - 失败
|
||||
* @history - V1.0, 2017-08-25, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
void swiic_pan159_init(swiic_pan159_t* hiic, uint32_t iic_speed,
|
||||
uint32_t sda_port_n, uint32_t sda_pin_n,
|
||||
uint32_t scl_port_n, uint32_t scl_pin_n)
|
||||
{
|
||||
hiic->sda = &GPIO_PIN_ADDR(sda_port_n,sda_pin_n);
|
||||
hiic->scl = &GPIO_PIN_ADDR(scl_port_n,scl_pin_n);
|
||||
/**
|
||||
* us * 6 - 4 = code
|
||||
* 时钟分布为 low : high = 2 : 1, 因此分为 3 份
|
||||
* ______
|
||||
* \______ ______/ \
|
||||
* low - 2 high - 1
|
||||
* 因此code = us * 2 - 1
|
||||
*/
|
||||
__swiic_pan159_set_speed(hiic, iic_speed);
|
||||
#define __PORT__(n) ((GPIO_T *) (AHBPERIPH_BASE + (0x04000 | ((n) << 6))))
|
||||
#define __PIN__(n) (1 << (n))
|
||||
GPIO_SetMode(__PORT__(sda_port_n),__PIN__(sda_pin_n),GPIO_MODE_OPEN_DRAIN);
|
||||
GPIO_SetMode(__PORT__(scl_port_n),__PIN__(scl_pin_n),GPIO_MODE_OPEN_DRAIN);
|
||||
#undef __PORT__
|
||||
#undef __PIN__
|
||||
__swiic_pan159_stop(hiic);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief GPIO IIC读取(该函数读取具有一定的风险,无法区分读取失败和读到0)
|
||||
* @param[in] dhiic - 目标IIC设备句柄
|
||||
* shiic - 源IIC设备句柄
|
||||
* iic_speed - IIC速率
|
||||
* @return 无
|
||||
* @history - V1.0, 2017-09-12, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
void swiic_pan159_copy(swiic_pan159_t* dhiic, const swiic_pan159_t* shiic, uint32_t iic_speed)
|
||||
{
|
||||
memcpy(dhiic,shiic,sizeof(swiic_pan159_t));
|
||||
if(iic_speed != SWIIC_PAN159_SPEED_SYS_48M_IIC_DEFAULT){
|
||||
__swiic_pan159_set_speed(dhiic,iic_speed);
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief GPIO IIC读取(该函数读取具有一定的风险,无法区分读取失败和读到0)
|
||||
* @param[in] hiic - IIC设备句柄
|
||||
* iic_speed - IIC速率
|
||||
* dev - IIC设备地址
|
||||
* reg - 寄存器地址
|
||||
* @return 读取到的字节
|
||||
* @history - V1.0, 2017-08-25, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
uint8_t swiic_pan159_read_byte(const swiic_pan159_t* hiic, uint8_t dev, uint8_t reg)
|
||||
{
|
||||
register uint8_t ret = 0;
|
||||
__swiic_pan159_mutex_lock(hiic); /* 锁定MUTEX */
|
||||
__swiic_pan159_start(hiic); /* 启动IIC */
|
||||
__swiic_pan159_write_byte(hiic,(dev << 1)|0); /* 写设备地址(写) */
|
||||
if(__swiic_pan159_read_ack(hiic) == 0){ /* 读取ACK */
|
||||
__swiic_pan159_write_byte(hiic,reg); /* 写寄存器地址 */
|
||||
if(__swiic_pan159_read_ack(hiic) == 0){ /* 读取ACK */
|
||||
__swiic_pan159_start(hiic); /* 重启IIC */
|
||||
__swiic_pan159_write_byte(hiic,(dev << 1)|1); /* 写设备地址(读) */
|
||||
if(__swiic_pan159_read_ack(hiic) == 0){ /* 读取ACK */
|
||||
ret = __swiic_pan159_read_byte(hiic); /* 读取数据字节 */
|
||||
__swiic_pan159_write_nack(hiic); /* 回写NACK */
|
||||
} /* */
|
||||
} /* */
|
||||
} /* */
|
||||
__swiic_pan159_stop(hiic); /* 停止IIC */
|
||||
__swiic_pan159_mutex_unlock(hiic); /* 释放MUTEX */
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief GPIO IIC读取
|
||||
* @param[in] hiic - IIC设备句柄
|
||||
* iic_speed - IIC速率
|
||||
* dev - IIC设备地址
|
||||
* reg - 寄存器地址
|
||||
* len - 要读取的数据长度
|
||||
* @param[out] _buf - 数据缓冲区
|
||||
* @return 读取到的字节数
|
||||
* @history - V1.0, 2017-08-25, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
uint32_t swiic_pan159_read_bytes(const swiic_pan159_t* hiic, uint8_t dev, uint8_t reg, uint8_t* buf, uint32_t len)
|
||||
{
|
||||
register uint32_t i = 0;
|
||||
__swiic_pan159_mutex_lock(hiic); /* 锁定MUTEX */
|
||||
__swiic_pan159_start(hiic); /* 启动IIC */
|
||||
__swiic_pan159_write_byte(hiic,(dev << 1)|0); /* 写设备地址(写) */
|
||||
if(__swiic_pan159_read_ack(hiic) == 0){ /* 读取ACK */
|
||||
__swiic_pan159_write_byte(hiic,reg); /* 写寄存器地址 */
|
||||
if(__swiic_pan159_read_ack(hiic) == 0){ /* 读取ACK */
|
||||
__swiic_pan159_start(hiic); /* 重启IIC */
|
||||
__swiic_pan159_write_byte(hiic,(dev << 1)|1); /* 写设备地址(读) */
|
||||
if(__swiic_pan159_read_ack(hiic) == 0){ /* 读取ACK */
|
||||
for(len--; i < len; i++){ /* len中减掉读取数据中的最后一个字节 */
|
||||
buf[i] = __swiic_pan159_read_byte(hiic); /* 读取字节 */
|
||||
__swiic_pan159_write_ack(hiic); /* 回写ACK */
|
||||
} /* */
|
||||
buf[i++] = __swiic_pan159_read_byte(hiic); /* 读取最后一个字节 */
|
||||
__swiic_pan159_write_nack(hiic); /* 回写NACK */
|
||||
} /* */
|
||||
} /* */
|
||||
} /* */
|
||||
__swiic_pan159_stop(hiic); /* 停止IIC */
|
||||
__swiic_pan159_mutex_unlock(hiic); /* 释放MUTEX */
|
||||
return i;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief GPIO IIC写入
|
||||
* @param[in] hiic - IIC设备句柄
|
||||
* iic_speed - IIC速率
|
||||
* dev - IIC设备地址
|
||||
* reg - 寄存器地址
|
||||
* ubyte - 待写入字节
|
||||
* @return 1 - 成功
|
||||
* 0 - 失败
|
||||
* @history - V1.0, 2017-08-25, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
uint8_t swiic_pan159_write_byte(const swiic_pan159_t* hiic, uint8_t dev, uint8_t reg, uint8_t ubyte)
|
||||
{
|
||||
__swiic_pan159_mutex_lock(hiic); /* 锁定MUTEX */
|
||||
__swiic_pan159_start(hiic); /* 启动IIC */
|
||||
__swiic_pan159_write_byte(hiic,(dev << 1)|0); /* 写设备地址(写) */
|
||||
if(__swiic_pan159_read_ack(hiic) == 0){ /* 读取ACK */
|
||||
__swiic_pan159_write_byte(hiic,reg); /* 写寄存器地址 */
|
||||
if(__swiic_pan159_read_ack(hiic) == 0){ /* 读取ACK */
|
||||
__swiic_pan159_write_byte(hiic,ubyte); /* 写字节数据 */
|
||||
ubyte = (__swiic_pan159_read_ack(hiic) == 0) ? 1 : 0; /* 读取ACK */
|
||||
} /* */
|
||||
} /* */
|
||||
__swiic_pan159_stop(hiic); /* 停止IIC */
|
||||
__swiic_pan159_mutex_unlock(hiic); /* 释放MUTEX */
|
||||
return ubyte;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief GPIO IIC写入
|
||||
* @param[in] hiic - IIC设备句柄
|
||||
* iic_speed - IIC速率
|
||||
* dev - IIC设备地址
|
||||
* reg - 寄存器地址
|
||||
* buf - 数据缓冲区
|
||||
* len - 要写入的数据长度
|
||||
* @return 写入的字节数
|
||||
* @history - V1.0, 2017-08-25, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
uint32_t swiic_pan159_write_bytes(const swiic_pan159_t* hiic, uint8_t dev, uint8_t reg, const uint8_t* buf, uint32_t len)
|
||||
{
|
||||
register uint32_t i = 0;
|
||||
__swiic_pan159_mutex_lock(hiic); /* 锁定MUTEX */
|
||||
__swiic_pan159_start(hiic); /* 启动IIC */
|
||||
__swiic_pan159_write_byte(hiic,(dev << 1)|0); /* 写设备地址(写) */
|
||||
if(__swiic_pan159_read_ack(hiic) == 0){ /* 读取ACK */
|
||||
__swiic_pan159_write_byte(hiic,reg); /* 写寄存器地址 */
|
||||
if(__swiic_pan159_read_ack(hiic) == 0){ /* 读取ACK */
|
||||
for(; i < len; i++){ /* */
|
||||
__swiic_pan159_write_byte(hiic,buf[i]); /* 写字节数据 */
|
||||
if(__swiic_pan159_read_ack(hiic) != 0){ /* 读取ACK */
|
||||
break; /* */
|
||||
} /* */
|
||||
} /* */
|
||||
} /* */
|
||||
} /* */
|
||||
__swiic_pan159_stop(hiic); /* 停止IIC */
|
||||
__swiic_pan159_mutex_unlock(hiic); /* 释放MUTEX */
|
||||
return i;
|
||||
}
|
||||
|
||||
swiic_pan159_t imu_iic;
|
||||
swiic_pan159_t bar_iic;
|
||||
//typedef void (*TCallback)(void);
|
||||
void iic_pan159_init(void)
|
||||
{
|
||||
swiic_pan159_init(&imu_iic,0x00030003,3,4,3,5);
|
||||
swiic_pan159_copy(&bar_iic,&imu_iic,0x00030003);
|
||||
}
|
||||
|
||||
void iic_start_send_bytes(uint16_t devAddr,uint8_t regAddr, uint8_t *buf, uint8_t len,TCallback cbk, TCallback fail_cbk)
|
||||
{
|
||||
if(swiic_pan159_write_bytes(&imu_iic, devAddr, regAddr, buf, len)){
|
||||
if(cbk){
|
||||
cbk();
|
||||
}
|
||||
}
|
||||
else{
|
||||
if(fail_cbk){
|
||||
fail_cbk();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void iic_start_read_bytes(uint16_t devAddr,uint8_t regAddr, uint8_t *buf, uint8_t len,TCallback cbk, TCallback fail_cbk)
|
||||
{
|
||||
if(swiic_pan159_read_bytes(&imu_iic, devAddr, regAddr, buf, len)){
|
||||
if(cbk){
|
||||
cbk();
|
||||
}
|
||||
}
|
||||
else{
|
||||
if(fail_cbk){
|
||||
fail_cbk();
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,178 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file driver_swiic_pan159.h
|
||||
* @brief PAN159 GPIO IIC通用驱动
|
||||
*
|
||||
* @history - V1.0, 2017-08-25, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
#ifndef __DRIVER_SWIIC_PAN159_H
|
||||
#define __DRIVER_SWIIC_PAN159_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
#include "lib_driver_delay_pan159.h"
|
||||
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_578K 0x00000000
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_540K 0x00010000
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_515K 0x00020000
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_476K 0x00010001
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_457K 0x00020001
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_426K 0x00020002
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_412K 0x00030002
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_397K 0x00040002
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_385K 0x00030003
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_373K 0x00040003
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_361K 0x00050003
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_351K 0x00060003
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_341K 0x00050004
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_331K 0x00060004
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_322K 0x00070004
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_313K 0x00060005
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_306K 0x00070005
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_298K 0x00080005
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_291K 0x00090005
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_284K 0x00080006
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_278K 0x00090006
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_271K 0x000A0006
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_265K 0x000B0006
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_259K 0x000C0006
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_254K 0x000D0006
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_249K 0x000C0007
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_244K 0x000D0007
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_239K 0x000E0007
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_234K 0x000F0007
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_230K 0x000E0008
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_225K 0x000F0008
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_220K 0x00100008
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_215K 0x00110008
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_200K 0x0010000B
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_190K 0x0011000C
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_181K 0x0010000E
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_171K 0x00100010
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_161K 0x00140010
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_151K 0x00190010
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_141K 0x001E0010
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_129K 0x001E0014
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_119K 0x001E0018
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_108K 0x001E001D
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_100K 0x00220020
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_81K 0x00380023
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_69K 0x00480028
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_54K 0x00580038
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_42K 0x00690050
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_31K 0x00880070
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_20K 0x010000A0
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_10K 0x02000160
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_1K 0x0FFF0F69
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_750 0x1A01123B
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_500 0x20001EDD
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_200 0x60004539
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_FASTEST 0x00000000
|
||||
#define SWIIC_PAN159_SPEED_SYS_48M_IIC_DEFAULT 0xFFFFFFFF
|
||||
|
||||
typedef struct{
|
||||
volatile uint32_t *sda;
|
||||
volatile uint32_t *scl;
|
||||
union{
|
||||
uint32_t code;
|
||||
struct{
|
||||
uint16_t l;
|
||||
uint16_t h;
|
||||
}scl_tim_code;
|
||||
}speed;
|
||||
}swiic_pan159_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief GPIO IIC初始化
|
||||
* @param[in] hiic - IIC设备句柄
|
||||
* iic_speed - IIC速率
|
||||
* sda_port_n - SDA端口号
|
||||
* sda_pin_n - SDA引脚号
|
||||
* scl_port_n - SCL端口号
|
||||
* scl_pin_n - SCL引脚号
|
||||
* @return 无
|
||||
* @history - V1.0, 2017-08-25, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
void swiic_pan159_init(swiic_pan159_t* hiic, uint32_t iic_speed,
|
||||
uint32_t sda_port_n, uint32_t sda_pin_n,
|
||||
uint32_t scl_port_n, uint32_t scl_pin_n);
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief GPIO IIC读取(该函数读取具有一定的风险,无法区分读取失败和读到0)
|
||||
* @param[in] dhiic - 目标IIC设备句柄
|
||||
* shiic - 源IIC设备句柄
|
||||
* iic_speed - IIC速率
|
||||
* @return 无
|
||||
* @history - V1.0, 2017-09-12, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
void swiic_pan159_copy(swiic_pan159_t* dhiic, const swiic_pan159_t* shiic,
|
||||
uint32_t iic_speed);
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief GPIO IIC读取(该函数读取具有一定的风险,无法区分读取失败和读到0)
|
||||
* @param[in] hiic - IIC设备句柄
|
||||
* dev - IIC设备地址
|
||||
* reg - 寄存器地址
|
||||
* @return 读取到的字节
|
||||
* @history - V1.0, 2017-08-25, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
uint8_t swiic_pan159_read_byte(const swiic_pan159_t* hiic,
|
||||
uint8_t dev, uint8_t reg);
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief GPIO IIC读取
|
||||
* @param[in] hiic - IIC设备句柄
|
||||
* dev - IIC设备地址
|
||||
* reg - 寄存器地址
|
||||
* len - 要读取的数据长度
|
||||
* @param[out] _buf - 数据缓冲区
|
||||
* @return 读取到的字节数
|
||||
* @history - V1.0, 2017-08-25, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
uint32_t swiic_pan159_read_bytes(const swiic_pan159_t* hiic,
|
||||
uint8_t dev, uint8_t reg,
|
||||
uint8_t* buf, uint32_t len);
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief GPIO IIC写入
|
||||
* @param[in] hiic - IIC设备句柄
|
||||
* dev - IIC设备地址
|
||||
* reg - 寄存器地址
|
||||
* ubyte - 待写入字节
|
||||
* @return 1 - 成功
|
||||
* 0 - 失败
|
||||
* @history - V1.0, 2017-08-25, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
uint8_t swiic_pan159_write_byte(const swiic_pan159_t* hiic,
|
||||
uint8_t dev, uint8_t reg, uint8_t ubyte);
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief GPIO IIC写入
|
||||
* @param[in] hiic - IIC设备句柄
|
||||
* dev - IIC设备地址
|
||||
* reg - 寄存器地址
|
||||
* buf - 数据缓冲区
|
||||
* len - 要写入的数据长度
|
||||
* @return 写入的字节数
|
||||
* @history - V1.0, 2017-08-25, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
uint32_t swiic_pan159_write_bytes(const swiic_pan159_t* hiic,
|
||||
uint8_t dev, uint8_t reg,
|
||||
const uint8_t* buf, uint32_t len);
|
||||
|
||||
typedef void (*TCallback)(void);
|
||||
void iic_pan159_init(void);
|
||||
void iic_start_send_bytes(uint16_t devAddr,uint8_t regAddr, uint8_t *buf, uint8_t len,TCallback cbk, TCallback fail_cbk);
|
||||
void iic_start_read_bytes(uint16_t devAddr,uint8_t regAddr, uint8_t *buf, uint8_t len,TCallback cbk, TCallback fail_cbk);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __DRIVER_SWIIC_PAN159_H */
|
||||
|
||||
@@ -0,0 +1,105 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file lib_driver_timer_pan159.c
|
||||
* @brief 定时器
|
||||
*
|
||||
* @history - V1.0, 2017-11-16, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
#include "lib_driver_timer_pan159.h"
|
||||
|
||||
static void (*__s_lib_driver_timer_pan159_irq_handler)(void) = NULL;
|
||||
static void (*__s_lib_driver_timer1_pan159_irq_handler)(void) = NULL;
|
||||
/*******************************************************************************
|
||||
* @brief 定时器0初始化
|
||||
* @param[in] 无
|
||||
* @param[out] 无
|
||||
* @return 无
|
||||
* @history - V1.0, 2017-03-07, xiaoguolin, first implementation.
|
||||
******************************************************************************/
|
||||
void timer_pan159_init(uint32_t freq, void(*irq_handler)(void))
|
||||
{
|
||||
CLK_EnableModuleClock(TMR0_MODULE);
|
||||
TIMER_Open(TIMER0, TIMER_PERIODIC_MODE, freq);
|
||||
// Enable timer interrupt
|
||||
if(irq_handler){
|
||||
TIMER_EnableInt(TIMER0);
|
||||
NVIC_EnableIRQ(TMR0_IRQn);
|
||||
NVIC_SetPriority(TMR0_IRQn,2);
|
||||
}
|
||||
__s_lib_driver_timer_pan159_irq_handler = irq_handler;
|
||||
// Start Timer 0.
|
||||
TIMER_Start(TIMER0);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief 定时器0中断处理函数
|
||||
* @param[in] 无
|
||||
* @param[out] 无
|
||||
* @return 无
|
||||
* @history - V1.0, 2017-03-07, xiaoguolin, first implementation.
|
||||
******************************************************************************/
|
||||
void TMR0_IRQHandler(void)
|
||||
{
|
||||
TIMER_ClearIntFlag(TIMER0);
|
||||
if(__s_lib_driver_timer_pan159_irq_handler){
|
||||
__s_lib_driver_timer_pan159_irq_handler();
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* @brief 定时�1初始化
|
||||
* @param[in] 无
|
||||
* @param[out] 无
|
||||
* @return 无
|
||||
* @history - V1.0, 2018-01-19, huoweibin, first implementation.
|
||||
******************************************************************************/
|
||||
void timer1_pan159_init(uint32_t freq, void(*irq_handler)(void))
|
||||
{
|
||||
CLK_EnableModuleClock(TMR1_MODULE);
|
||||
TIMER_Open(TIMER1, TIMER_PERIODIC_MODE, freq);
|
||||
// Enable timer interrupt
|
||||
if(irq_handler){
|
||||
TIMER_EnableInt(TIMER1);
|
||||
NVIC_EnableIRQ(TMR1_IRQn);
|
||||
NVIC_SetPriority(TMR1_IRQn,2);
|
||||
}
|
||||
__s_lib_driver_timer1_pan159_irq_handler = irq_handler;
|
||||
// Start Timer 0.
|
||||
TIMER_Start(TIMER1);
|
||||
}
|
||||
/*******************************************************************************
|
||||
* @brief 定时器1中断处理函数
|
||||
* @param[in] 无
|
||||
* @param[out] 无
|
||||
* @return 无
|
||||
* @history - V1.0, 2018-01-19, huoweibin, first implementation.
|
||||
******************************************************************************/
|
||||
void TMR1_IRQHandler(void)
|
||||
{
|
||||
TIMER_ClearIntFlag(TIMER1);
|
||||
if(__s_lib_driver_timer1_pan159_irq_handler){
|
||||
__s_lib_driver_timer1_pan159_irq_handler();
|
||||
}
|
||||
}
|
||||
|
||||
void DrvTimer0_SetTimer(uint32_t usec)
|
||||
{
|
||||
TIMER_Close(TIMER0);
|
||||
TIMER_Open(TIMER0, TIMER_PERIODIC_MODE, usec);
|
||||
TIMER_EnableInt(TIMER0);
|
||||
//NVIC_EnableIRQ(TMR0_IRQn);
|
||||
//NVIC_SetPriority(TMR0_IRQn,2);
|
||||
TIMER_Start(TIMER0);
|
||||
}
|
||||
|
||||
void DrvTimer1_SetTimer(uint32_t usec)
|
||||
{
|
||||
TIMER_Close(TIMER1);
|
||||
TIMER_Open(TIMER1, TIMER_PERIODIC_MODE, usec);
|
||||
TIMER_EnableInt(TIMER1);
|
||||
//NVIC_EnableIRQ(TMR1_IRQn);
|
||||
//NVIC_SetPriority(TMR1_IRQn,2);
|
||||
TIMER_Start(TIMER1);
|
||||
}
|
||||
@@ -0,0 +1,27 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file lib_driver_timer_pan159.c
|
||||
* @brief ¶¨Ê±Æ÷
|
||||
*
|
||||
* @history - V1.0, 2017-11-16, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
#ifndef __LIB_DRIVER_TIMER_PAN159_H
|
||||
#define __LIB_DRIVER_TIMER_PAN159_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
#include "Mini58Series.h"
|
||||
|
||||
void timer_pan159_init(uint32_t freq, void(*irq_handler)(void));
|
||||
void timer1_pan159_init(uint32_t freq, void(*irq_handler)(void));
|
||||
void DrvTimer0_SetTimer(uint32_t usec);
|
||||
void DrvTimer1_SetTimer(uint32_t usec);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__LIB_DRIVER_TIMER_PAN159_H
|
||||
@@ -0,0 +1,69 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2018 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file lib_driver_uart_pan159.c
|
||||
* @brief PAN159 hardware uartÇý¶¯
|
||||
*
|
||||
* @history - V1.0, 2018-01-19, huoweibin, first implementation.
|
||||
*******************************************************************************/
|
||||
#include "lib_driver_uart_pan159.h"
|
||||
#include "string.h"
|
||||
|
||||
uint8_t uartRcvBuffer[RX_BUF_SIZE],wptr,u8InChar,uartTxBuffer[TX_BUF_SIZE];
|
||||
uint16_t u16Count;
|
||||
uint16_t u16TxDataLen;
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* ISR to handle UART Channel 0 interrupt event */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
void UART0_IRQHandler(void)
|
||||
{
|
||||
uint32_t u32IntSts= UART0->INTSTS;
|
||||
if(u32IntSts & UART_INTSTS_RDAINT_Msk) {
|
||||
/* Get all the input characters */
|
||||
while(UART_IS_RX_READY(UART0)) {
|
||||
/* Get the character from UART Buffer */
|
||||
if(wptr < RX_BUF_SIZE) {
|
||||
uartRcvBuffer[wptr++] = UART_READ(UART0);
|
||||
}
|
||||
else{
|
||||
wptr = 0;
|
||||
uartRcvBuffer[wptr] = UART_READ(UART0);
|
||||
}
|
||||
}
|
||||
}
|
||||
if(u32IntSts & UART_INTSTS_THREINT_Msk) {
|
||||
if(u16Count < u16TxDataLen && u16TxDataLen != 0){
|
||||
u8InChar = uartTxBuffer[u16Count++];
|
||||
UART_WRITE(UART0,u8InChar);
|
||||
if(u16Count >= u16TxDataLen){
|
||||
u16TxDataLen = 0;
|
||||
u16Count = 0;
|
||||
UART_DISABLE_INT(UART0,UART_INTEN_THREIEN_Msk);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void uart_init_pan159(void)
|
||||
{
|
||||
CLK_EnableModuleClock(UART0_MODULE);
|
||||
// SYS->P4_MFP = SYS_MFP_P46_UART1_RXD | SYS_MFP_P47_UART1_TXD;
|
||||
SYS->P5_MFP = SYS_MFP_P51_UART0_RXD | SYS_MFP_P50_UART0_TXD;
|
||||
GPIO_ENABLE_DIGITAL_PATH(P5,(1<<1));
|
||||
// UART_Open(UART1, 115200);
|
||||
UART_Open(UART0, 115200);
|
||||
UART_ENABLE_INT(UART0, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk /*| UART_INTEN_THREIEN_Msk*/));
|
||||
NVIC_EnableIRQ(UART0_IRQn);
|
||||
}
|
||||
|
||||
void uart_send(uint8_t *buff,uint16_t len)
|
||||
{
|
||||
u16TxDataLen = len;
|
||||
u16Count = 0;
|
||||
memcpy(&uartTxBuffer[0],&buff[0],len);
|
||||
UART_ENABLE_INT(UART0,UART_INTEN_THREIEN_Msk);
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,27 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2018 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file lib_driver_uart_pan159.c
|
||||
* @brief PAN159 hardware uartÇý¶¯
|
||||
*
|
||||
* @history - V1.0, 2018-01-19, huoweibin, first implementation.
|
||||
*******************************************************************************/
|
||||
#ifndef __LIB_DIRVER_UART_PAN159_H
|
||||
#define __LIB_DIRVER_UART_PAN159_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
#include "Mini58Series.h"
|
||||
#define RX_BUF_SIZE 32
|
||||
#define TX_BUF_SIZE 32
|
||||
//#define DEBUG_PORT UART1
|
||||
void uart_init_pan159(void);
|
||||
void uart_send(uint8_t *buff,uint16_t len);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __LIB_DIRVER_UART_PAN159_H
|
||||
@@ -0,0 +1,44 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2018 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file lib_driver_wdt_pan159.c
|
||||
* @brief PAN159 hardware wdtÇý¶¯
|
||||
*
|
||||
* @history - V1.0, 2018-01-19, huoweibin, first implementation.
|
||||
*******************************************************************************/
|
||||
#include "lib_driver_wdt_pan159.h"
|
||||
/**
|
||||
* @brief This function make WDT module start counting with different time-out interval
|
||||
* @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are:
|
||||
* - \ref WDT_TIMEOUT_2POW4 -- 1.6MS
|
||||
* - \ref WDT_TIMEOUT_2POW6 -- 6.4MS
|
||||
* - \ref WDT_TIMEOUT_2POW8 -- 25.6MS
|
||||
* - \ref WDT_TIMEOUT_2POW10 -- 102.4MS
|
||||
* - \ref WDT_TIMEOUT_2POW12 -- 409.6MS
|
||||
* - \ref WDT_TIMEOUT_2POW14 -- 1.6384S
|
||||
* - \ref WDT_TIMEOUT_2POW16 -- 6.5536S
|
||||
* - \ref WDT_TIMEOUT_2POW18 -- 26.214S
|
||||
*/
|
||||
void DrvWDT_Init(uint32_t u32TimeoutInterval)
|
||||
{
|
||||
SYS_UnlockReg();
|
||||
CLK->CLKSEL1 |= 0x00000003;
|
||||
SystemCoreClockUpdate();
|
||||
WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk |
|
||||
(TRUE << WDT_CTL_RSTEN_Pos) |
|
||||
(FALSE << WDT_CTL_WKEN_Pos);
|
||||
WDT->ALTCTL = WDT_RESET_DELAY_3CLK;
|
||||
}
|
||||
|
||||
void DrvWDT_Feed(void)
|
||||
{
|
||||
WDT_RESET_COUNTER();
|
||||
}
|
||||
|
||||
void DrvWDT_close(void)
|
||||
{
|
||||
WDT->CTL = 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,26 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2018 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file lib_driver_wdt_pan159.c
|
||||
* @brief PAN159 hardware wdtÇý¶¯
|
||||
*
|
||||
* @history - V1.0, 2018-01-19, huoweibin, first implementation.
|
||||
*******************************************************************************/
|
||||
#ifndef __LIB_DIRVER_WDT_PAN159_H
|
||||
#define __LIB_DIRVER_WDT_PAN159_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
#include "Mini58Series.h"
|
||||
|
||||
void DrvWDT_Init(uint32_t ms);
|
||||
void DrvWDT_Feed(void);
|
||||
void DrvWDT_close(void);
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __LIB_DIRVER_WDT_PAN159_H
|
||||
@@ -0,0 +1,289 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file drv_xn297l.c
|
||||
* @brief XN297L RF驱动
|
||||
*
|
||||
* @history - V1.0, 2017-03-06, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
#include "lib_driver_xn297l.h"
|
||||
|
||||
/******************************************************************************/
|
||||
//void rf_write_reg(uint8_t reg,uint8_t data);
|
||||
//rf写寄存器函数
|
||||
//input:uint8_t reg，寄存器地址；uint8_t data:需要写入寄存器的值
|
||||
//output:无
|
||||
/******************************************************************************/
|
||||
void xn297l_write_reg(uint8_t reg,uint8_t data)
|
||||
{
|
||||
rfspi_cs(0); //使能片选
|
||||
rfspi_rwc(reg); //写入的寄存器的地址
|
||||
rfspi_rwc(data); //写入的寄存器的值
|
||||
rfspi_cs(1); //禁能片选
|
||||
}
|
||||
/******************************************************************************/
|
||||
//uint8_t rf_read_reg(uint8_t reg);
|
||||
//rf读寄存器函数
|
||||
//input:uint8_t reg，需要读取的寄存器
|
||||
//output:寄存器的值
|
||||
/******************************************************************************/
|
||||
uint8_t xn297l_read_reg(uint8_t reg)
|
||||
{
|
||||
uint8_t tmp;
|
||||
rfspi_cs(0); //使能片选
|
||||
rfspi_rwc(reg); //写入的寄存器的地址
|
||||
tmp = rfspi_rwc(0x00); //读取寄存器的值
|
||||
rfspi_cs(1); //禁能片选
|
||||
return tmp;
|
||||
}
|
||||
/******************************************************************************/
|
||||
//void rf_write_buf(uint8_t reg,uint8_t *pbuf,uint8_t length);
|
||||
//rf写缓冲函数
|
||||
//input:uint8_t reg，写入寄存器的地址;uint8_t *pbuf，写入数组的首地址;uint8_t length，写入数据的长度
|
||||
//output:无
|
||||
/******************************************************************************/
|
||||
void xn297l_write_buf(uint8_t reg,uint8_t *pbuf,uint8_t length)
|
||||
{
|
||||
uint8_t i;
|
||||
rfspi_cs(0); //使能片选
|
||||
rfspi_rwc(reg);
|
||||
for(i = 0;i < length; i++)
|
||||
{
|
||||
rfspi_rwc(pbuf[i]); //写入数据
|
||||
}
|
||||
rfspi_cs(1); //禁能片选
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
//void rf_read_buf(uint8_t reg,uint8_t *pbuf,uint8_t length);
|
||||
//rf读缓冲函数
|
||||
//input:uint8_t reg，读出寄存器的地址;uint8_t *pbuf，读出缓冲数组的首地址;uint8_t length，读出数据的长度
|
||||
//output:无
|
||||
/******************************************************************************/
|
||||
void xn297l_read_buf(uint8_t reg, uint8_t *pbuf, uint8_t length)
|
||||
{
|
||||
uint8_t i;
|
||||
rfspi_cs(0); //使能片选
|
||||
rfspi_rwc(reg);
|
||||
for(i = 0; i < length; i++)
|
||||
{
|
||||
pbuf[i] = rfspi_rwc(0x00); //读取数据
|
||||
}
|
||||
rfspi_cs(1); //禁能片选
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
//void rf_tx_mode(void);
|
||||
//XN297L设置为发送模式
|
||||
//input:无
|
||||
//output:无
|
||||
/******************************************************************************/
|
||||
void xn297l_tx_mode(void)
|
||||
{
|
||||
// uint8_t rf_cal_data[] = {0xF6,0x37,0x5D};
|
||||
// rf_write_buf(W_REGISTER + RF_CAL,rf_cal_data, sizeof(rf_cal_data));//设置RF_CAL
|
||||
xn297l_write_reg(W_REGISTER + CONFIG,0x8E); // rf设置为发送模式
|
||||
clear_CE();
|
||||
delay_us(20);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
//void rf_rx_mode(void);
|
||||
//XN297L设置为接收模式
|
||||
//input:无
|
||||
//output:无
|
||||
/******************************************************************************/
|
||||
void xn297l_rx_mode(void)
|
||||
{
|
||||
// uint8_t rf_cal_data[] = {0x06,0x37,0x5D};
|
||||
// rf_write_buf(W_REGISTER + RF_CAL,rf_cal_data, sizeof(rf_cal_data));//设置RF_CAL
|
||||
xn297l_write_reg(W_REGISTER + CONFIG,0X8F); // rf设置为接收模式
|
||||
set_CE();
|
||||
//delay_ms(1);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
//void rf_get_status(void);
|
||||
//XN297L获取状态信息
|
||||
//input:无
|
||||
//output:状态寄存器的值
|
||||
/******************************************************************************/
|
||||
uint8_t xn297l_get_status(void)
|
||||
{
|
||||
return xn297l_read_reg(RF_STATUS)&0x70; //读取状态值
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
//void rf_clear_status(void);
|
||||
//XN297L清除状态信息
|
||||
//input:无
|
||||
//output:无
|
||||
/******************************************************************************/
|
||||
void xn297l_clear_status(void)
|
||||
{
|
||||
xn297l_write_reg(W_REGISTER + RF_STATUS,0x70);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
//void rf_clear_FIFO(void);
|
||||
//XN297L清除缓冲
|
||||
//input:无
|
||||
//output:无
|
||||
/******************************************************************************/
|
||||
void xn297l_clear_fifo(void)
|
||||
{
|
||||
xn297l_write_reg(FLUSH_TX, 0); //清除发送缓冲
|
||||
xn297l_write_reg(FLUSH_RX, 0); //清除接收缓冲
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
//void rf_set_channel(uint8_t channel);
|
||||
//XN297L设置通信信道
|
||||
//input:uint8_t channel，设置的通信信道
|
||||
//output:无
|
||||
/******************************************************************************/
|
||||
void xn297l_set_channel(uint8_t channel)
|
||||
{
|
||||
// current_channel = channel;
|
||||
xn297l_write_reg(W_REGISTER + RF_CH, channel);
|
||||
}
|
||||
/******************************************************************************/
|
||||
//void rf_set_addr(uint8_t reg,uint8_t *rf_addr_array);
|
||||
//XN297L设置通信地址
|
||||
//input:uint8_t reg,需要设置的寄存器，uint8_t *rf_addr_array，设置的地址
|
||||
//output:无
|
||||
/******************************************************************************/
|
||||
void xn297l_set_addr(uint8_t reg,uint8_t *rf_addr_array,uint8_t addr_len)
|
||||
{
|
||||
xn297l_write_buf(W_REGISTER + reg,rf_addr_array, addr_len);//设置地址
|
||||
}
|
||||
/******************************************************************************/
|
||||
//uint8_t rf_tx_data(uint8_t *data, uint8_t length);
|
||||
//XN297L发送数据
|
||||
//input:uint8_t *data，发送数据数组的首地址；uint8_t length发送数据的长度
|
||||
//output:发送状态值
|
||||
/******************************************************************************/
|
||||
void xn297l_tx_data(uint8_t *data, uint8_t length)
|
||||
{
|
||||
set_CE();
|
||||
delay_us(100);
|
||||
xn297l_write_buf(W_TX_PAYLOAD,data,length); //发送数据
|
||||
while(IRQ_STATUS);
|
||||
xn297l_clear_status(); //清除状态
|
||||
xn297l_write_reg(FLUSH_TX,0); //清除发送缓冲
|
||||
clear_CE();
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
//uint8_t rf_rx_data(uint8_t *data,uint8_t length);
|
||||
//rf接收函数
|
||||
//input:uint8_t *data,接收数据数组首地址；uint8_t length:接收数据的长度
|
||||
//output:接收正确与否标志
|
||||
/******************************************************************************/
|
||||
uint8_t xn297l_rx_data(uint8_t *data,uint8_t length)
|
||||
{
|
||||
if(IRQ_STATUS)
|
||||
{
|
||||
return 0; //等待接收
|
||||
}
|
||||
xn297l_read_buf(R_RX_PAYLOAD,data,length); //接收数据
|
||||
xn297l_write_reg(FLUSH_RX,0); //清除接收缓冲
|
||||
xn297l_clear_status(); //清除状态
|
||||
return 1;
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
//void rf_init(void);
|
||||
//rf初始化函数，执行一些初始化操作
|
||||
//input:无
|
||||
//output:无
|
||||
/******************************************************************************/
|
||||
void rf_init(void)
|
||||
{
|
||||
uint8_t addr[] = {0x23,0x23,0x23};
|
||||
rfspi_init();
|
||||
xn297l_init(addr,3,20,13,XN297L_RF_POWER_P_5|XN297L_RF_DATA_RATE_1M);
|
||||
xn297l_rx_mode();
|
||||
}
|
||||
|
||||
void xn297l_init(uint8_t* addr,uint8_t addr_len,uint8_t chn,uint8_t payload,uint8_t rate_power)
|
||||
{
|
||||
#if ((DATA_RATE==DR_1M) || (DATA_RATE==DR_2M))
|
||||
uint8_t BB_cal_data[] = {0x12,0xED,0x67,0x9C,0x46};
|
||||
uint8_t rf_cal_data[] = {0xF6,0x3F,0x5D};
|
||||
uint8_t rf_cal2_data[] = {0x45,0x21,0xEF,0x2C,0x5A,0x40};
|
||||
uint8_t Dem_cal_data[] = {0x01};
|
||||
uint8_t Dem_cal2_data[] = {0x0B,0xDF,0x02};
|
||||
#elif (DATA_RATE==DR_250K)
|
||||
uint8_t BB_cal_data[] = {0x12,0xEC,0x6F,0xA1,0x46};
|
||||
uint8_t rf_cal_data[] = {0xF6,0x3F,0x5D};
|
||||
uint8_t rf_cal2_data[] = {0xD5,0x21,0xEB,0x2C,0x5A,0x40};
|
||||
uint8_t Dem_cal_data[] = {0x1F};
|
||||
uint8_t Dem_cal2_data[] = {0x0B,0xDF,0x02};
|
||||
#endif
|
||||
|
||||
xn297l_write_reg(RST_FSPI,0x5A); //芯片软复位
|
||||
xn297l_write_reg(RST_FSPI,0XA5);
|
||||
delay_ms(1);
|
||||
xn297l_clear_fifo();//清除缓冲
|
||||
xn297l_clear_status(); //清除状态寄存器
|
||||
if(payload < 33)
|
||||
{
|
||||
#if(CE_TYPE==CE_HARDWARE_MODE)
|
||||
xn297l_write_reg(W_REGISTER +FEATURE, 0x00); //32字节数据，使能硬件CE
|
||||
#else
|
||||
xn297l_write_reg(W_REGISTER +FEATURE, 0x20); //32字节数据，使能软件CE
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
#if(CE_TYPE==CE_HARDWARE_MODE)
|
||||
xn297l_write_reg(W_REGISTER +FEATURE, 0x18); //64字节数据，使能硬件CE
|
||||
#else
|
||||
xn297l_write_reg(W_REGISTER +FEATURE, 0x38); //64字节数据，使能软件CE
|
||||
#endif
|
||||
}
|
||||
|
||||
clear_CE();
|
||||
|
||||
xn297l_write_reg(W_REGISTER + EN_RXADDR,0x03); //使能接收通道0通道1
|
||||
xn297l_write_reg(W_REGISTER + SETUP_AW,addr_len-2); //[1-3] = [3-5]
|
||||
xn297l_write_reg(W_REGISTER + RF_CH,chn); //设置接收信道
|
||||
xn297l_write_reg(W_REGISTER + RX_PW_P0,payload); //设置接收数据宽度，即Payload宽度
|
||||
xn297l_write_reg(W_REGISTER + RX_PW_P1,payload); //设置接收数据宽度，即Payload宽度
|
||||
xn297l_write_buf(W_REGISTER + TX_ADDR,addr, addr_len); //设置发送地址
|
||||
xn297l_write_buf(W_REGISTER + RX_ADDR_P0,addr, addr_len); //设置接收地址
|
||||
xn297l_write_buf(W_REGISTER + BB_CAL,BB_cal_data, sizeof(BB_cal_data)); //设置BB_CAL
|
||||
xn297l_write_buf(W_REGISTER + RF_CAL2,rf_cal2_data, sizeof(rf_cal2_data)); //设置RF_CAL2
|
||||
xn297l_write_buf(W_REGISTER + DEM_CAL,Dem_cal_data, sizeof(Dem_cal_data)); //设置DEM_CAL
|
||||
xn297l_write_buf(W_REGISTER + RF_CAL,rf_cal_data, sizeof(rf_cal_data)); //设置RF_CAL
|
||||
xn297l_write_buf(W_REGISTER + DEM_CAL2,Dem_cal2_data,sizeof(Dem_cal2_data));//设置DEM_CAL2
|
||||
xn297l_write_reg(W_REGISTER + DYNPD, 0x00); //禁止动态Payload
|
||||
xn297l_write_reg(W_REGISTER + RF_SETUP,rate_power); //设置发射功率和速率
|
||||
#if(TRANSMIT_TYPE == TRANS_ENHANCE_MODE) //设置为增强模式
|
||||
xn297l_write_reg(W_REGISTER + SETUP_RETR,0x03); //使能三次重发
|
||||
xn297l_write_reg(W_REGISTER + EN_AA, 0x01); //使能自动应答
|
||||
#elif(TRANSMIT_TYPE == TRANS_NORMAL_MODE) //设置为普通模式
|
||||
xn297l_write_reg(W_REGISTER + SETUP_RETR,0x00); //禁止重发
|
||||
xn297l_write_reg(W_REGISTER + EN_AA, 0x00); //禁止自动应答
|
||||
#endif
|
||||
}
|
||||
/******************************************************************************/
|
||||
//单载波模式
|
||||
/******************************************************************************/
|
||||
void RF_Carrier( uint8_t ucChannel_Set)
|
||||
{
|
||||
uint8_t BB_cal_data[] = {0x0A,0x6D,0x67,0x9C,0x46};
|
||||
uint8_t RF_cal_data[] = {0xF6,0x37,0x5D};
|
||||
uint8_t RF_cal2_data[] = {0x45,0x21,0xEF,0xAC,0x5A,0x50};
|
||||
uint8_t Dem_cal_data[] = {0xE1};
|
||||
uint8_t Dem_cal2_data[] = {0x0B,0xDF,0x02};
|
||||
xn297l_write_reg(W_REGISTER + RF_CH,ucChannel_Set);
|
||||
xn297l_write_reg(W_REGISTER + RF_SETUP, 0x3F); //13dbm
|
||||
xn297l_write_buf(W_REGISTER + BB_CAL, BB_cal_data, sizeof(BB_cal_data));
|
||||
xn297l_write_buf(W_REGISTER + RF_CAL2, RF_cal2_data, sizeof(RF_cal2_data));
|
||||
xn297l_write_buf(W_REGISTER + DEM_CAL, Dem_cal_data, sizeof(Dem_cal_data));
|
||||
xn297l_write_buf(W_REGISTER + RF_CAL, RF_cal_data, sizeof(RF_cal_data));
|
||||
xn297l_write_buf(W_REGISTER + DEM_CAL2, Dem_cal2_data,sizeof(Dem_cal2_data));
|
||||
}
|
||||
@@ -0,0 +1,180 @@
|
||||
/*******************************************************************************
|
||||
* @note Copyright (C) 2017 Shanghai Panchip Microelectronics Co., Ltd.
|
||||
* All rights reserved.
|
||||
*
|
||||
* @file drv_xn297l.h
|
||||
* @brief XN297L RF驱动
|
||||
*
|
||||
* @history - V1.0, 2017-03-06, xiaoguolin, first implementation.
|
||||
*******************************************************************************/
|
||||
#ifndef __DRV_XN297L_H
|
||||
#define __DRV_XN297L_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"{
|
||||
#endif
|
||||
|
||||
#include "lib_driver_delay_pan159.h"
|
||||
#include "lib_driver_rfspi_pan159.h"
|
||||
|
||||
#define XN297L_RF_DATA_RATE_1M 0x00
|
||||
#define XN297L_RF_DATA_RATE_2M 0x40
|
||||
#define XN297L_RF_DATA_RATE_250K 0xC0
|
||||
|
||||
#define USER_RF_POWER (CONF_RF_REMOTE_POWER|CONF_RF_REMOTE_RATE)
|
||||
//#define MONITOR_RF_POWER (CONF_RF_CONGLEX_POWER|CONF_RF_DONGLEX_RATE)
|
||||
|
||||
#define TRANS_ENHANCE_MODE 1 //发送增强模式
|
||||
#define TRANS_NORMAL_MODE 2 //发送普通模式
|
||||
#define TRANSMIT_TYPE TRANS_NORMAL_MODE //初始设置为普通模式
|
||||
|
||||
#define RX_DR_FLAG 0x40 // 接收中断标志位
|
||||
#define TX_DS_FLAG 0x20 // 发送完成中断标志位
|
||||
#define RX_TX_FLAG 0x60 // 发送接收完成中断标志位，ack_payload 模式下使用
|
||||
#define MAX_RT_FLAG 0x10 // 发送重传超时中断标志位
|
||||
|
||||
#define XN297L_RF_POWER_P_11 0x27 /** 11dBm */
|
||||
#define XN297L_RF_POWER_P_10 0x26 /** 10dBm */
|
||||
#define XN297L_RF_POWER_P_9 0x15 /** 9dBm */
|
||||
#define XN297L_RF_POWER_P_5 0x2c /** 5dBm */
|
||||
#define XN297L_RF_POWER_P_4 0x14 /** 4dBm */
|
||||
#define XN297L_RF_POWER_N_1 0x2A /** -1dBm */
|
||||
#define XN297L_RF_POWER_N_9 0x29 /** -9dBm */
|
||||
#define XN297L_RF_POWER_N_10 0x19 /** -10dBm */
|
||||
#define XN297L_RF_POWER_N_23 0x30 /** -23dBm */
|
||||
|
||||
#if( (DATA_RATE ==DR_1M) || (DATA_RATE==DR_2M) )
|
||||
|
||||
#define rf7dBm 0X0D // 7dBm 只能用于1M过安规用
|
||||
#define rf6dBm 0X06 // 6dBm 只能用于1M过安规用
|
||||
#define rf3dBm 0X0C // 3dBm 只能用于1M过安规用
|
||||
|
||||
#endif
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
//XN297L寄存器操作命令
|
||||
#define RF_READ_REG 0x00 //读配置寄存器,低5位为寄存器地址
|
||||
#define RF_WRITE_REG 0x20 //写配置寄存器,低5位为寄存器地址
|
||||
#define W_REGISTER 0x20 //写配置寄存器,低5位为寄存器地址
|
||||
#define R_RX_PAYLOAD 0x61 //读RX有效数据, 1~32字节
|
||||
#define W_TX_PAYLOAD 0xA0 //写TX有效数据,1~32字节
|
||||
#define FLUSH_TX 0xE1 //清除TX FIFO寄存器.发射模式下用
|
||||
#define FLUSH_RX 0xE2 //清除RX FIFO寄存器.接收模式下用
|
||||
#define REUSE_TX_PL 0xE3 //重新使用上一包数据,CE为高,数据包被不断发送.
|
||||
#define NOP 0xFF //空操作,可以用来读状态寄存器
|
||||
|
||||
|
||||
#define ACTIVATE 0x50 //ACTIVATE
|
||||
#define DEACTIVATE 0x50 //DEACTIVATE
|
||||
#define R_RX_PL_WID 0x60 //Read width of RX data
|
||||
#define W_ACK_PAYLOAD 0xA8 //Data with ACK
|
||||
#define W_TX_PAYLOAD_NOACK 0xB0 //TX Payload no ACK Request
|
||||
#define CE_FSPI_ON 0xFD // CE HIGH
|
||||
#define CE_FSPI_OFF 0xFC // CE LOW
|
||||
#define RST_FSPI 0x53 // RESET
|
||||
|
||||
|
||||
//SPI(XN297L)寄存器地址
|
||||
#define CONFIG 0x00 //配置寄存器地址;bit0:1接收模式,0发射模式;bit1:电选择;bit2:CRC模式;bit3:CRC使能;
|
||||
//bit4:中断MAX_RT(达到最大重发次数中断)使能;bit5:中断TX_DS使能;bit6:中断RX_DR使能
|
||||
#define EN_AA 0x01 //使能自动应答功能 bit0~5,对应通道0~5
|
||||
#define EN_RXADDR 0x02 //接收地址允许,bit0~5,对应通道0~5
|
||||
#define SETUP_AW 0x03 //设置地址宽度(所有数据通道):bit1,0:00,3字节;01,4字节;02,5字节;
|
||||
#define SETUP_RETR 0x04 //建立自动重发;bit3:0,自动重发计数器;bit7:4,自动重发延时 250*x+86us
|
||||
#define RF_CH 0x05 //rf通道,bit6:0,工作通道频率;
|
||||
#define RF_SETUP 0x06 //rf寄存器;bit3:传输速率(0:1Mbps,1:2Mbps);bit2:1,发射功率;bit0:低噪声放大器增益
|
||||
#define RF_STATUS 0x07 //状态寄存器;bit0:TX FIFO满标志;bit3:1,接收数据通道号(最大:6);bit4,达到最多次重发
|
||||
//bit5:数据发送完成中断;bit6:接收数据中断;
|
||||
#define MAX_TX 0x10 //达到最大发送次数中断
|
||||
#define TX_OK 0x20 //TX发送完成中断
|
||||
#define RX_OK 0x40 //接收到数据中断
|
||||
|
||||
#define OBSERVE_TX 0x08 //传输状态寄存器,bit7:4,数据包丢失计数器;bit3:0,重发计数器
|
||||
#define CD 0x09 //载波检测寄存器,bit0,载波检测;
|
||||
#define RX_ADDR_P0 0x0A //数据通道0接收地址,最大长度5个字节,低字节在前
|
||||
#define RX_ADDR_P1 0x0B //数据通道1接收地址,最大长度5个字节,低字节在前
|
||||
#define RX_ADDR_P2 0x0C //数据通道2接收地址,最低字节可设置,高字节,必须同RX_ADDR_P1[39:8]相等;
|
||||
#define RX_ADDR_P3 0x0D //数据通道3接收地址,最低字节可设置,高字节,必须同RX_ADDR_P1[39:8]相等;
|
||||
#define RX_ADDR_P4 0x0E //数据通道4接收地址,最低字节可设置,高字节,必须同RX_ADDR_P1[39:8]相等;
|
||||
#define RX_ADDR_P5 0x0F //数据通道5接收地址,最低字节可设置,高字节,必须同RX_ADDR_P1[39:8]相等;
|
||||
#define TX_ADDR 0x10 //发送地址(低字节在前),ShockBurstTM模式下,RX_ADDR_P0与此地址相等
|
||||
#define RX_PW_P0 0x11 //接收数据通道0有效数据宽度(1~32字节),设置为0则非法
|
||||
#define RX_PW_P1 0x12 //接收数据通道1有效数据宽度(1~32字节),设置为0则非法
|
||||
#define RX_PW_P2 0x13 //接收数据通道2有效数据宽度(1~32字节),设置为0则非法
|
||||
#define RX_PW_P3 0x14 //接收数据通道3有效数据宽度(1~32字节),设置为0则非法
|
||||
#define RX_PW_P4 0x15 //接收数据通道4有效数据宽度(1~32字节),设置为0则非法
|
||||
#define RX_PW_P5 0x16 //接收数据通道5有效数据宽度(1~32字节),设置为0则非法
|
||||
#define FIFO_STATUS 0x17 //FIFO状态寄存器;bit0,RX FIFO寄存器空标志;bit1,RX FIFO满标志;bit2,3,保留
|
||||
//bit4,TX FIFO空标志;bit5,TX FIFO满标志;bit6,1,循环发送上一数据包.0,不循环;
|
||||
|
||||
#define DEM_CAL 0x19
|
||||
#define RF_CAL2 0x1A
|
||||
#define DEM_CAL2 0x1B
|
||||
#define DYNPD 0x1C
|
||||
#define FEATURE 0x1D
|
||||
#define RF_CAL 0x1E
|
||||
#define BB_CAL 0x1F
|
||||
|
||||
|
||||
#define USER_CHN CONF_RF_REMOTE_CHN //通信信道设置
|
||||
#define MONITOR_CHN CONF_RF_DONGLEX_CHN //监测通信信道设置
|
||||
#define PAYLOAD_WIDTH CONF_RF_REMOTE_RX_PAYLOAD_WIDTH //XN297L发送接收数据宽度定义
|
||||
#define MONITOR_WIDTH CONF_RF_DONGLEX_TX_PAYLOAD_WIDTH
|
||||
//#define TX_ADR_WIDTH 5 //5字节的地址宽度
|
||||
//#define RX_ADR_WIDTH 5 //5字节的地址宽度
|
||||
//#define TX_PLOAD_WIDTH 32 //32字节的用户数据宽度
|
||||
//#define RX_PLOAD_WIDTH 32 //32字节的用户数据宽度
|
||||
|
||||
#define CE_SOFTWARE_MODE 1 //CE软件模式
|
||||
#define CE_HARDWARE_MODE 2 //CE硬件模式
|
||||
#define CE_TYPE CE_HARDWARE_MODE //设置为硬件模式
|
||||
|
||||
#define IRQ_STATUS rfspi_irq()
|
||||
#define CSN_HIGH P01=1
|
||||
#define CSN_LOW P01=0
|
||||
|
||||
//#if 0
|
||||
////PAN163
|
||||
//#if(CE_TYPE==CE_HARDWARE_MODE)
|
||||
// #define set_CE() (P02=1)
|
||||
// #define clear_CE() (P02=0)
|
||||
//#else
|
||||
// #define set_CE() (xn297l_write_reg(CE_FSPI_ON, 0))//内部置位CE
|
||||
// #define clear_CE() (xn297l_write_reg(CE_FSPI_OFF, 0))//内部拉低CE
|
||||
//#endif
|
||||
//#endif
|
||||
////PAN159
|
||||
//#define set_CE() (xn297l_write_reg(CE_FSPI_ON, 0))//内部置位CE
|
||||
//#define clear_CE() (xn297l_write_reg(CE_FSPI_OFF, 0))//内部拉低CE
|
||||
|
||||
|
||||
#if(CE_TYPE==CE_HARDWARE_MODE)
|
||||
#define set_CE() rfspi_ce(1)
|
||||
#define clear_CE() rfspi_ce(0)
|
||||
#else
|
||||
#define set_CE() (xn297l_write_reg(CE_FSPI_ON, 0))//内部置位CE
|
||||
#define clear_CE() (xn297l_write_reg(CE_FSPI_OFF, 0))//内部拉低CE
|
||||
#endif
|
||||
|
||||
void xn297l_write_reg(uint8_t reg,uint8_t data);//rf写寄存器函数
|
||||
uint8_t xn297l_read_reg(uint8_t reg);//rf读寄存器函数
|
||||
void xn297l_write_buf(uint8_t reg,uint8_t *pbuf,uint8_t length);//rf写缓冲函数
|
||||
void xn297l_read_buf(uint8_t reg,uint8_t *pbuf,uint8_t length);//rf读缓冲函数
|
||||
//void xn297l_init(void);//rf初始化
|
||||
void xn297l_init(uint8_t* addr,uint8_t addr_len,uint8_t chn,uint8_t payload,uint8_t rate_power);
|
||||
void xn297l_tx_mode(void);//XN297L设置为发送模式
|
||||
void xn297l_rx_mode(void);//XN297L设置为接收模式
|
||||
uint8_t xn297l_get_status(void);//XN297L获取状态信息
|
||||
void xn297l_clear_status(void);//XN297L清除状态信息
|
||||
void xn297l_clear_fifo(void);//XN297L清除缓冲
|
||||
void xn297l_set_channel(uint8_t channel);//XN297L设置通信信道
|
||||
void xn297l_tx_data(uint8_t *data, uint8_t length);//XN297L发送数据
|
||||
uint8_t xn297l_rx_data(uint8_t *data,uint8_t length);//rf接收函数
|
||||
void xn297l_set_addr(uint8_t reg,uint8_t *rf_addr_array,uint8_t addr_len);//rf设置通信地址
|
||||
void rf_init(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __DRV_XN297L_H
|
||||
@@ -0,0 +1,323 @@
|
||||
/**************************************************************************//**
|
||||
* @file acmp.h
|
||||
* @version V1.00
|
||||
* $Revision: 4 $
|
||||
* $Date: 15/05/26 5:56p $
|
||||
* @brief Mini58 series Analog Comparator(ACMP) driver header file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __ACMP_H__
|
||||
#define __ACMP_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_ACMP_Driver ACMP Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
#define ACMP_VNEG_PIN (0xFFUL) ///< Selecting the voltage of ACMP negative input pin as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_BANDGAP (0x00UL) ///< Selecting band-gap voltage as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_4_OVER_24_VDD (0x80UL) ///< Selecting 4/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_5_OVER_24_VDD (0x81UL) ///< Selecting 5/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_6_OVER_24_VDD (0x82UL) ///< Selecting 6/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_7_OVER_24_VDD (0x83UL) ///< Selecting 7/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_8_OVER_24_VDD (0x84UL) ///< Selecting 8/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_9_OVER_24_VDD (0x85UL) ///< Selecting 9/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_10_OVER_24_VDD (0x86UL) ///< Selecting 10/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_11_OVER_24_VDD (0x87UL) ///< Selecting 11/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_12_OVER_24_VDD (0x88UL) ///< Selecting 12/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_13_OVER_24_VDD (0x89UL) ///< Selecting 13/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_14_OVER_24_VDD (0x8AUL) ///< Selecting 14/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_15_OVER_24_VDD (0x8BUL) ///< Selecting 15/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_16_OVER_24_VDD (0x8CUL) ///< Selecting 16/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_17_OVER_24_VDD (0x8DUL) ///< Selecting 17/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_18_OVER_24_VDD (0x8EUL) ///< Selecting 18/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_VNEG_19_OVER_24_VDD (0x8FUL) ///< Selecting 19/24 VDD as the source of ACMP V- \hideinitializer
|
||||
#define ACMP_HYSTERESIS_ENABLE (1UL << ACMP_CTL_HYSSEL_Pos) ///< Enable hysteresis function \hideinitializer
|
||||
#define ACMP_HYSTERESIS_DISABLE (0UL) ///< Disable hysteresis function \hideinitializer
|
||||
#define ACMP_CH0_POSPIN_P15 (0UL) ///< Selecting P1.5 as ACMP Channel 0 positive input pin \hideinitializer
|
||||
#define ACMP_CH0_POSPIN_P10 (1UL << ACMP_CTL_POSSEL_Pos) ///< Selecting P1.0 as ACMP Channel 0 positive input pin \hideinitializer
|
||||
#define ACMP_CH0_POSPIN_P12 (2UL << ACMP_CTL_POSSEL_Pos) ///< Selecting P1.2 as ACMP Channel 0 positive input pin \hideinitializer
|
||||
#define ACMP_CH0_POSPIN_P13 (3UL << ACMP_CTL_POSSEL_Pos) ///< Selecting P1.3 as ACMP Channel 0 positive input pin \hideinitializer
|
||||
#define ACMP_CH1_POSPIN_P31 (0UL) ///< Selecting P3.1 as ACMP Channel 1 positive input pin \hideinitializer
|
||||
#define ACMP_CH1_POSPIN_P32 (1UL << ACMP_CTL_POSSEL_Pos) ///< Selecting P3.2 as ACMP Channel 1 positive input pin \hideinitializer
|
||||
#define ACMP_CH1_POSPIN_P34 (2UL << ACMP_CTL_POSSEL_Pos) ///< Selecting P3.4 as ACMP Channel 1 positive input pin \hideinitializer
|
||||
#define ACMP_CH1_POSPIN_P35 (3UL << ACMP_CTL_POSSEL_Pos) ///< Selecting P3.5 as ACMP Channel 1 positive input pin \hideinitializer
|
||||
#define ACMP_FILTSEL_OFF (0UL) ///< Comparator output filter function is disabled \hideinitializer
|
||||
#define ACMP_FILTSEL_1PCLK (1UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 1 consecutive PCLK \hideinitializer
|
||||
#define ACMP_FILTSEL_2PCLK (2UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 2 consecutive PCLKs \hideinitializer
|
||||
#define ACMP_FILTSEL_4PCLK (3UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 4 consecutive PCLKs \hideinitializer
|
||||
#define ACMP_FILTSEL_8PCLK (4UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 8 consecutive PCLKs \hideinitializer
|
||||
#define ACMP_FILTSEL_16PCLK (5UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 16 consecutive PCLKs \hideinitializer
|
||||
#define ACMP_FILTSEL_32PCLK (6UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 32 consecutive PCLKs \hideinitializer
|
||||
#define ACMP_FILTSEL_64PCLK (7UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 64 consecutive PCLKs \hideinitializer
|
||||
#define ACMP_FILTSEL_128PCLK (8UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 128 consecutive PCLKs \hideinitializer
|
||||
#define ACMP_FILTSEL_256PCLK (9UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 256 consecutive PCLKs \hideinitializer
|
||||
#define ACMP_FILTSEL_512PCLK (10UL << ACMP_CTL_FILTSEL_Pos) ///< Comparator output filter is sampled 512 consecutive PCLKs \hideinitializer
|
||||
|
||||
/*@}*/ /* end of group Mini58_ACMP_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup Mini58_ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This macro is used to select ACMP negative input source
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number, ether 0 or 1
|
||||
* @param[in] u32Src is comparator negative input selection. Including :
|
||||
* - \ref ACMP_VNEG_PIN
|
||||
* - \ref ACMP_VNEG_BANDGAP
|
||||
* - \ref ACMP_VNEG_4_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_5_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_6_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_7_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_8_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_9_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_10_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_11_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_12_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_13_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_14_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_15_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_16_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_17_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_18_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_19_OVER_24_VDD
|
||||
*
|
||||
* @return None
|
||||
* @note The V- setting is shared by both comparators if input source is not coming from PIN
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) do{\
|
||||
if(u32Src == ACMP_VNEG_PIN)\
|
||||
ACMP->CTL[u32ChNum] &= ~ACMP_CTL_NEGSEL_Msk;\
|
||||
else {\
|
||||
ACMP->CTL[u32ChNum] |= ACMP_CTL_NEGSEL_Msk;\
|
||||
ACMP->VREF = u32Src;\
|
||||
}\
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to enable hysteresis function
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number, ether 0 or 1
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_HYSSEL_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to disable hysteresis function
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number, ether 0 or 1
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_HYSSEL_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to enable interrupt
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number, ether 0 or 1
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_ENABLE_INT(acmp, u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPIE_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to disable interrupt
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number, ether 0 or 1
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_DISABLE_INT(acmp, u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPIE_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief This macro is used to enable ACMP
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_ENABLE(acmp, u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_ACMPEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to disable ACMP
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number, ether 0 or 1
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_DISABLE(acmp, u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_ACMPEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to get ACMP output value
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number, ether 0 or 1
|
||||
* @return 1 or 0
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_GET_OUTPUT(acmp, u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPO0_Msk<<(u32ChNum))?1:0)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to get ACMP interrupt flag
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number, ether 0 or 1
|
||||
* @return ACMP interrupt occurred or not
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (ACMP->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum))?1:0)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to clear ACMP interrupt flag
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number, ether 0 or 1
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) (ACMP->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<(u32ChNum)))
|
||||
|
||||
/**
|
||||
* @brief This macro is used to select the V+ pin of ACMP
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number, ether 0 or 1
|
||||
* @param[in] u32Pin The input pin. For channel 0, valid values are \ref ACMP_CH0_POSPIN_P15,
|
||||
* \ref ACMP_CH0_POSPIN_P10, \ref ACMP_CH0_POSPIN_P12, and \ref ACMP_CH0_POSPIN_P13. For
|
||||
* channel 1, valid values are , \ref ACMP_CH1_POSPIN_P31, \ref ACMP_CH1_POSPIN_P32,
|
||||
* \ref ACMP_CH1_POSPIN_P34, and \ref ACMP_CH1_POSPIN_P35.
|
||||
* @return None
|
||||
* @note Except this setting, multi-function pin also needs to be configured
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) (ACMP->CTL[u32ChNum] = (ACMP->CTL[u32ChNum] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
|
||||
/**
|
||||
* @brief This macro is used to set the level of CRV(Comparator Reference Voltage)
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32Level CRV level, possible values are
|
||||
* - \ref ACMP_VNEG_4_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_5_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_6_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_7_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_8_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_9_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_10_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_11_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_12_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_13_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_14_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_15_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_16_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_17_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_18_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_19_OVER_24_VDD
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_CRV_SEL(acmp, u32Level) (ACMP->VREF = (ACMP->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level) & ~ACMP_VREF_IREFSEL_Msk))
|
||||
/**
|
||||
* @brief This macro is used to enable CRV(Comparator Reference Voltage)
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_ENABLE_CRV(acmp) (ACMP->VREF |= ACMP_VREF_IREFSEL_Msk)
|
||||
/**
|
||||
* @brief This macro is used to disable CRV(Comparator Reference Voltage)
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_DISABLE_CRV(acmp) (ACMP->VREF &= ~ACMP_VREF_IREFSEL_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to enable ACMP falling edge trigger Timer/PWM
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number, ether 0 or 1
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_ENABLE_FALLING_EDGE_TRIGGER(acmp, u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_FTRGEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to disable ACMP falling edge trigger Timer/PWM
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number, ether 0 or 1
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_DISABLE_FALLING_EDGE_TRIGGER(acmp, u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_FTRGEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to enable ACMP rising edge trigger Timer/PWM
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number, ether 0 or 1
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_ENABLE_RISING_EDGE_TRIGGER(acmp, u32ChNum) (ACMP->CTL[u32ChNum] |= ACMP_CTL_RTRGEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to disable ACMP rising edge trigger Timer/PWM
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum The ACMP number, ether 0 or 1
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_DISABLE_RISING_EDGE_TRIGGER(acmp, u32ChNum) (ACMP->CTL[u32ChNum] &= ~ACMP_CTL_RTRGEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to set ACMP filter function
|
||||
* @param[in] acmp The pointer of the specified ACMP module
|
||||
* @param[in] u32ChNum The ACMP number
|
||||
* @param[in] u32Cnt is comparator filter count setting.
|
||||
* - \ref ACMP_FILTSEL_OFF
|
||||
* - \ref ACMP_FILTSEL_1PCLK
|
||||
* - \ref ACMP_FILTSEL_2PCLK
|
||||
* - \ref ACMP_FILTSEL_4PCLK
|
||||
* - \ref ACMP_FILTSEL_8PCLK
|
||||
* - \ref ACMP_FILTSEL_16PCLK
|
||||
* - \ref ACMP_FILTSEL_32PCLK
|
||||
* - \ref ACMP_FILTSEL_64PCLK
|
||||
* - \ref ACMP_FILTSEL_128PCLK
|
||||
* - \ref ACMP_FILTSEL_256PCLK
|
||||
* - \ref ACMP_FILTSEL_512PCLK
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[u32ChNum] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))
|
||||
|
||||
void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn);
|
||||
void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum);
|
||||
|
||||
/*@}*/ /* end of group Mini58_ACMP_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_ACMP_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__ACMP_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,299 @@
|
||||
/**************************************************************************//**
|
||||
* @file adc.h
|
||||
* @version V1.00
|
||||
* $Revision: 3 $
|
||||
* $Date: 15/06/03 9:34p $
|
||||
* @brief Mini58 series ADC driver header file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __ADC_H__
|
||||
#define __ADC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_ADC_Driver ADC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_ADC_EXPORTED_CONSTANTS ADC Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
#define ADC_CH7_EXT (0UL) /*!< Use external input pin as ADC channel 7 source */
|
||||
#define ADC_CH7_BGP (ADC_CHEN_CH7SEL_Msk) /*!< Use internal band-gap voltage (VBG) as channel 7 source. */
|
||||
#define ADC_CMP0_LESS_THAN (0UL << ADC_CMP0_CMPCOND_Pos) /*!< ADC compare condition less than */
|
||||
#define ADC_CMP1_LESS_THAN (0UL << ADC_CMP1_CMPCOND_Pos) /*!< ADC compare condition less than */
|
||||
#define ADC_CMP0_GREATER_OR_EQUAL_TO (1ul << ADC_CMP0_CMPCOND_Pos) /*!< ADC compare condition greater or equal to */
|
||||
#define ADC_CMP1_GREATER_OR_EQUAL_TO (1ul << ADC_CMP1_CMPCOND_Pos) /*!< ADC compare condition greater or equal to */
|
||||
#define ADC_TRIGGER_BY_EXT_PIN (0UL) /*!< ADC trigger by STADC (P3.2) pin */
|
||||
#define ADC_TRIGGER_BY_PWM (ADC_CTL_HWTRGSEL_Msk) /*!< ADC trigger by PWM events */
|
||||
#define ADC_FALLING_EDGE_TRIGGER (0UL) /*!< External pin falling edge trigger ADC */
|
||||
#define ADC_RISING_EDGE_TRIGGER (ADC_CTL_HWTRGCOND_Msk) /*!< External pin rising edge trigger ADC */
|
||||
#define ADC_ADIF_INT (ADC_STATUS_ADIF_Msk) /*!< ADC convert complete interrupt */
|
||||
#define ADC_CMP0_INT (ADC_STATUS_ADCMPF0_Msk) /*!< ADC comparator 0 interrupt */
|
||||
#define ADC_CMP1_INT (ADC_STATUS_ADCMPF1_Msk) /*!< ADC comparator 0 interrupt */
|
||||
#define ADC_SAMPLE_CLOCK_0 (0UL) /*!< ADC sample time is 0 ADC clock */
|
||||
#define ADC_SAMPLE_CLOCK_1 (1UL) /*!< ADC sample time is 1 ADC clock */
|
||||
#define ADC_SAMPLE_CLOCK_2 (2UL) /*!< ADC sample time is 2 ADC clock */
|
||||
#define ADC_SAMPLE_CLOCK_4 (3UL) /*!< ADC sample time is 4 ADC clock */
|
||||
#define ADC_SAMPLE_CLOCK_8 (4UL) /*!< ADC sample time is 8 ADC clock */
|
||||
#define ADC_SAMPLE_CLOCK_16 (5UL) /*!< ADC sample time is 16 ADC clock */
|
||||
#define ADC_SAMPLE_CLOCK_32 (6UL) /*!< ADC sample time is 32 ADC clock */
|
||||
#define ADC_SAMPLE_CLOCK_64 (7UL) /*!< ADC sample time is 64 ADC clock */
|
||||
#define ADC_SAMPLE_CLOCK_128 (8UL) /*!< ADC sample time is 128 ADC clock */
|
||||
#define ADC_SAMPLE_CLOCK_256 (9UL) /*!< ADC sample time is 256 ADC clock */
|
||||
#define ADC_SAMPLE_CLOCK_512 (10UL) /*!< ADC sample time is 512 ADC clock */
|
||||
#define ADC_SAMPLE_CLOCK_1024 (11UL) /*!< ADC sample time is 1024 ADC clock */
|
||||
#define ADC_SEQMODE_TYPE_23SHUNT (0UL) /*!< ADC sequential mode 23-shunt type */
|
||||
#define ADC_SEQMODE_TYPE_1SHUNT (1UL) /*!< ADC sequential mode 1-shunt type */
|
||||
#define ADC_SEQMODE_MODESELECT_CH01 (0UL) /*!< ADC channel 0 then channel 1 conversion */
|
||||
#define ADC_SEQMODE_MODESELECT_CH12 (1UL) /*!< ADC channel 1 then channel 2 conversion */
|
||||
#define ADC_SEQMODE_MODESELECT_CH02 (2UL) /*!< ADC channel 0 then channel 2 conversion */
|
||||
#define ADC_SEQMODE_PWM0_RISING (0UL) /*!< ADC sequential mode PWM0 rising trigger ADC*/
|
||||
#define ADC_SEQMODE_PWM0_CENTER (1UL) /*!< ADC sequential mode PWM0 center trigger ADC*/
|
||||
#define ADC_SEQMODE_PWM0_FALLING (2UL) /*!< ADC sequential mode PWM0 falling trigger ADC*/
|
||||
#define ADC_SEQMODE_PWM0_PERIOD (3UL) /*!< ADC sequential mode PWM0 period trigger ADC*/
|
||||
#define ADC_SEQMODE_PWM2_RISING (4UL) /*!< ADC sequential mode PWM2 rising trigger ADC*/
|
||||
#define ADC_SEQMODE_PWM2_CENTER (5UL) /*!< ADC sequential mode PWM2 center trigger ADC*/
|
||||
#define ADC_SEQMODE_PWM2_FALLING (6UL) /*!< ADC sequential mode PWM2 falling trigger ADC*/
|
||||
#define ADC_SEQMODE_PWM2_PERIOD (7UL) /*!< ADC sequential mode PWM2 period trigger ADC*/
|
||||
#define ADC_SEQMODE_PWM4_RISING (8UL) /*!< ADC sequential mode PWM4 rising trigger ADC*/
|
||||
#define ADC_SEQMODE_PWM4_CENTER (9UL) /*!< ADC sequential mode PWM4 center trigger ADC*/
|
||||
#define ADC_SEQMODE_PWM4_FALLING (10UL) /*!< ADC sequential mode PWM4 falling trigger ADC*/
|
||||
#define ADC_SEQMODE_PWM4_PERIOD (11UL) /*!< ADC sequential mode PWM4 period trigger ADC*/
|
||||
/*@}*/ /* end of group Mini58_ADC_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup Mini58_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configure the analog input source of channel 7
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32Source Decides the analog input source of channel 7, valid values are
|
||||
* - \ref ADC_CH7_EXT
|
||||
* - \ref ADC_CH7_BGP
|
||||
* @return None
|
||||
* @note While using VBG as channel 7 source, ADC module clock must /b not exceed 300kHz
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_CONFIG_CH7(adc, u32Source) (ADC->CHEN = ((adc)->CHEN & ~ADC_CHEN_CH7SEL_Msk) | (u32Source))
|
||||
|
||||
/**
|
||||
* @brief Get the latest ADC conversion data
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32ChNum Currently not used
|
||||
* @return Latest ADC conversion data
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_GET_CONVERSION_DATA(adc, u32ChNum) ((adc)->DAT & ADC_DAT_RESULT_Msk)
|
||||
|
||||
/**
|
||||
* @brief Return the user-specified interrupt flags
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
|
||||
* - \ref ADC_ADIF_INT
|
||||
* - \ref ADC_CMP0_INT
|
||||
* - \ref ADC_CMP1_INT
|
||||
* @return User specified interrupt flags
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_GET_INT_FLAG(adc, u32Mask) ((adc)->STATUS & (u32Mask))
|
||||
|
||||
/**
|
||||
* @brief This macro clear the selected interrupt status bits
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32Mask The combination of following interrupt status bits. Each bit corresponds to a interrupt status.
|
||||
* - \ref ADC_ADIF_INT
|
||||
* - \ref ADC_CMP0_INT
|
||||
* - \ref ADC_CMP1_INT
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_CLR_INT_FLAG(adc, u32Mask) ((adc)->STATUS = ((adc)->STATUS & ~(ADC_STATUS_ADIF_Msk | \
|
||||
ADC_STATUS_ADCMPF0_Msk | \
|
||||
ADC_STATUS_ADCMPF1_Msk)) | (u32Mask))
|
||||
|
||||
/**
|
||||
* @brief Get the busy state of ADC
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @return busy state of ADC
|
||||
* @retval 0 ADC is not busy
|
||||
* @retval 1 ADC is busy
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_IS_BUSY(adc) ((adc)->STATUS & ADC_STATUS_BUSY_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Check if the ADC conversion data is over written or not
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32ChNum Currently not used
|
||||
* @return Over run state of ADC data
|
||||
* @retval 0 ADC data is not overrun
|
||||
* @retval 1 ADC data is overrun
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_IS_DATA_OVERRUN(adc, u32ChNum) ((adc)->STATUS & ADC_STATUS_OV_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Check if the ADC conversion data is valid or not
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32ChNum Currently not used
|
||||
* @return Valid state of ADC data
|
||||
* @retval 0 ADC data is not valid
|
||||
* @retval 1 ADC data us valid
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_IS_DATA_VALID(adc, u32ChNum) ((adc)->STATUS & ADC_STATUS_VALID_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief Power down ADC module
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_POWER_DOWN(adc) ((adc)->CTL &= ~ADC_CTL_ADCEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Power on ADC module
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_POWER_ON(adc) ((adc)->CTL |= ADC_CTL_ADCEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Configure the comparator 0 and enable it
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7
|
||||
* @param[in] u32Condition Specifies the compare condition
|
||||
* - \ref ADC_CMP0_LESS_THAN
|
||||
* - \ref ADC_CMP0_GREATER_OR_EQUAL_TO
|
||||
* @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF
|
||||
* @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16
|
||||
* @return None
|
||||
* @details For example, ADC_ENABLE_CMP0(ADC, 5, ADC_CMP_GREATER_OR_EQUAL_TO, 0x800, 10);
|
||||
* Means ADC will assert comparator 0 flag if channel 5 conversion result is
|
||||
* greater or equal to 0x800 for 10 times continuously.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_ENABLE_CMP0(adc, \
|
||||
u32ChNum, \
|
||||
u32Condition, \
|
||||
u32Data, \
|
||||
u32MatchCount) (ADC->CMP0 = ((u32ChNum) << ADC_CMP0_CMPCH_Pos) | \
|
||||
(u32Condition) | \
|
||||
((u32Data) << ADC_CMP0_CMPDAT_Pos) | \
|
||||
(((u32MatchCount) - 1) << ADC_CMP0_CMPMCNT_Pos) |\
|
||||
ADC_CMP0_ADCMPIE_Msk |\
|
||||
ADC_CMP0_ADCMPEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable comparator 0
|
||||
* @param[in] adc Base address of ADC module
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_DISABLE_CMP0(adc) ((adc)->CMP0 = 0)
|
||||
|
||||
/**
|
||||
* @brief Configure the comparator 1 and enable it
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32ChNum Specifies the source channel, valid value are from 0 to 7
|
||||
* @param[in] u32Condition Specifies the compare condition
|
||||
* - \ref ADC_CMP1_LESS_THAN
|
||||
* - \ref ADC_CMP1_GREATER_OR_EQUAL_TO
|
||||
* @param[in] u32Data Specifies the compare value. Valid value are between 0 ~ 0x3FF
|
||||
* @param[in] u32MatchCount Specifies the match count setting, valid values are between 1~16
|
||||
* @return None
|
||||
* @details For example, ADC_ENABLE_CMP1(ADC, 5, ADC_CMP1_GREATER_OR_EQUAL_TO, 0x800, 10);
|
||||
* Means ADC will assert comparator 1 flag if channel 5 conversion result is
|
||||
* greater or equal to 0x800 for 10 times continuously.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_ENABLE_CMP1(adc, \
|
||||
u32ChNum, \
|
||||
u32Condition, \
|
||||
u32Data, \
|
||||
u32MatchCount) (ADC->CMP1 = ((u32ChNum) << ADC_CMP1_CMPCH_Pos) | \
|
||||
(u32Condition) | \
|
||||
((u32Data) << ADC_CMP1_CMPDAT_Pos) | \
|
||||
((u32MatchCount - 1) << ADC_CMP1_CMPMCNT_Pos) |\
|
||||
ADC_CMP1_ADCMPEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable comparator 1
|
||||
* @param[in] adc Base address of ADC module
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_DISABLE_CMP1(adc) ((adc)->CMP1 = 0)
|
||||
|
||||
/**
|
||||
* @brief Set ADC input channel. Enabled channel will be converted while ADC starts.
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32Mask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1...
|
||||
* @return None
|
||||
* @note Mini58 series MCU ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel
|
||||
* with smallest number will be convert.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_SET_INPUT_CHANNEL(adc, u32Mask) ((adc)->CHEN = (ADC->CHEN & ~ADC_CHEN_CHEN0_Msk) | (u32Mask))
|
||||
|
||||
/**
|
||||
* @brief Start the A/D conversion.
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_START_CONV(adc) ((adc)->CTL |= ADC_CTL_SWTRG_Msk)
|
||||
|
||||
/**
|
||||
* @brief Stop the A/D conversion.
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define ADC_STOP_CONV(adc) ((adc)->CTL &= ~ADC_CTL_SWTRG_Msk)
|
||||
|
||||
void ADC_Open(ADC_T *adc,
|
||||
uint32_t u32InputMode,
|
||||
uint32_t u32OpMode,
|
||||
uint32_t u32ChMask);
|
||||
void ADC_Close(ADC_T *adc);
|
||||
void ADC_EnableHWTrigger(ADC_T *adc,
|
||||
uint32_t u32Source,
|
||||
uint32_t u32Param);
|
||||
void ADC_DisableHWTrigger(ADC_T *adc);
|
||||
void ADC_SetExtraSampleTime(ADC_T *adc,
|
||||
uint32_t u32ChNum,
|
||||
uint32_t u32SampleTime);
|
||||
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask);
|
||||
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask);
|
||||
|
||||
void ADC_SeqModeEnable(ADC_T *adc, uint32_t u32SeqTYPE, uint32_t u32ModeSel);
|
||||
void ADC_SeqModeTriggerSrc(ADC_T *adc, uint32_t u32SeqModeTriSrc1, uint32_t u32SeqModeTriSrc2);
|
||||
|
||||
/*@}*/ /* end of group Mini58_ADC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_ADC_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__ADC_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,263 @@
|
||||
/**************************************************************************//**
|
||||
* @file clk.h
|
||||
* @version V1.00
|
||||
* $Revision: 16 $
|
||||
* $Date: 15/06/05 9:38a $
|
||||
* @brief Mini58 series CLK driver header file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __CLK_H__
|
||||
#define __CLK_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_CLK_Driver CLK Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @addtogroup Mini58_CLK_EXPORTED_CONSTANTS CLK Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
#define FREQ_25MHZ 25000000
|
||||
#define FREQ_50MHZ 50000000
|
||||
#define FREQ_72MHZ 72000000
|
||||
#define FREQ_100MHZ 100000000
|
||||
#define FREQ_200MHZ 200000000
|
||||
#define FREQ_250MHZ 250000000
|
||||
#define FREQ_500MHZ 500000000
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* PWRCTL constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_PWRCTL_XTL12M 0x01UL /*!< Setting External Crystal Oscillator as 12MHz */
|
||||
#define CLK_PWRCTL_XTLEN_HXT 0x01UL /*!< Setting External Crystal Oscillator as 12MHz */
|
||||
#define CLK_PWRCTL_XTL32K 0x02UL /*!< Setting External Crystal Oscillator as 32KHz */
|
||||
#define CLK_PWRCTL_XTLEN_LXT 0x02UL /*!< Setting External Crystal Oscillator as 32KHz */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CLKSEL0 constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_CLKSEL0_HCLKSEL_XTAL 0x00UL /*!< Setting clock source as external XTAL */
|
||||
#define CLK_CLKSEL0_HCLKSEL_HXT 0x00UL /*!< Setting clock source as external HXT */
|
||||
#define CLK_CLKSEL0_HCLKSEL_LXT 0x00UL /*!< Setting clock source as external LXT */
|
||||
#define CLK_CLKSEL0_HCLKSEL_PLL 0x02UL /*!< Setting clock source as PLL */
|
||||
#define CLK_CLKSEL0_HCLKSEL_LIRC 0x03UL /*!< Setting clock source as internal 10KHz RC clock */
|
||||
#define CLK_CLKSEL0_HCLKSEL_HIRC 0x07UL /*!< Setting clock source as internal RC clock */
|
||||
#define CLK_CLKSEL0_STCLKSEL_XTAL 0x00UL /*!< Setting clock source as external XTAL */
|
||||
#define CLK_CLKSEL0_STCLKSEL_XTAL_DIV2 0x10UL /*!< Setting clock source as external XTAL/2 */
|
||||
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 0x18UL /*!< Setting clock source as HCLK/2 */
|
||||
#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 0x38UL /*!< Setting clock source as internal RC clock/2 */
|
||||
#define CLK_CLKSEL0_STCLKSEL_HCLK 0x08UL /*!< Setting clock source as HCLK */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CLKSEL1 constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_CLKSEL1_WDTSEL_XTAL 0x00000000UL /*!< Setting WDT clock source as external XTAL */
|
||||
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 0x00000002UL /*!< Setting WDT clock source as HCLK/2048 */
|
||||
#define CLK_CLKSEL1_WDTSEL_IRC10K 0x00000003UL /*!< Setting WDT clock source as internal 10KHz RC clock */
|
||||
#define CLK_CLKSEL1_WDTSEL_LIRC 0x00000003UL /*!< Setting WDT clock source as internal 10KHz RC clock */
|
||||
#define CLK_CLKSEL1_ADCSEL_XTAL 0x00000000UL /*!< Setting ADC clock source as external XTAL */
|
||||
#define CLK_CLKSEL1_ADCSEL_PLL 0x00000004UL /*!< Setting ADC clock source as PLL */
|
||||
#define CLK_CLKSEL1_ADCSEL_HCLK 0x00000008UL /*!< Setting ADC clock source as HCLK */
|
||||
#define CLK_CLKSEL1_ADCSEL_HIRC 0x0000000CUL /*!< Setting ADC clock source as internal RC clock */
|
||||
#define CLK_CLKSEL1_SPISEL_XTAL 0x00000000UL /*!< Setting SPI clock source as HXT or LXT */
|
||||
#define CLK_CLKSEL1_SPISEL_HCLK 0x00000010UL /*!< Setting SPI clock source as HCLK */
|
||||
#define CLK_CLKSEL1_SPISEL_PLL 0x00000020UL /*!< Setting SPI clock source as PLL */
|
||||
#define CLK_CLKSEL1_TMR0SEL_XTAL 0x00000000UL /*!< Setting Timer 0 clock source as external XTAL */
|
||||
#define CLK_CLKSEL1_TMR0SEL_LIRC 0x00000100UL /*!< Setting Timer 0 clock source as internal 10KHz RC clock */
|
||||
#define CLK_CLKSEL1_TMR0SEL_HCLK 0x00000200UL /*!< Setting Timer 0 clock source as HCLK */
|
||||
#define CLK_CLKSEL1_TMR0SEL_TM0 0x00000300UL /*!< Setting Timer 0 clock source as external trigger */
|
||||
#define CLK_CLKSEL1_TMR0SEL_HIRC 0x00000700UL /*!< Setting Timer 0 clock source as internal RC clock */
|
||||
#define CLK_CLKSEL1_TMR1SEL_XTAL 0x00000000UL /*!< Setting Timer 1 clock source as external XTAL */
|
||||
#define CLK_CLKSEL1_TMR1SEL_LIRC 0x00001000UL /*!< Setting Timer 1 clock source as internal 10KHz RC clock */
|
||||
#define CLK_CLKSEL1_TMR1SEL_HCLK 0x00002000UL /*!< Setting Timer 1 clock source as HCLK */
|
||||
#define CLK_CLKSEL1_TMR1SEL_TM1 0x00003000UL /*!< Setting Timer 1 clock source as external trigger */
|
||||
#define CLK_CLKSEL1_TMR1SEL_HIRC 0x00007000UL /*!< Setting Timer 1 clock source as internal RC clock */
|
||||
#define CLK_CLKSEL1_UARTSEL_XTAL 0x00000000UL /*!< Setting UART clock source as external XTAL */
|
||||
#define CLK_CLKSEL1_UARTSEL_PLL 0x01000000UL /*!< Setting UART clock source as external PLL */
|
||||
#define CLK_CLKSEL1_UARTSEL_HIRC 0x02000000UL /*!< Setting UART clock source as external internal RC clock */
|
||||
#define CLK_CLKSEL1_PWMCH01SEL_HCLK 0x20000000UL /*!< Setting PWM01 clock source as external HCLK */
|
||||
#define CLK_CLKSEL1_PWMCH23SEL_HCLK 0x80000000UL /*!< Setting PWM23 clock source as external HCLK */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CLKSEL2 constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_CLKSEL2_CLKOSEL_XTAL 0x00000000UL /*!< Setting CLKODIV clock source as external XTAL */
|
||||
#define CLK_CLKSEL2_CLKOSEL_HXT 0x00000000UL /*!< Setting CLKODIV clock source as external XTAL */
|
||||
#define CLK_CLKSEL2_CLKOSEL_LXT 0x00000000UL /*!< Setting CLKODIV clock source as external XTAL */
|
||||
#define CLK_CLKSEL2_CLKOSEL_LIRC 0x00000004UL /*!< Setting CLKODIV clock source as LIRC */
|
||||
#define CLK_CLKSEL2_CLKOSEL_HCLK 0x00000008UL /*!< Setting CLKODIV clock source as HCLK */
|
||||
#define CLK_CLKSEL2_CLKOSEL_HIRC 0x0000000CUL /*!< Setting CLKODIV clock source as internal RC clock */
|
||||
#define CLK_CLKSEL2_PWMCH45SEL_HCLK 0x00000020UL /*!< Setting PWMCH45 clock source as HCLK */
|
||||
#define CLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 0x00020000UL /*!< Setting WWDT clock source as HCLK/2048 */
|
||||
#define CLK_CLKSEL2_WWDTSEL_LIRC 0x00030000UL /*!< Setting WWDT clock source as internal RC clock */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* CLKDIV constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_CLKDIV_ADC(x) (((x)-1) << 16) /*!< CLKDIV Setting for ADC clock divider. It could be 1~256 */
|
||||
#define CLK_CLKDIV_UART(x) (((x)-1) << 8) /*!< CLKDIV Setting for UART clock divider. It could be 1~16 */
|
||||
#define CLK_CLKDIV_HCLK(x) ((x)-1) /*!< CLKDIV Setting for HCLK clock divider. It could be 1~16 */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* PLLCTL constant definitions. PLL = FIN * NF / NR / NO */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 3.2MHz < FIN < 150MHz */
|
||||
#define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 3.2MHz < FIN < 150MHz */
|
||||
|
||||
#define CLK_PLLCTL_NF(x) ((x)-2) /*!< x must be constant and 2 <= x <= 513. 200MHz < FIN*NF/NR < 500MHz. (FIN*NF/NR > 250MHz is preferred.) */
|
||||
#define CLK_PLLCTL_NR(x) (((x)-2)<<9) /*!< x must be constant and 2 <= x <= 33. 1.6MHz < FIN/NR < 16MHz */
|
||||
|
||||
#define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 */
|
||||
#define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 */
|
||||
#define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 */
|
||||
|
||||
#define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 24) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) */
|
||||
#define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF( 32) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 96MHz PLL output with HXT(12MHz X'tal) */
|
||||
#define CLK_PLLCTL_100MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3) | CLK_PLLCTL_NF( 50) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 100MHz PLL output with HXT(12MHz X'tal) */
|
||||
|
||||
#define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 26) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 71.884800MHz PLL output with HIRC(22.1184MHz X'tal) */
|
||||
#define CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(13)| CLK_PLLCTL_NF(113) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 96.129968MHz PLL output with HIRC(22.1184MHz X'tal) */
|
||||
#define CLK_PLLCTL_100MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(4) | CLK_PLLCTL_NF( 36) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 99.532800MHz PLL output with HIRC(22.1184MHz X'tal) */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* MODULE constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define MODULE_APBCLK(x) ((x >>31) & 0x1) /*!< Calculate APBCLK offset on MODULE index */
|
||||
#define MODULE_CLKSEL(x) ((x >>29) & 0x3) /*!< Calculate CLKSEL offset on MODULE index */
|
||||
#define MODULE_CLKSEL_Msk(x) ((x >>25) & 0xf) /*!< Calculate CLKSEL mask offset on MODULE index */
|
||||
#define MODULE_CLKSEL_Pos(x) ((x >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index */
|
||||
#define MODULE_CLKDIV(x) ((x >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index */
|
||||
#define MODULE_CLKDIV_Msk(x) ((x >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index */
|
||||
#define MODULE_CLKDIV_Pos(x) ((x >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index */
|
||||
#define MODULE_IP_EN_Pos(x) ((x >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index */
|
||||
#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index */
|
||||
#define NA MODULE_NoMsk /*!< Not Available */
|
||||
|
||||
#define MODULE_APBCLK_ENC(x) (((x) & 0x01) << 31) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK */
|
||||
#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 29) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1 0x3 CLKSEL2*/
|
||||
#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0f) << 25) /*!< CLKSEL mask offset on MODULE index */
|
||||
#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) /*!< CLKSEL position offset on MODULE index */
|
||||
#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV */
|
||||
#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) /*!< CLKDIV mask offset on MODULE index */
|
||||
#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) /*!< CLKDIV position offset on MODULE index */
|
||||
#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) /*!< APBCLK offset on MODULE index */
|
||||
/*-------------------------------------------------------------------------------------------------------------------------------*/
|
||||
/* APBCLK(1) | CLKSEL(2) | CLKSEL_Msk(4) | CLKSEL_Pos(5) | CLKDIV(2) | CLKDIV_Msk(8) | CLKDIV_Pos(5) | IP_EN_Pos(5)*/
|
||||
/*-------------------------------------------------------------------------------------------------------------------------------*/
|
||||
#define ISP_MODULE (( 0UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 2<<0)) /*!< ISP Module \hideinitializer */
|
||||
#define WDT_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 0<<0)) /*!< WDT Module \hideinitializer */
|
||||
#define TMR0_MODULE (( 1UL<<31)|( 1<<29)|( 7<<25)|( 8<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 2<<0)) /*!< TMR0 Module \hideinitializer */
|
||||
#define TMR1_MODULE (( 1UL<<31)|( 1<<29)|( 7<<25)|(12<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 3<<0)) /*!< TMR1 Module \hideinitializer */
|
||||
#define CLKO_MODULE (( 1UL<<31)|( 3<<29)|( 3<<25)|( 2<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 6<<0)) /*!< CLKO Module \hideinitializer */
|
||||
#define I2C0_MODULE (( 1UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 8<<0)) /*!< I2C0 Module \hideinitializer */
|
||||
#define I2C1_MODULE (( 1UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 9<<0)) /*!< I2C1 Module \hideinitializer */
|
||||
#define SPI0_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|( 4<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(12<<0)) /*!< SPI Module \hideinitializer */
|
||||
#define UART0_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(24<<20)|( 0<<18)|( 0xF<<10)|( 8<<5)|(16<<0)) /*!< UART0 Module \hideinitializer */
|
||||
#define UART1_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(24<<20)|( 0<<18)|( 0xF<<10)|( 8<<5)|(17<<0)) /*!< UART1 Module \hideinitializer */
|
||||
#define PWMCH01_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(28<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(20<<0)) /*!< PWMCH01 Module \hideinitializer */
|
||||
#define PWMCH23_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|(30<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(21<<0)) /*!< PWMCH23 Module \hideinitializer */
|
||||
#define PWMCH45_MODULE (( 1UL<<31)|( 3<<29)|( 3<<25)|( 4<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(22<<0)) /*!< PWMCH45 Module \hideinitializer */
|
||||
#define ADC_MODULE (( 1UL<<31)|( 1<<29)|( 3<<25)|( 2<<20)|( 0<<18)|( 0xFF<<10)|(16<<5)|(28<<0)) /*!< ADC Module \hideinitializer */
|
||||
#define ACMP_MODULE (( 1UL<<31)|( 0<<29)|( MODULE_NoMsk<<25)|( 0<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|(30<<0)) /*!< ACMP Module \hideinitializer */
|
||||
#define WWDT_MODULE (( 1UL<<31)|( 3<<29)|( 3<<25)|(16<<20)|( 0<<18)|( MODULE_NoMsk<<10)|( 0<<5)|( 0<<0)) /*!< WWDT Module \hideinitializer */
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_CLK_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup Mini58_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Get PLL clock frequency
|
||||
* @param None
|
||||
* @return PLL frequency
|
||||
* @details This function get PLL frequency. The frequency unit is Hz.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t CLK_GetPLLClockFreq(void)
|
||||
{
|
||||
uint32_t u32PllFreq = 0, u32PllReg;
|
||||
uint32_t u32FIN, u32NF, u32NR, u32NO;
|
||||
uint8_t au8NoTbl[4] = {1, 2, 2, 4};
|
||||
|
||||
u32PllReg = CLK->PLLCTL;
|
||||
|
||||
if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk))
|
||||
return 0; /* PLL is in power down mode or fix low */
|
||||
|
||||
if(u32PllReg & CLK_PLLCTL_PLLSRC_HIRC)
|
||||
u32FIN = __HIRC; /* PLL source clock from HIRC */
|
||||
else
|
||||
u32FIN = __XTAL; /* PLL source clock from HXT */
|
||||
|
||||
if(u32PllReg & CLK_PLLCTL_BP_Msk)
|
||||
return u32FIN; /* PLL is in bypass mode */
|
||||
|
||||
/* PLL is output enabled in normal work mode */
|
||||
u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)];
|
||||
u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2;
|
||||
u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 2;
|
||||
|
||||
/* u32FIN is shifted 2 bits to avoid overflow */
|
||||
u32PllFreq = (((u32FIN >> 2) * u32NF) / (u32NR * u32NO) << 2);
|
||||
|
||||
return u32PllFreq;
|
||||
}
|
||||
|
||||
void CLK_DisableCKO(void);
|
||||
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
|
||||
void CLK_PowerDown(void);
|
||||
void CLK_Idle(void);
|
||||
uint32_t CLK_GetHXTFreq(void);
|
||||
uint32_t CLK_GetLXTFreq(void);
|
||||
uint32_t CLK_GetHCLKFreq(void);
|
||||
uint32_t CLK_GetCPUFreq(void);
|
||||
uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
|
||||
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
|
||||
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
|
||||
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
|
||||
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
|
||||
void CLK_DisableSysTick(void);
|
||||
void CLK_EnableXtalRC(uint32_t u32ClkMask);
|
||||
void CLK_DisableXtalRC(uint32_t u32ClkMask);
|
||||
void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
|
||||
void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
|
||||
void CLK_SysTickDelay(uint32_t us);
|
||||
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
|
||||
void CLK_DisablePLL(void);
|
||||
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_CLK_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_CLK_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__CLK_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,111 @@
|
||||
/**************************************************************************//**
|
||||
* @file FMC.h
|
||||
* @version V1.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 15/05/26 12:39p $
|
||||
* @brief Mini58 series FMC driver header file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
******************************************************************************/
|
||||
#ifndef __FMC_H__
|
||||
#define __FMC_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_FMC_Driver FMC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_FMC_EXPORTED_CONSTANTS FMC Exported Constants
|
||||
@{
|
||||
*/
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Define Base Address */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */
|
||||
#define FMC_APROM_END 0x00008000UL /*!< APROM End Address */
|
||||
#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */
|
||||
#define FMC_LDROM_END 0x00100A00UL /*!< LDROM End Address */
|
||||
#define FMC_SPROM_BASE 0x00200000UL /*!< SPROM Base Address */
|
||||
#define FMC_SPROM_END 0x00200200UL /*!< SPROM End Address */
|
||||
#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */
|
||||
|
||||
#define FMC_FLASH_PAGE_SIZE 0x200 /*!< Flash Page Size (512 Bytes) */
|
||||
#define FMC_LDROM_SIZE 0xA00 /*!< LDROM Size (2 Kbytes) */
|
||||
#define FMC_SPROM_SIZE 0x200 /*!< SPROM Size (512 bytes) */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* ISPCMD constant definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define FMC_ISPCMD_READ 0x00 /*!< ISP Command: Read Flash */
|
||||
#define FMC_ISPCMD_READ_UID 0x04 /*!< ISP Command: Read Unique ID */
|
||||
#define FMC_ISPCMD_READ_CID 0x0B /*!< ISP Command: Read Company ID */
|
||||
#define FMC_ISPCMD_READ_PID 0x0C /*!< ISP Command: Read Product ID */
|
||||
#define FMC_ISPCMD_READ_CRC32 0x0D /*!< ISP Command: Read CRC32 checksum */
|
||||
#define FMC_ISPCMD_PROGRAM 0x21 /*!< ISP Command: Program Flash */
|
||||
#define FMC_ISPCMD_PAGE_ERASE 0x22 /*!< ISP Command: Page Erase Flash */
|
||||
#define FMC_ISPCMD_CAL_CRC32 0x2D /*!< ISP Command: Run CRC32 checksum calculation */
|
||||
#define FMC_ISPCMD_VECMAP 0x2E /*!< ISP Command: Vector Page Remap */
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_FMC_EXPORTED_CONSTANTS */
|
||||
|
||||
/** @addtogroup Mini58_FMC_EXPORTED_FUNCTIONS FMC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
#define FMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk) /*!< Select booting from APROM */
|
||||
#define FMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk) /*!< Select booting from LDROM */
|
||||
#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM update */
|
||||
#define FMC_DISABLE_SP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_SPUEN_Msk) /*!< Disable SPROM update */
|
||||
#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable User Config update */
|
||||
#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM update */
|
||||
#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP function */
|
||||
#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM update */
|
||||
#define FMC_ENABLE_SP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_SPUEN_Msk) /*!< Enable SPROM update */
|
||||
#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM update */
|
||||
#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable User Config update */
|
||||
#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP function */
|
||||
#define FMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1 : 0) /*!< Get ISP fail flag */
|
||||
|
||||
|
||||
extern void FMC_Close(void);
|
||||
extern int32_t FMC_Erase(uint32_t u32PageAddr);
|
||||
extern int32_t FMC_GetBootSource(void);
|
||||
extern void FMC_Open(void);
|
||||
extern uint32_t FMC_Read (uint32_t u32Addr);
|
||||
extern uint32_t FMC_ReadCID(void);
|
||||
extern uint32_t FMC_ReadPID(void);
|
||||
extern uint32_t FMC_ReadUCID(uint32_t u32Index);
|
||||
extern uint32_t FMC_ReadUID(uint32_t u32Index);
|
||||
extern uint32_t FMC_ReadDataFlashBaseAddr(void);
|
||||
extern void FMC_SetVectorPageAddr(uint32_t u32PageAddr);
|
||||
extern uint32_t FMC_GetVectorPageAddr(void);
|
||||
extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data);
|
||||
extern int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count);
|
||||
extern int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count);
|
||||
extern int32_t FMC_GetCRC32Sum(uint32_t addr, uint32_t count, uint32_t *chksum);
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_FMC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_FMC_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,375 @@
|
||||
/**************************************************************************//**
|
||||
* @file gpio.h
|
||||
* @version V1.00
|
||||
* $Revision: 3 $
|
||||
* $Date: 15/06/11 4:13p $
|
||||
* @brief Mini58 series GPIO driver header file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __GPIO_H__
|
||||
#define __GPIO_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_GPIO_Driver GPIO Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define GPIO_PIN_MAX 8 /*!< Specify Maximum Pins of Each GPIO Port */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* MODE Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode */
|
||||
#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode */
|
||||
#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */
|
||||
#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* GPIO Interrupt Type Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */
|
||||
#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */
|
||||
#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */
|
||||
#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */
|
||||
#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* IMD Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define GPIO_INTTYPE_EDGE 0UL /*!< INTTYPE Setting for Edge Trigger Mode */
|
||||
#define GPIO_INTTYPE_LEVEL 1UL /*!< INTTYPE Setting for Edge Level Mode */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* DBNCECON Constant Definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< DBCTL setting for all IO pins edge detection circuit is always active after reset */
|
||||
#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */
|
||||
|
||||
#define GPIO_DBCTL_DBCLKSRC_IRC10K 0x00000010UL /*!< DBCTL setting for de-bounce counter clock source is the internal 10 kHz */
|
||||
#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< DBCTL setting for de-bounce counter clock source is the internal HCLK */
|
||||
|
||||
#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< DBCTL setting for sampling cycle = 1 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< DBCTL setting for sampling cycle = 2 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< DBCTL setting for sampling cycle = 4 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< DBCTL setting for sampling cycle = 8 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< DBCTL setting for sampling cycle = 16 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< DBCTL setting for sampling cycle = 32 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< DBCTL setting for sampling cycle = 64 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< DBCTL setting for sampling cycle = 128 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< DBCTL setting for sampling cycle = 256 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< DBCTL setting for sampling cycle = 512 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< DBCTL setting for sampling cycle = 1024 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< DBCTL setting for sampling cycle = 2048 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< DBCTL setting for sampling cycle = 4096 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< DBCTL setting for sampling cycle = 8192 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< DBCTL setting for sampling cycle = 16384 clocks */
|
||||
#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< DBCTL setting for sampling cycle = 32768 clocks */
|
||||
|
||||
/** Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
|
||||
* Example 1:
|
||||
*
|
||||
* P00 = 1;
|
||||
*
|
||||
* It is used to set P0.0 to high;
|
||||
*
|
||||
* Example 2:
|
||||
*
|
||||
* if (P00)
|
||||
* P00 = 0;
|
||||
*
|
||||
* If P0.0 pin status is high, then set P0.0 data output to low.
|
||||
*/
|
||||
#define GPIO_PIN_ADDR(port, pin) (*((volatile uint32_t *)((GPIOBIT0_BASE+(0x20*(port))) + ((pin)<<2))))
|
||||
#define P00 GPIO_PIN_ADDR(0, 0) /*!< Specify P00 Pin Data Input/Output */
|
||||
#define P01 GPIO_PIN_ADDR(0, 1) /*!< Specify P01 Pin Data Input/Output */
|
||||
#define P02 GPIO_PIN_ADDR(0, 2) /*!< Specify P02 Pin Data Input/Output */
|
||||
#define P03 GPIO_PIN_ADDR(0, 3) /*!< Specify P03 Pin Data Input/Output */
|
||||
#define P04 GPIO_PIN_ADDR(0, 4) /*!< Specify P04 Pin Data Input/Output */
|
||||
#define P05 GPIO_PIN_ADDR(0, 5) /*!< Specify P05 Pin Data Input/Output */
|
||||
#define P06 GPIO_PIN_ADDR(0, 6) /*!< Specify P06 Pin Data Input/Output */
|
||||
#define P07 GPIO_PIN_ADDR(0, 7) /*!< Specify P07 Pin Data Input/Output */
|
||||
#define P10 GPIO_PIN_ADDR(1, 0) /*!< Specify P10 Pin Data Input/Output */
|
||||
#define P11 GPIO_PIN_ADDR(1, 1) /*!< Specify P11 Pin Data Input/Output */
|
||||
#define P12 GPIO_PIN_ADDR(1, 2) /*!< Specify P12 Pin Data Input/Output */
|
||||
#define P13 GPIO_PIN_ADDR(1, 3) /*!< Specify P13 Pin Data Input/Output */
|
||||
#define P14 GPIO_PIN_ADDR(1, 4) /*!< Specify P14 Pin Data Input/Output */
|
||||
#define P15 GPIO_PIN_ADDR(1, 5) /*!< Specify P15 Pin Data Input/Output */
|
||||
#define P16 GPIO_PIN_ADDR(1, 6) /*!< Specify P16 Pin Data Input/Output */
|
||||
#define P17 GPIO_PIN_ADDR(1, 7) /*!< Specify P17 Pin Data Input/Output */
|
||||
#define P20 GPIO_PIN_ADDR(2, 0) /*!< Specify P20 Pin Data Input/Output */
|
||||
#define P21 GPIO_PIN_ADDR(2, 1) /*!< Specify P21 Pin Data Input/Output */
|
||||
#define P22 GPIO_PIN_ADDR(2, 2) /*!< Specify P22 Pin Data Input/Output */
|
||||
#define P23 GPIO_PIN_ADDR(2, 3) /*!< Specify P23 Pin Data Input/Output */
|
||||
#define P24 GPIO_PIN_ADDR(2, 4) /*!< Specify P24 Pin Data Input/Output */
|
||||
#define P25 GPIO_PIN_ADDR(2, 5) /*!< Specify P25 Pin Data Input/Output */
|
||||
#define P26 GPIO_PIN_ADDR(2, 6) /*!< Specify P26 Pin Data Input/Output */
|
||||
#define P27 GPIO_PIN_ADDR(2, 7) /*!< Specify P27 Pin Data Input/Output */
|
||||
#define P30 GPIO_PIN_ADDR(3, 0) /*!< Specify P30 Pin Data Input/Output */
|
||||
#define P31 GPIO_PIN_ADDR(3, 1) /*!< Specify P31 Pin Data Input/Output */
|
||||
#define P32 GPIO_PIN_ADDR(3, 2) /*!< Specify P32 Pin Data Input/Output */
|
||||
#define P33 GPIO_PIN_ADDR(3, 3) /*!< Specify P33 Pin Data Input/Output */
|
||||
#define P34 GPIO_PIN_ADDR(3, 4) /*!< Specify P34 Pin Data Input/Output */
|
||||
#define P35 GPIO_PIN_ADDR(3, 5) /*!< Specify P35 Pin Data Input/Output */
|
||||
#define P36 GPIO_PIN_ADDR(3, 6) /*!< Specify P36 Pin Data Input/Output */
|
||||
#define P37 GPIO_PIN_ADDR(3, 7) /*!< Specify P37 Pin Data Input/Output */
|
||||
#define P40 GPIO_PIN_ADDR(4, 0) /*!< Specify P40 Pin Data Input/Output */
|
||||
#define P41 GPIO_PIN_ADDR(4, 1) /*!< Specify P41 Pin Data Input/Output */
|
||||
#define P42 GPIO_PIN_ADDR(4, 2) /*!< Specify P42 Pin Data Input/Output */
|
||||
#define P43 GPIO_PIN_ADDR(4, 3) /*!< Specify P43 Pin Data Input/Output */
|
||||
#define P44 GPIO_PIN_ADDR(4, 4) /*!< Specify P44 Pin Data Input/Output */
|
||||
#define P45 GPIO_PIN_ADDR(4, 5) /*!< Specify P45 Pin Data Input/Output */
|
||||
#define P46 GPIO_PIN_ADDR(4, 6) /*!< Specify P46 Pin Data Input/Output */
|
||||
#define P47 GPIO_PIN_ADDR(4, 7) /*!< Specify P47 Pin Data Input/Output */
|
||||
#define P50 GPIO_PIN_ADDR(5, 0) /*!< Specify P50 Pin Data Input/Output */
|
||||
#define P51 GPIO_PIN_ADDR(5, 1) /*!< Specify P51 Pin Data Input/Output */
|
||||
#define P52 GPIO_PIN_ADDR(5, 2) /*!< Specify P52 Pin Data Input/Output */
|
||||
#define P53 GPIO_PIN_ADDR(5, 3) /*!< Specify P53 Pin Data Input/Output */
|
||||
#define P54 GPIO_PIN_ADDR(5, 4) /*!< Specify P54 Pin Data Input/Output */
|
||||
#define P55 GPIO_PIN_ADDR(5, 5) /*!< Specify P55 Pin Data Input/Output */
|
||||
|
||||
/*@}*/ /* end of group Mini58_GPIO_EXPORTED_CONSTANTS */
|
||||
|
||||
/** @addtogroup Mini58_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Clear GPIO Pin Interrupt Flag
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Clear the interrupt status of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_CLR_INT_FLAG(gpio, u32PinMask) ((gpio)->INTSRC = u32PinMask)
|
||||
|
||||
/**
|
||||
* @brief Disable Pin De-bounce Function
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Disable the interrupt de-bounce function of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_DISABLE_DEBOUNCE(gpio, u32PinMask) ((gpio)->DBEN &= ~u32PinMask)
|
||||
|
||||
/**
|
||||
* @brief Enable Pin De-bounce Function
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Enable the interrupt de-bounce function of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_ENABLE_DEBOUNCE(gpio, u32PinMask) ((gpio)->DBEN |= u32PinMask)
|
||||
|
||||
/**
|
||||
* @brief Disable I/O Digital Input Path
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Disable I/O digital input path of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_DISABLE_DIGITAL_PATH(gpio, u32PinMask) ((gpio)->DINOFF |= (u32PinMask << 16))
|
||||
|
||||
/**
|
||||
* @brief Enable I/O Digital Input Path
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Enable I/O digital input path of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_ENABLE_DIGITAL_PATH(gpio, u32PinMask) ((gpio)->DINOFF &= ~(u32PinMask << 16))
|
||||
|
||||
/**
|
||||
* @brief Disable I/O DOUT mask
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Disable I/O DOUT mask of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_DISABLE_DOUT_MASK(gpio, u32PinMask) ((gpio)->DATMSK &= ~u32PinMask)
|
||||
|
||||
/**
|
||||
* @brief Enable I/O DOUT mask
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Enable I/O DOUT mask of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_ENABLE_DOUT_MASK(gpio, u32PinMask) ((gpio)->DATMSK |= u32PinMask)
|
||||
|
||||
/**
|
||||
* @brief Get GPIO Pin Interrupt Flag
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
|
||||
*
|
||||
* @retval 0 No interrupt at specified GPIO pin
|
||||
* @retval 1 The specified GPIO pin generate an interrupt
|
||||
*
|
||||
* @details Get the interrupt status of specified GPIO pin.
|
||||
*/
|
||||
#define GPIO_GET_INT_FLAG(gpio, u32PinMask) ((gpio)->INTSRC & u32PinMask)
|
||||
|
||||
/**
|
||||
* @brief Set De-bounce Sampling Cycle Time
|
||||
*
|
||||
* @param[in] clksrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_IRC10K.
|
||||
* @param[in] clksel The de-bounce sampling cycle selection. It could be \n
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_1, \ref GPIO_DBCTL_DBCLKSEL_2, \ref GPIO_DBCTL_DBCLKSEL_4, \ref GPIO_DBCTL_DBCLKSEL_8, \n
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_16, \ref GPIO_DBCTL_DBCLKSEL_32, \ref GPIO_DBCTL_DBCLKSEL_64, \ref GPIO_DBCTL_DBCLKSEL_128, \n
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_256, \ref GPIO_DBCTL_DBCLKSEL_512, \ref GPIO_DBCTL_DBCLKSEL_1024, \ref GPIO_DBCTL_DBCLKSEL_2048, \n
|
||||
* - \ref GPIO_DBCTL_DBCLKSEL_4096, \ref GPIO_DBCTL_DBCLKSEL_8192, \ref GPIO_DBCTL_DBCLKSEL_16384, \ref GPIO_DBCTL_DBCLKSEL_32768.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
|
||||
* Example: GPIO_SET_DEBOUNCE_TIME(GPIO_DBCTL_DBCLKSRC_IRC10K, GPIO_DBCTL_DBCLKSEL_4). \n
|
||||
* It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
|
||||
* Then the target de-bounce sampling cycle time is (2^4)*(1/(10*1000)) s = 16*0.0001 s = 1600 us,
|
||||
* and system will sampling interrupt input once per 1600 us.
|
||||
*/
|
||||
#define GPIO_SET_DEBOUNCE_TIME(clksrc, clksel) (GPIO->DBCTL = (GP_DBCTL_ICLKON_Msk | clksrc | clksel))
|
||||
|
||||
/**
|
||||
* @brief Get GPIO Port IN Data
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
*
|
||||
* @retval The specified port data
|
||||
*
|
||||
* @details Get the PIN register of specified GPIO port.
|
||||
*/
|
||||
#define GPIO_GET_IN_DATA(gpio) ((gpio)->PIN)
|
||||
|
||||
/**
|
||||
* @brief Set GPIO Port OUT Data
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] data GPIO port data.
|
||||
*
|
||||
* @retval None
|
||||
*
|
||||
* @details Set the Data into specified GPIO port.
|
||||
*/
|
||||
#define GPIO_SET_OUT_DATA(gpio, data) ((gpio)->DOUT = (data))
|
||||
|
||||
/**
|
||||
* @brief Toggle Specified GPIO pin
|
||||
*
|
||||
* @param[in] u32Pin Pxy
|
||||
*
|
||||
* @retval None
|
||||
*
|
||||
* @details Toggle the specified GPIO pint.
|
||||
*/
|
||||
#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
|
||||
|
||||
/**
|
||||
* @brief Enable External GPIO interrupt 0
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32Pin The pin of specified GPIO port.
|
||||
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
|
||||
* - \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
*/
|
||||
#define GPIO_EnableEINT0 GPIO_EnableInt
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable External GPIO interrupt 0
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
*/
|
||||
#define GPIO_DisableEINT0 GPIO_DisableInt
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable External GPIO interrupt 1
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32Pin The pin of specified GPIO port.
|
||||
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
|
||||
* - \ref GPIO_INT_RISING, \ref GPIO_INT_FALLING, \ref GPIO_INT_BOTH_EDGE, \ref GPIO_INT_HIGH, \ref GPIO_INT_LOW.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
*/
|
||||
#define GPIO_EnableEINT1 GPIO_EnableInt
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable External GPIO interrupt 1
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
*/
|
||||
#define GPIO_DisableEINT1 GPIO_DisableInt
|
||||
|
||||
|
||||
void GPIO_SetMode(GPIO_T *gpio, uint32_t u32PinMask, uint32_t u32Mode);
|
||||
void GPIO_EnableInt(GPIO_T *gpio, uint32_t u32Pin, uint32_t u32IntAttribs);
|
||||
void GPIO_DisableInt(GPIO_T *gpio, uint32_t u32Pin);
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_GPIO_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_GPIO_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__GPIO_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,212 @@
|
||||
/**************************************************************************//**
|
||||
* @file i2c.h
|
||||
* @version V1.00
|
||||
* $Revision: 7 $
|
||||
* $Date: 15/12/31 1:36p $
|
||||
* @brief Mini58 series I2C driver header file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __I2C_H__
|
||||
#define __I2C_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_I2C_Driver I2C Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Mini58_I2C_EXPORTED_CONSTANTS I2C Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
#define I2C_STA 0x20 /*!< I2C START */
|
||||
#define I2C_STO 0x10 /*!< I2C STOP */
|
||||
#define I2C_SI 0x08 /*!< I2C SI */
|
||||
#define I2C_AA 0x04 /*!< I2C ACK */
|
||||
|
||||
/*@}*/ /* end of group Mini58_I2C_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup Mini58_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This macro sets the I2C control register at one time.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @param[in] u8Ctrl is the register value of I2C control register.
|
||||
* @return none
|
||||
*/
|
||||
#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ( (i2c)->CTL = ((i2c)->CTL & ~0x3c) | u8Ctrl )
|
||||
|
||||
/**
|
||||
* @brief This macro only set START bit to the control register of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
#define I2C_START(i2c) ( (i2c)->CTL = ((i2c)->CTL & ~I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk )
|
||||
|
||||
/**
|
||||
* @brief This macro only set STOP bit to the control register of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
#define I2C_STOP(i2c) \
|
||||
do { \
|
||||
(i2c)->CTL |= (I2C_CTL_SI_Msk | I2C_CTL_STO_Msk); \
|
||||
while((i2c)->CTL & I2C_CTL_STO_Msk); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @brief This macro will return when I2C module is ready.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL & I2C_CTL_SI_Msk))
|
||||
|
||||
/**
|
||||
* @brief This macro disables the FIFO function.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
#define I2C_DISABLE_FIFO(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_TWOLVFIFO_Msk )
|
||||
|
||||
/**
|
||||
* @brief This macro enables the FIFO function.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
#define I2C_ENABLE_FIFO(i2c) ( (i2c)->CTL1 |= I2C_CTL1_TWOLVFIFO_Msk )
|
||||
|
||||
/**
|
||||
* @brief This macro disables clock stretch function.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
#define I2C_DISABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_NSTRETCH_Msk )
|
||||
|
||||
/**
|
||||
* @brief This macro enables clock stretch function.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
#define I2C_ENABLE_CLOCK_STRETCH(i2c) ( (i2c)->CTL1 |= I2C_CTL1_NSTRETCH_Msk )
|
||||
|
||||
/**
|
||||
* @brief This macro disables over-run interrupt.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
#define I2C_DISABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_OVIEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief This macro enables over-run interrupt.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
#define I2C_ENABLE_OVERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_OVIEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief This macro enables under-run interrupt.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
#define I2C_ENABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 |= I2C_CTL1_URIEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief This macro disables under-run interrupt.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
#define I2C_DISABLE_UNDERRUN_INT(i2c) ( (i2c)->CTL1 &= ~I2C_CTL1_URIEN_Msk )
|
||||
|
||||
/**
|
||||
* @brief This macro returns the data stored in data register of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return Data.
|
||||
*/
|
||||
#define I2C_GET_DATA(i2c) ( (i2c)->DAT )
|
||||
|
||||
/**
|
||||
* @brief This macro writes the data to data register of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @param[in] u8Data is the data which will be write to data register of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
#define I2C_SET_DATA(i2c, u8Data) ( (i2c)->DAT = u8Data )
|
||||
|
||||
/**
|
||||
* @brief This macro returns the status of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return Status.
|
||||
*/
|
||||
#define I2C_GET_STATUS(i2c) ( (i2c)->STATUS )
|
||||
|
||||
/**
|
||||
* @brief This macro returns timeout flag.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return Status.
|
||||
* @retval 0 Flag is not set.
|
||||
* @retval 1 Flag is set.
|
||||
*/
|
||||
#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief This macro returns wakeup flag.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return Status.
|
||||
* @retval 0 Flag is not set.
|
||||
* @retval 1 Flag is set.
|
||||
*/
|
||||
#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->STATUS1 & I2C_STATUS1_WKIF_Msk) == I2C_STATUS1_WKIF_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief This macro clears wakeup flag.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
#define I2C_CLEAR_WAKEUP_FLAG(i2c) ( (i2c)->STATUS1 = I2C_STATUS1_WKIF_Msk )
|
||||
|
||||
uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
|
||||
void I2C_Close(I2C_T *i2c);
|
||||
void I2C_ClearTimeoutFlag(I2C_T *i2c);
|
||||
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
|
||||
void I2C_DisableInt(I2C_T *i2c);
|
||||
void I2C_EnableInt(I2C_T *i2c);
|
||||
uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
|
||||
uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
|
||||
uint32_t I2C_GetIntFlag(I2C_T *i2c);
|
||||
uint32_t I2C_GetStatus(I2C_T *i2c);
|
||||
uint32_t I2C_GetData(I2C_T *i2c);
|
||||
void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
|
||||
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
|
||||
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
|
||||
void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
|
||||
void I2C_DisableTimeout(I2C_T *i2c);
|
||||
void I2C_EnableWakeup(I2C_T *i2c);
|
||||
void I2C_DisableWakeup(I2C_T *i2c);
|
||||
|
||||
/*@}*/ /* end of group Mini58_I2C_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_I2C_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__I2C_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,282 @@
|
||||
/**************************************************************************//**
|
||||
* @file pwm.h
|
||||
* @version V1.00
|
||||
* $Revision: 6 $
|
||||
* $Date: 15/06/05 1:41p $
|
||||
* @brief Mini58 series PWM driver header file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __PWM_H__
|
||||
#define __PWM_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_PWM_Driver PWM Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_PWM_EXPORTED_CONSTANTS PWM Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define PWM_CHANNEL_NUM (6) /*!< PWM channel number */
|
||||
#define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 */
|
||||
#define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 */
|
||||
#define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 */
|
||||
#define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 */
|
||||
#define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 */
|
||||
#define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type */
|
||||
#define PWM_CENTER_ALIGNED (PWM_CTL_CNTTYPE_Msk) /*!< PWM working in center aligned type */
|
||||
#define PWM_TRIGGER_ADC_CNTR_IS_0 PWM_ADCTCTL0_ZPTRGEN0_Msk /*!< PWM trigger ADC while counter matches 0 */
|
||||
#define PWM_TRIGGER_ADC_CNTR_IS_CMR_D PWM_ADCTCTL0_CDTRGEN0_Msk /*!< PWM trigger ADC while counter matches CMR during down count */
|
||||
#define PWM_TRIGGER_ADC_CNTR_IS_CNR PWM_ADCTCTL0_CPTRGEN0_Msk /*!< PWM trigger ADC while counter matches CNR */
|
||||
#define PWM_TRIGGER_ADC_CNTR_IS_CMR_U PWM_ADCTCTL0_CUTRGEN0_Msk /*!< PWM trigger ADC while counter matches CMR during up count */
|
||||
#define PWM_FB0_EINT0 (PWM_BRKCTL_BRK0EN_Msk) /*!< External interrupt 0 as fault brake 0 source */
|
||||
#define PWM_FB0_ACMP1 (PWM_BRKCTL_BRK0EN_Msk | PWM_BRKCTL_BRK1SEL_Msk) /*!< Comparator 1 as fault brake 0 source */
|
||||
#define PWM_FB1_EINT1 (PWM_BRKCTL_BRK1EN_Msk) /*!< External interrupt 1 as fault brake 1 source */
|
||||
#define PWM_FB1_ACMP0 (PWM_BRKCTL_BRK1EN_Msk | PWM_BRKCTL_BRK0SEL_Msk) /*!< Comparator 0 as fault brake 1 source */
|
||||
#define PWM_PERIOD_INT_UNDERFLOW (0) /*!< PWM period interrupt trigger if counter underflow */
|
||||
#define PWM_PERIOD_INT_MATCH_CNR (PWM_INTEN_PINTTYPE_Msk) /*!< PWM period interrupt trigger if counter match CNR */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* PWM Group channel number constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define PWM_CH0 0x0 /*!< PWM channel 0 */
|
||||
#define PWM_CH1 0x1 /*!< PWM channel 1 */
|
||||
#define PWM_CH2 0x2 /*!< PWM channel 2 */
|
||||
#define PWM_CH3 0x3 /*!< PWM channel 3 */
|
||||
#define PWM_CH4 0x4 /*!< PWM channel 4 */
|
||||
#define PWM_CH5 0x5 /*!< PWM channel 5 */
|
||||
|
||||
/*@}*/ /* end of group Mini58_PWM_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup Mini58_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This macro enable complementary mode
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (PWM->CTL & ~PWM_CTL_MODE_Msk) |(1UL << PWM_CTL_MODE_Pos))
|
||||
|
||||
/**
|
||||
* @brief This macro disable complementary mode, and enable independent mode.
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro enable group mode
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL |= PWM_CTL_GROUPEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro disable group mode
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_GROUPEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro enable synchronous mode
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_ENABLE_SYNC_MODE(pwm) (PWM->CTL = ((pwm)->CTL & ~PWM_CTL_MODE_Msk) |(2UL << PWM_CTL_MODE_Pos))
|
||||
|
||||
/**
|
||||
* @brief This macro disable synchronous mode, and enable independent mode.
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL &= ~PWM_CTL_MODE_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro enable output inverter of specified channel(s)
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) \
|
||||
do{ \
|
||||
int i;\
|
||||
(pwm)->CTL &= ~(PWM_CTL_PINV0_Msk|PWM_CTL_PINV1_Msk|PWM_CTL_PINV2_Msk|PWM_CTL_PINV3_Msk|PWM_CTL_PINV4_Msk|PWM_CTL_PINV5_Msk);\
|
||||
for(i = 0; i < 6; i++) { \
|
||||
if((u32ChannelMask) & (1 << i)) \
|
||||
(pwm)->CTL |= (1 << (PWM_CTL_PINV0_Pos + (i * 4))); \
|
||||
} \
|
||||
}while(0)
|
||||
|
||||
/**
|
||||
* @brief This macro set the prescaler of the selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF
|
||||
* @return None
|
||||
* @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed,
|
||||
* channel 1 will also be affected.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \
|
||||
((pwm)->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8)))
|
||||
|
||||
/**
|
||||
* @brief This macro set the divider of the selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Divider Clock divider of specified channel. Valid values are
|
||||
* - \ref PWM_CLK_DIV_1
|
||||
* - \ref PWM_CLK_DIV_2
|
||||
* - \ref PWM_CLK_DIV_4
|
||||
* - \ref PWM_CLK_DIV_8
|
||||
* - \ref PWM_CLK_DIV_16
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \
|
||||
((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4)))
|
||||
|
||||
/**
|
||||
* @brief This macro set the duty of the selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
|
||||
* @return None
|
||||
* @note This new setting will take effect on next PWM period
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4)))= (u32CMR))
|
||||
|
||||
/**
|
||||
* @brief This macro set the period of the selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
|
||||
* @return None
|
||||
* @note This new setting will take effect on next PWM period
|
||||
* @note PWM counter will stop if period length set to 0
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) (*((__IO uint32_t *) ((((uint32_t)&((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = (u32CNR))
|
||||
|
||||
/**
|
||||
* @brief This macro set the duty of the selected channel for PWM asymmetric Mode
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32CMRD Down counter in Asymmetric Mode. Valid values are between 0~0xFFFF
|
||||
* @return None
|
||||
* @note This new setting will take effect on next PWM period
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_CMRD(pwm, u32ChannelNum, u32CMRD) (*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + (u32ChannelNum) * 4)))= (u32CMRD << 16))
|
||||
|
||||
/**
|
||||
* @brief This macro set the PWM aligned type
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelMask This parameter is not used
|
||||
* @param[in] u32AlignedType PWM aligned type, valid values are:
|
||||
* - \ref PWM_EDGE_ALIGNED
|
||||
* - \ref PWM_CENTER_ALIGNED
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
|
||||
((pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk) | (u32AlignedType))
|
||||
|
||||
/**
|
||||
* @brief This macro enables PWM asymmetric mode
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_ENABLE_ASYMMETRIC_MODE(pwm) ((pwm)->CTL |= PWM_CTL_ASYMEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro enables PWM Precise Center-Aligned Type
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define PWM_ENABLE_PCAEN(pwm) (PWM->PCACTL |= PWM_PCACTL_PCAEN_Msk)
|
||||
|
||||
uint32_t PWM_ConfigOutputChannel(PWM_T *pwm,
|
||||
uint32_t u32ChannelNum,
|
||||
uint32_t u32Frequency,
|
||||
uint32_t u32DutyCycle);
|
||||
void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
||||
void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
||||
uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
||||
void PWM_EnableFaultBrake(PWM_T *pwm,
|
||||
uint32_t u32ChannelMask,
|
||||
uint32_t u32LevelMask,
|
||||
uint32_t u32BrakeSource);
|
||||
void PWM_ClearFaultBrakeFlag(PWM_T *pwm, uint32_t u32BrakeSource);
|
||||
void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||
void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
|
||||
void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
|
||||
void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
|
||||
void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
|
||||
void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
|
||||
void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
|
||||
void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
|
||||
uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
|
||||
|
||||
void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
|
||||
void PWM_EnableCenterInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
|
||||
void PWM_DisableCenterInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_ClearCenterIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
uint32_t PWM_GetCenterIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
|
||||
void PWM_EnableRiseInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_DisableRiseInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
void PWM_ClearRiseIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
uint32_t PWM_GetRiseIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||
|
||||
/*@}*/ /* end of group Mini58_PWM_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_PWM_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__PWM_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,258 @@
|
||||
/**************************************************************************//**
|
||||
* @file spi.h
|
||||
* @version V1.00
|
||||
* $Revision: 3 $
|
||||
* $Date: 15/04/17 11:45a $
|
||||
* @brief Mini58 series SPI driver header file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __SPI_H__
|
||||
#define __SPI_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_SPI_Driver SPI Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_SPI_EXPORTED_CONSTANTS SPI Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKP=0; RX_NEG=0; TX_NEG=1 */
|
||||
#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKP=0; RX_NEG=1; TX_NEG=0 */
|
||||
#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKP=1; RX_NEG=1; TX_NEG=0 */
|
||||
#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKP=1; RX_NEG=0; TX_NEG=1 */
|
||||
|
||||
#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */
|
||||
#define SPI_MASTER (0x0) /*!< Set as master */
|
||||
|
||||
#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS0 */
|
||||
#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */
|
||||
#define SPI_SS_ACTIVE_LOW (0x0) /*!< SS active low */
|
||||
|
||||
#define SPI_IE_MASK (0x01) /*!< Interrupt enable mask */
|
||||
#define SPI_SSTA_INTEN_MASK (0x04) /*!< Slave 3-Wire mode start interrupt enable mask */
|
||||
#define SPI_FIFO_TX_INTEN_MASK (0x08) /*!< FIFO TX interrupt mask */
|
||||
#define SPI_FIFO_RX_INTEN_MASK (0x10) /*!< FIFO RX interrupt mask */
|
||||
#define SPI_FIFO_RXOV_INTEN_MASK (0x20) /*!< FIFO RX overrun interrupt mask */
|
||||
#define SPI_FIFO_TIMEOUT_INTEN_MASK (0x40) /*!< FIFO timeout interrupt mask */
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_SPI_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup Mini58_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Abort the current transfer in slave 3-wire mode.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
#define SPI_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLVABT_Msk )
|
||||
|
||||
/**
|
||||
* @brief Clear the slave 3-wire mode start interrupt flag.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
#define SPI_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_SLVSTIF_Msk )
|
||||
|
||||
/**
|
||||
* @brief Clear the unit transfer interrupt flag.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable slave 3-wire mode.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
#define SPI_DISABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL &= ~SPI_SLVCTL_SLV3WIRE_Msk )
|
||||
|
||||
/**
|
||||
* @brief Enable slave 3-wire mode.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
#define SPI_ENABLE_3WIRE_MODE(spi) ( (spi)->SLVCTL |= SPI_SLVCTL_SLV3WIRE_Msk )
|
||||
|
||||
/**
|
||||
* @brief Get the count of available data in RX FIFO.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return The count of available data in RX FIFO.
|
||||
*/
|
||||
#define SPI_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos) & 0xf )
|
||||
|
||||
/**
|
||||
* @brief Get the Rx FIFO empty flag.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return Rx FIFO flag
|
||||
* @retval 0 Rx FIFO is not empty
|
||||
* @retval 1 Rx FIFO is empty
|
||||
*/
|
||||
#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) == SPI_STATUS_RXEMPTY_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief Get the Tx FIFO empty flag.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return Tx FIFO flag
|
||||
* @retval 0 Tx FIFO is not empty
|
||||
* @retval 1 Tx FIFO is empty
|
||||
*/
|
||||
#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) == SPI_STATUS_TXEMPTY_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief Get the Tx FIFO full flag.
|
||||
* @param spi is the base address of SPI module.
|
||||
* @return Tx FIFO flag
|
||||
* @retval 0 Tx FIFO is not full
|
||||
* @retval 1 Tx FIFO is full
|
||||
*/
|
||||
#define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) == SPI_STATUS_TXFULL_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief Get the datum read from Rx FIFO.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return Data in Rx buffer
|
||||
*/
|
||||
#define SPI_READ_RX(spi) ( (spi)->RX )
|
||||
|
||||
/**
|
||||
* @brief Write datum to TX register.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @param[in] u32TxData is the datum which user attempt to transfer through SPI bus.
|
||||
* @return none
|
||||
*/
|
||||
#define SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = u32TxData )
|
||||
|
||||
/**
|
||||
* @brief Disable automatic slave select function and set SPI_SS pin to high state.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
static __INLINE void SPI_SET_SS_HIGH(SPI_T *spi)
|
||||
{
|
||||
spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
|
||||
spi->SSCTL |= (SPI_SSCTL_LTF_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable automatic slave select function and set SPI_SS pin to low state.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
static __INLINE void SPI_SET_SS_LOW(SPI_T *spi)
|
||||
{
|
||||
spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
|
||||
spi->SSCTL |= SPI_SSCTL_LTF_Msk;
|
||||
spi->SSCTL &= ~SPI_SSCTL_SSACTPOL_Msk;
|
||||
spi->SSCTL |= SPI_SSCTL_SS_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable byte reorder function.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
#define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk )
|
||||
|
||||
/**
|
||||
* @brief Disable byte reorder function.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
#define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk )
|
||||
|
||||
/**
|
||||
* @brief Set the length of suspend interval.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @param[in] u32SuspCycle decides the length of suspend interval.
|
||||
* @return none
|
||||
*/
|
||||
#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | (u32SuspCycle << SPI_CTL_SUSPITV_Pos) )
|
||||
|
||||
/**
|
||||
* @brief Set the SPI transfer sequence with LSB first.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
#define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk )
|
||||
|
||||
/**
|
||||
* @brief Set the SPI transfer sequence with MSB first.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
#define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk )
|
||||
|
||||
/**
|
||||
* @brief Set the data width of a SPI transaction.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @param[in] u32Width is the bit width of transfer data.
|
||||
* @return none
|
||||
*/
|
||||
static __INLINE void SPI_SET_DATA_WIDTH(SPI_T *spi, uint32_t u32Width)
|
||||
{
|
||||
if(u32Width == 32)
|
||||
u32Width = 0;
|
||||
|
||||
spi->CTL = (spi->CTL & ~SPI_CTL_DWIDTH_Msk) | (u32Width << SPI_CTL_DWIDTH_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the SPI busy state.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return SPI busy status
|
||||
* @retval 0 SPI module is not busy
|
||||
* @retval 1 SPI module is busy
|
||||
*/
|
||||
#define SPI_IS_BUSY(spi) ( ((spi)->CTL & SPI_CTL_SPIEN_Msk) == SPI_CTL_SPIEN_Msk ? 1:0 )
|
||||
|
||||
/**
|
||||
* @brief Set the GO_BUSY bit to trigger SPI transfer.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
#define SPI_TRIGGER(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk )
|
||||
|
||||
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
|
||||
void SPI_Close(SPI_T *spi);
|
||||
void SPI_ClearRxFIFO(SPI_T *spi);
|
||||
void SPI_ClearTxFIFO(SPI_T *spi);
|
||||
void SPI_DisableAutoSS(SPI_T *spi);
|
||||
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
|
||||
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
|
||||
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
|
||||
void SPI_DisableFIFO(SPI_T *spi);
|
||||
uint32_t SPI_GetBusClock(SPI_T *spi);
|
||||
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
|
||||
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
|
||||
|
||||
/*@}*/ /* end of group Mini58_SPI_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_SPI_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__SPI_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,462 @@
|
||||
/**************************************************************************//**
|
||||
* @file sys.h
|
||||
* @version V1.00
|
||||
* $Revision: 15 $
|
||||
* $Date: 15/06/04 5:18p $
|
||||
* @brief Mini58 series SYS driver header file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __SYS_H__
|
||||
#define __SYS_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_SYS_Driver SYS Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_SYS_EXPORTED_CONSTANTS SYS Exported Constants
|
||||
@{
|
||||
*/
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Module Reset Control Resister constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define ADC_RST ((0x4<<24) | SYS_IPRST1_ADCRST_Pos ) /*!< ADC reset is one of the SYS_ResetModule parameter */
|
||||
#define ACMP_RST ((0x4<<24) | SYS_IPRST1_ACMPRST_Pos ) /*!< ACMP reset is one of the SYS_ResetModule parameter */
|
||||
#define PWM0_RST ((0x4<<24) | SYS_IPRST1_PWM0RST_Pos ) /*!< PWM reset is one of the SYS_ResetModule parameter */
|
||||
#define UART0_RST ((0x4<<24) | SYS_IPRST1_UART0RST_Pos ) /*!< UART0 reset is one of the SYS_ResetModule parameter */
|
||||
#define UART1_RST ((0x4<<24) | SYS_IPRST1_UART1RST_Pos ) /*!< UART1 reset is one of the SYS_ResetModule parameter */
|
||||
#define SPI0_RST ((0x4<<24) | SYS_IPRST1_SPI0RST_Pos ) /*!< SPI reset is one of the SYS_ResetModule parameter */
|
||||
#define I2C0_RST ((0x4<<24) | SYS_IPRST1_I2C0RST_Pos ) /*!< I2C0 reset is one of the SYS_ResetModule parameter */
|
||||
#define I2C1_RST ((0x4<<24) | SYS_IPRST1_I2C1RST_Pos ) /*!< I2C1 reset is one of the SYS_ResetModule parameter */
|
||||
#define TMR1_RST ((0x4<<24) | SYS_IPRST1_TMR1RST_Pos ) /*!< TMR1 reset is one of the SYS_ResetModule parameter */
|
||||
#define TMR0_RST ((0x4<<24) | SYS_IPRST1_TMR0RST_Pos ) /*!< TMR0 reset is one of the SYS_ResetModule parameter */
|
||||
#define GPIO_RST ((0x4<<24) | SYS_IPRST1_GPIORST_Pos ) /*!< GPIO reset is one of the SYS_ResetModule parameter */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Brown Out Detector Threshold Voltage Selection constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define SYS_BODCTL_BOD_RST_EN (1UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Reset Enable */
|
||||
#define SYS_BODCTL_BOD_INTERRUPT_EN (0UL<<SYS_BODCTL_BODRSTEN_Pos) /*!< Brown-out Interrupt Enable */
|
||||
#define SYS_BODCTL_BODVL_4_4V (3UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 4.4V */
|
||||
#define SYS_BODCTL_BODVL_3_7V (2UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 3.7V */
|
||||
#define SYS_BODCTL_BODVL_2_7V (1UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.7V */
|
||||
#define SYS_BODCTL_BODVL_2_2V (0UL<<SYS_BODCTL_BODVL_Pos) /*!< Setting Brown Out Detector Threshold Voltage as 2.2V */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Multi-Function constant definitions. */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define SYS_MFP_TYPE_Msk(bit) (1UL << ((bit) +16)) /*!< TYPE mask for Multiple Function Port */
|
||||
#define SYS_MFP_ALT_Msk(bit) (1UL << ((bit) + 8)) /*!< ALT mask for Multiple Function Port */
|
||||
#define SYS_MFP_MFP_Msk(bit) (1UL << ((bit) )) /*!< MFP mask for Multiple Function Port */
|
||||
|
||||
#define SYS_MFP_P00_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P00_UART0_nCTS 0x00000100UL /*!< Clear to Send input pin for UART0. */
|
||||
#define SYS_MFP_P00_UART0_TXD 0x00000101UL /*!< Data transmitter output pin for UART0. */
|
||||
#define SYS_MFP_P00_Msk 0x00000101UL /*!< P0_MFP pin 0 mask */
|
||||
|
||||
#define SYS_MFP_P01_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P01_SPI0_SS 0x00000002UL /*!< 1st SPI0 slave select pin. */
|
||||
#define SYS_MFP_P01_UART0_nRTS 0x00000200UL /*!< Request to Send output pin for UART0. */
|
||||
#define SYS_MFP_P01_UART0_RXD 0x00000202UL /*!< Data receiver input pin for UART0. */
|
||||
#define SYS_MFP_P01_Msk 0x00000202UL /*!< P0_MFP pin 1 mask */
|
||||
|
||||
#define SYS_MFP_P04_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P04_PWM0_CH5 0x00001010UL /*!< PWM0 channel5 output/capture input. */
|
||||
#define SYS_MFP_P04_SPI0_SS 0x00001000UL /*!< 1st SPI0 slave select pin. */
|
||||
#define SYS_MFP_P04_Msk 0x00001010UL /*!< P0_MFP pin 4 mask */
|
||||
|
||||
#define SYS_MFP_P05_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P05_PWM0_CH4 0x00002020UL /*!< PWM0 channel4 output/capture input. */
|
||||
#define SYS_MFP_P05_SPI0_MOSI 0x00002000UL /*!< 1st SPI0 MOSI (Master Out, Slave In) pin. */
|
||||
#define SYS_MFP_P05_Msk 0x00002020UL /*!< P0_MFP pin 5 mask */
|
||||
|
||||
#define SYS_MFP_P06_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P06_PWM0_CH1 0x00004040UL /*!< PWM0 channel1 output/capture input. */
|
||||
#define SYS_MFP_P06_SPI0_MISO 0x00004000UL /*!< 1st SPI0 MISO (Master In, Slave Out) pin. */
|
||||
#define SYS_MFP_P06_Msk 0x00004040UL /*!< P0_MFP pin 6 mask */
|
||||
|
||||
#define SYS_MFP_P07_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P07_PWM0_CH0 0x00008080UL /*!< PWM0 channel0 output/capture input. */
|
||||
#define SYS_MFP_P07_SPI0_CLK 0x00008000UL /*!< SPI0 serial clock pin. */
|
||||
#define SYS_MFP_P07_Msk 0x00008080UL /*!< P0_MFP pin 7 mask */
|
||||
|
||||
#define SYS_MFP_P10_ACMP0_P1 0x00000101UL /*!< Analog comparator0 positive input pin. */
|
||||
#define SYS_MFP_P10_ADC_CH1 0x00000001UL /*!< ADC channel1 analog input. */
|
||||
#define SYS_MFP_P10_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P10_Msk 0x00000101UL /*!< P1_MFP pin 0 mask */
|
||||
|
||||
#define SYS_MFP_P12_ACMP0_P2 0x00000404UL /*!< Analog comparator0 positive input pin. */
|
||||
#define SYS_MFP_P12_ADC_CH2 0x00000004UL /*!< ADC channel2 analog input. */
|
||||
#define SYS_MFP_P12_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P12_UART0_RXD 0x00000400UL /*!< Data receiver input pin for UART0. */
|
||||
#define SYS_MFP_P12_PWM0_CH0 0x04000000UL /*!< PWM0 channel0 output/capture input. */
|
||||
#define SYS_MFP_P12_Msk 0x04000404UL /*!< P1_MFP pin 2 mask */
|
||||
|
||||
#define SYS_MFP_P13_ACMP0_P3 0x00000808UL /*!< Analog comparator0 positive input pin. */
|
||||
#define SYS_MFP_P13_ADC_CH3 0x00000008UL /*!< ADC channel3 analog input. */
|
||||
#define SYS_MFP_P13_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P13_UART0_TXD 0x00000800UL /*!< Data transmitter output pin for UART0. */
|
||||
#define SYS_MFP_P13_PWM0_CH1 0x08000000UL /*!< PWM0 channel1 output/capture input. */
|
||||
#define SYS_MFP_P13_Msk 0x08000808UL /*!< P1_MFP pin 3 mask */
|
||||
|
||||
#define SYS_MFP_P14_ACMP0_N 0x00001010UL /*!< Analog comparator0 negative input pin. */
|
||||
#define SYS_MFP_P14_ADC_CH4 0x00000010UL /*!< ADC channel4 analog input. */
|
||||
#define SYS_MFP_P14_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P14_UART1_RXD 0x00001000UL /*!< Data receiver input pin for UART1. */
|
||||
#define SYS_MFP_P14_PWM0_CH4 0x10000000UL /*!< PWM0 channel4 output/capture input. */
|
||||
#define SYS_MFP_P14_Msk 0x10001010UL /*!< P1_MFP pin 4 mask */
|
||||
|
||||
#define SYS_MFP_P15_ACMP0_P0 0x00002020UL /*!< Analog comparator0 positive input pin. */
|
||||
#define SYS_MFP_P15_ADC_CH5 0x00000020UL /*!< ADC channel5 analog input. */
|
||||
#define SYS_MFP_P15_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P15_UART1_TXD 0x00002000UL /*!< Data transmitter output pin for UART1. */
|
||||
#define SYS_MFP_P15_Msk 0x00002020UL /*!< P1_MFP pin 5 mask */
|
||||
|
||||
#define SYS_MFP_P22_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P22_I2C1_SCL 0x00000404UL /*!< I2C1 clock pin. */
|
||||
#define SYS_MFP_P22_PWM0_CH0 0x00000400UL /*!< PWM0 channel0 output/capture input. */
|
||||
#define SYS_MFP_P22_Msk 0x00000404UL /*!< P2_MFP pin 2 mask */
|
||||
|
||||
#define SYS_MFP_P23_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P23_I2C1_SDA 0x00000808UL /*!< I2C1 data input/output pin. */
|
||||
#define SYS_MFP_P23_PWM0_CH1 0x00000800UL /*!< PWM0 channel1 output/capture input. */
|
||||
#define SYS_MFP_P23_Msk 0x00000808UL /*!< P2_MFP pin 3 mask */
|
||||
|
||||
#define SYS_MFP_P24_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P24_PWM0_CH2 0x00001000UL /*!< PWM0 channel2 output/capture input. */
|
||||
#define SYS_MFP_P24_UART1_RXD 0x00000010UL /*!< Data receiver input pin for UART1. */
|
||||
#define SYS_MFP_P24_Msk 0x00001010UL /*!< P2_MFP pin 4 mask */
|
||||
|
||||
#define SYS_MFP_P25_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P25_PWM0_CH3 0x00002000UL /*!< PWM0 channel3 output/capture input. */
|
||||
#define SYS_MFP_P25_UART1_TXD 0x00000020UL /*!< Data transmitter output pin for UART1. */
|
||||
#define SYS_MFP_P25_Msk 0x00002020UL /*!< P2_MFP pin 5 mask */
|
||||
|
||||
#define SYS_MFP_P26_ACMP1_O 0x00004040UL /*!< Analog ccomparator1 output. */
|
||||
#define SYS_MFP_P26_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P26_PWM0_CH4 0x00004000UL /*!< PWM0 channel4 output/capture input. */
|
||||
#define SYS_MFP_P26_Msk 0x00004040UL /*!< P2_MFP pin 6 mask */
|
||||
|
||||
#define SYS_MFP_P30_ACMP1_N 0x00000100UL /*!< Analog comparator1 negative input pin. */
|
||||
#define SYS_MFP_P30_ADC_CH6 0x00000101UL /*!< ADC channel6 analog input. */
|
||||
#define SYS_MFP_P30_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P30_Msk 0x00000101UL /*!< P3_MFP pin 0 mask */
|
||||
|
||||
#define SYS_MFP_P31_ACMP1_P0 0x00000200UL /*!< Analog comparator1 positive input pin. */
|
||||
#define SYS_MFP_P31_ADC_CH7 0x00000202UL /*!< ADC channel7 analog input. */
|
||||
#define SYS_MFP_P31_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P31_Msk 0x00000202UL /*!< P3_MFP pin 1 mask */
|
||||
|
||||
#define SYS_MFP_P32_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P32_INT0 0x00000004UL /*!< External interrupt0 input pin. */
|
||||
#define SYS_MFP_P32_STADC 0x00000404UL /*!< ADC external trigger input. */
|
||||
#define SYS_MFP_P32_TM0_EXT 0x00000400UL /*!< Timer0 external capture input. */
|
||||
#define SYS_MFP_P32_ACMP1_P1 0x04000000UL /*!< Analog comparator1 positive input pin. */
|
||||
#define SYS_MFP_P32_Msk 0x04000404UL /*!< P3_MFP pin 2 mask */
|
||||
|
||||
#define SYS_MFP_P34_ACMP1_P2 0x00001010UL /*!< Analog comparator1 positive input pin. */
|
||||
#define SYS_MFP_P34_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P34_I2C0_SDA 0x00001000UL /*!< I2C0 data input/output pin. */
|
||||
#define SYS_MFP_P34_TM0_CNT_OUT 0x00000010UL /*!< Timer0 event counter input/toggle output. */
|
||||
#define SYS_MFP_P34_Msk 0x00001010UL /*!< P3_MFP pin 4 mask */
|
||||
|
||||
#define SYS_MFP_P35_ACMP1_P3 0x00002020UL /*!< Analog comparator1 positive input pin. */
|
||||
#define SYS_MFP_P35_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P35_I2C0_SCL 0x00002000UL /*!< I2C0 clock pin. */
|
||||
#define SYS_MFP_P35_TM1_CNT_OUT 0x00000020UL /*!< Timer1 event counter input/toggle output. */
|
||||
#define SYS_MFP_P35_Msk 0x00002020UL /*!< P3_MFP pin 5 mask */
|
||||
|
||||
#define SYS_MFP_P36_ACMP0_O 0x00004040UL /*!< Analog ccomparator0 output. */
|
||||
#define SYS_MFP_P36_CLKO 0x00004000UL /*!< Clock output. */
|
||||
#define SYS_MFP_P36_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P36_TM1_EXT 0x00000040UL /*!< Timer1 external capture input. */
|
||||
#define SYS_MFP_P36_Msk 0x00004040UL /*!< P3_MFP pin 6 mask */
|
||||
|
||||
#define SYS_MFP_P46_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P46_ICE_CLK 0x00000040UL /*!< Serial wired debugger clock pin. */
|
||||
#define SYS_MFP_P46_UART1_RXD 0x00004000UL /*!< Data receiver input pin for UART1. */
|
||||
#define SYS_MFP_P46_Msk 0x00004040UL /*!< P4_MFP pin 6 mask */
|
||||
|
||||
#define SYS_MFP_P47_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P47_ICE_DAT 0x00000080UL /*!< Serial wired debugger data pin. */
|
||||
#define SYS_MFP_P47_UART1_TXD 0x00008000UL /*!< Data transmitter output pin for UART1. */
|
||||
#define SYS_MFP_P47_Msk 0x00008080UL /*!< P4_MFP pin 7 mask */
|
||||
|
||||
#define SYS_MFP_P50_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P50_I2C1_SDA 0x00000100UL /*!< I2C1 data input/output pin. */
|
||||
#define SYS_MFP_P50_UART0_TXD 0x00000101UL /*!< Data transmitter output pin for UART0. */
|
||||
#define SYS_MFP_P50_XT1_IN 0x00000001UL /*!< External 4~24 MHz (high speed) crystal input pin. */
|
||||
#define SYS_MFP_P50_Msk 0x00000101UL /*!< P5_MFP pin 0 mask */
|
||||
|
||||
#define SYS_MFP_P51_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P51_I2C1_SCL 0x00000200UL /*!< I2C1 clock pin. */
|
||||
#define SYS_MFP_P51_UART0_RXD 0x00000202UL /*!< Data receiver input pin for UART0. */
|
||||
#define SYS_MFP_P51_XT1_OUT 0x00000002UL /*!< External 4~24 MHz (high speed) crystal output pin. */
|
||||
#define SYS_MFP_P51_Msk 0x00000202UL /*!< P5_MFP pin 1 mask */
|
||||
|
||||
#define SYS_MFP_P52_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P52_INT1 0x00000004UL /*!< External interrupt1 input pin. */
|
||||
#define SYS_MFP_P52_Msk 0x00000404UL /*!< P5_MFP pin 2 mask */
|
||||
|
||||
#define SYS_MFP_P53_ADC_CH0 0x00000008UL /*!< ADC channel0 analog input. */
|
||||
#define SYS_MFP_P53_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P53_Msk 0x00000808UL /*!< P5_MFP pin 3 mask */
|
||||
|
||||
#define SYS_MFP_P54_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P54_Msk 0x00001010UL /*!< P5_MFP pin 4 mask */
|
||||
|
||||
#define SYS_MFP_P55_GPIO 0x00000000UL /*!< General purpose digital I/O pin. */
|
||||
#define SYS_MFP_P55_Msk 0x00002020UL /*!< P5_MFP pin 5 mask */
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_SYS_EXPORTED_CONSTANTS */
|
||||
|
||||
/** @addtogroup Mini58_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
|
||||
@{
|
||||
*/
|
||||
/**
|
||||
* @brief Clear Brown-out detector interrupt flag
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro clear Brown-out detector interrupt flag.
|
||||
*/
|
||||
#define SYS_CLEAR_BOD_INT_FLAG() (SYS->BODCTL |= SYS_BODCTL_BODIF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set Brown-out detector function to normal mode
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro set Brown-out detector to normal mode.
|
||||
* The register write-protection function should be disabled before using this macro.
|
||||
*/
|
||||
#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable Brown-out detector function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro disable Brown-out detector function.
|
||||
* The register write-protection function should be disabled before using this macro.
|
||||
*/
|
||||
#define SYS_DISABLE_BOD() (SYS->BODCTL = (SYS->BODCTL &~(SYS_BODCTL_BODVL_Msk|SYS_BODCTL_BODEN_Msk))|SYS_BODCTL_BODVL_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable Brown-out detector function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro enable Brown-out detector function.
|
||||
* The register write-protection function should be disabled before using this macro.
|
||||
*/
|
||||
#define SYS_ENABLE_BOD() (SYS->BODCTL = (SYS->BODCTL | SYS_BODCTL_BODEN_Msk))
|
||||
|
||||
/**
|
||||
* @brief Get Brown-out detector interrupt flag
|
||||
* @param None
|
||||
* @retval 0 Brown-out detect interrupt flag is not set.
|
||||
* @retval >=1 Brown-out detect interrupt flag is set.
|
||||
* @details This macro get Brown-out detector interrupt flag.
|
||||
*/
|
||||
#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get Brown-out detector status
|
||||
* @param None
|
||||
* @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled.
|
||||
* @retval >=1 System voltage is lower than BOD threshold voltage setting.
|
||||
* @details This macro get Brown-out detector output status.
|
||||
* If the BOD function is disabled, this function always return 0.
|
||||
*/
|
||||
#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable Brown-out detector interrupt function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro enable Brown-out detector interrupt function.
|
||||
* The register write-protection function should be disabled before using this macro.
|
||||
*/
|
||||
#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Enable Brown-out detector reset function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro enable Brown-out detect reset function.
|
||||
* The register write-protection function should be disabled before using this macro.
|
||||
*/
|
||||
#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set Brown-out detector function low power mode
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro set Brown-out detector to low power mode.
|
||||
* The register write-protection function should be disabled before using this macro.
|
||||
*/
|
||||
#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk)
|
||||
|
||||
/**
|
||||
* @brief Set Brown-out detector voltage level
|
||||
* @param[in] u32Level is Brown-out voltage level. Including :
|
||||
* - \ref SYS_BODCTL_BODVL_4_4V
|
||||
* - \ref SYS_BODCTL_BODVL_3_7V
|
||||
* - \ref SYS_BODCTL_BODVL_2_7V
|
||||
* - \ref SYS_BODCTL_BODVL_2_2V
|
||||
* @return None
|
||||
* @details This macro set Brown-out detector voltage level.
|
||||
* The write-protection function should be disabled before using this macro.
|
||||
*/
|
||||
#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level))
|
||||
|
||||
/**
|
||||
* @brief Get reset source is from Brown-out detector reset
|
||||
* @param None
|
||||
* @retval 0 Previous reset source is not from Brown-out detector reset
|
||||
* @retval >=1 Previous reset source is from Brown-out detector reset
|
||||
* @details This macro get previous reset source is from Brown-out detect reset or not.
|
||||
*/
|
||||
#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get reset source is from CPU reset
|
||||
* @param None
|
||||
* @retval 0 Previous reset source is not from CPU reset
|
||||
* @retval >=1 Previous reset source is from CPU reset
|
||||
* @details This macro get previous reset source is from CPU reset.
|
||||
*/
|
||||
#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get reset source is from Power-on Reset
|
||||
* @param None
|
||||
* @retval 0 Previous reset source is not from Power-on Reset
|
||||
* @retval >=1 Previous reset source is from Power-on Reset
|
||||
* @details This macro get previous reset source is from Power-on Reset.
|
||||
*/
|
||||
#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get reset source is from reset pin reset
|
||||
* @param None
|
||||
* @retval 0 Previous reset source is not from reset pin reset
|
||||
* @retval >=1 Previous reset source is from reset pin reset
|
||||
* @details This macro get previous reset source is from reset pin reset.
|
||||
*/
|
||||
#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get reset source is from system reset
|
||||
* @param None
|
||||
* @retval 0 Previous reset source is not from system reset
|
||||
* @retval >=1 Previous reset source is from system reset
|
||||
* @details This macro get previous reset source is from system reset.
|
||||
*/
|
||||
#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Get reset source is from window watch dog reset
|
||||
* @param None
|
||||
* @retval 0 Previous reset source is not from window watch dog reset
|
||||
* @retval >=1 Previous reset source is from window watch dog reset
|
||||
* @details This macro get previous reset source is from window watch dog reset.
|
||||
*/
|
||||
#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk)
|
||||
|
||||
/**
|
||||
* @brief Disable Power-on Reset function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro disable Power-on Reset function.
|
||||
* The register write-protection function should be disabled before using this macro.
|
||||
*/
|
||||
#define SYS_DISABLE_POR() (SYS->PORCTL = 0x5AA5)
|
||||
|
||||
/**
|
||||
* @brief Enable Power-on Reset function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This macro enable Power-on Reset function.
|
||||
* The register write-protection function should be disabled before using this macro.
|
||||
*/
|
||||
#define SYS_ENABLE_POR() (SYS->PORCTL = 0)
|
||||
|
||||
/**
|
||||
* @brief Clear reset source flag
|
||||
* @param[in] u32RstSrc is reset source. Including :
|
||||
* - \ref SYS_RSTSTS_PORF_Msk
|
||||
* - \ref SYS_RSTSTS_PINRF_Msk
|
||||
* - \ref SYS_RSTSTS_WDTRF_Msk
|
||||
* - \ref SYS_RSTSTS_BODRF_Msk
|
||||
* - \ref SYS_RSTSTS_SYSRF_Msk
|
||||
* - \ref SYS_RSTSTS_CPURF_Msk
|
||||
* - \ref SYS_RSTSTS_CPULKRF_Msk
|
||||
* @return None
|
||||
* @details This macro clear reset source flag.
|
||||
*/
|
||||
#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) )
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable register write-protection function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function disable register write-protection function.
|
||||
* To unlock the protected register to allow write access.
|
||||
*/
|
||||
__STATIC_INLINE void SYS_UnlockReg(void)
|
||||
{
|
||||
do
|
||||
{
|
||||
SYS->REGLCTL = 0x59;
|
||||
SYS->REGLCTL = 0x16;
|
||||
SYS->REGLCTL = 0x88;
|
||||
}
|
||||
while(SYS->REGLCTL == 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable register write-protection function
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function is used to enable register write-protection function.
|
||||
* To lock the protected register to forbid write access.
|
||||
*/
|
||||
__STATIC_INLINE void SYS_LockReg(void)
|
||||
{
|
||||
SYS->REGLCTL = 0;
|
||||
}
|
||||
|
||||
void SYS_ClearResetSrc(uint32_t u32Src);
|
||||
uint32_t SYS_GetBODStatus(void);
|
||||
uint32_t SYS_GetResetSrc(void);
|
||||
uint32_t SYS_IsRegLocked(void);
|
||||
uint32_t SYS_ReadPDID(void);
|
||||
void SYS_ResetChip(void);
|
||||
void SYS_ResetCPU(void);
|
||||
void SYS_ResetModule(uint32_t u32ModuleIndex);
|
||||
void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel);
|
||||
void SYS_DisableBOD(void);
|
||||
|
||||
/*@}*/ /* end of group Mini58_SYS_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_SYS_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__SYS_H__
|
||||
@@ -0,0 +1,328 @@
|
||||
/**************************************************************************//**
|
||||
* @file timer.h
|
||||
* @version V1.00
|
||||
* $Revision: 7 $
|
||||
* $Date: 15/05/27 11:56a $
|
||||
* @brief Mini58 series TIMER driver header file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __TIMER_H__
|
||||
#define __TIMER_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_TIMER_Driver TIMER Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
#define TIMER_ONESHOT_MODE (0UL) /*!< Timer working in one shot mode */
|
||||
#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode */
|
||||
#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle mode */
|
||||
#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous mode */
|
||||
#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL) /*!< Free counting mode */
|
||||
#define TIMER_CAPTURE_TRIGGER_COUNTING_MODE (TIMER_EXTCTL_CAPSEL_Msk) /*!< Trigger counting mode */
|
||||
#define TIMER_CAPTURE_COUNTER_RESET_MODE (TIMER_EXTCTL_CAPFUNCS_Msk) /*!< Counter reset mode */
|
||||
#define TIMER_CAPTURE_FALLING_EDGE (0UL) /*!< Falling edge trigger timer capture */
|
||||
#define TIMER_CAPTURE_RISING_EDGE (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge trigger timer capture */
|
||||
#define TIMER_CAPTURE_FALLING_THEN_RISING_EDGE (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge then rising edge trigger timer capture */
|
||||
#define TIMER_CAPTURE_RISING_THEN_FALLING_EDGE (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge then falling edge trigger timer capture */
|
||||
#define TIMER_COUNTER_RISING_EDGE (TIMER_EXTCTL_CNTPHASE_Msk) /*!< Counter increase on rising edge */
|
||||
#define TIMER_COUNTER_FALLING_EDGE (0UL) /*!< Counter increase on falling edge */
|
||||
#define TIMER_TOGGLE_TMX_CNT_OUT (0UL) /*!< Timer use TMx_CNT_OUT, x = 0, 1 pin as toggle output pin */
|
||||
#define TIMER_TOGGLE_TMX_EXT (TIMER_CTL_TGLPINSEL_Msk) /*!< Timer use TMx_EXT, x = 0, 1 pin as toggle output pin */
|
||||
|
||||
/*@}*/ /* end of group Mini58_TIMER_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup Mini58_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This macro is used to set new Timer compared value
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value))
|
||||
|
||||
/**
|
||||
* @brief This macro is used to set new Timer prescale value
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF
|
||||
* @return None
|
||||
* @note Clock input is divided by (prescale + 1) before it is fed into timer
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
|
||||
|
||||
/**
|
||||
* @brief This macro is used to check if specify Timer is inactive or active
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return timer is activate or inactivate
|
||||
* @retval 0 Timer 24-bit up counter is inactive
|
||||
* @retval 1 Timer 24-bit up counter is active
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define TIMER_IS_ACTIVE(timer) ((timer)->CTL & TIMER_CTL_ACTSTS_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to select Timer toggle output pin
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @param[in] u32ToutSel Toggle output pin selection, valid values are
|
||||
* - \ref TIMER_TOGGLE_TMX_CNT_OUT
|
||||
* - \ref TIMER_TOGGLE_TMX_EXT
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function is used to start Timer counting
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_Start(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL |= TIMER_CTL_CNTEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to stop Timer counting
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_Stop(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL &= ~TIMER_CTL_CNTEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to enable the Timer wake-up function
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
* @note To wake the system from power down mode, timer clock source must be ether LXT or LIRC
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL |= TIMER_CTL_WKEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to disable the Timer wake-up function
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL &= ~TIMER_CTL_WKEN_Msk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function is used to enable the capture pin detection de-bounce function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
|
||||
{
|
||||
timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to disable the capture pin detection de-bounce function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
|
||||
{
|
||||
timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function is used to enable the counter pin detection de-bounce function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
|
||||
{
|
||||
timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to disable the counter pin detection de-bounce function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
|
||||
{
|
||||
timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to enable the Timer time-out interrupt function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL |= TIMER_CTL_INTEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to disable the Timer time-out interrupt function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL &= ~TIMER_CTL_INTEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to enable the Timer capture trigger interrupt function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
|
||||
{
|
||||
timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to disable the Timer capture trigger interrupt function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
|
||||
{
|
||||
timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function indicates Timer time-out interrupt occurred or not.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return Timer time-out interrupt occurred or not
|
||||
* @retval 0 Timer time-out interrupt did not occur
|
||||
* @retval 1 Timer time-out interrupt occurred
|
||||
*/
|
||||
__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
|
||||
{
|
||||
return(timer->INTSTS & TIMER_INTSTS_TIF_Msk ? 1 : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function clears the Timer time-out interrupt flag.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
|
||||
{
|
||||
timer->INTSTS = TIMER_INTSTS_TIF_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function indicates Timer capture interrupt occurred or not.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return Timer capture interrupt occurred or not
|
||||
* @retval 0 Timer capture interrupt did not occur
|
||||
* @retval 1 Timer capture interrupt occurred
|
||||
*/
|
||||
__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
|
||||
{
|
||||
return timer->EINTSTS;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function clears the Timer capture interrupt flag.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
|
||||
{
|
||||
timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function indicates Timer has waked up system or not.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return Timer has waked up system or not
|
||||
* @retval 0 Timer did not wake up system
|
||||
* @retval 1 Timer wake up system
|
||||
*/
|
||||
__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
|
||||
{
|
||||
return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1 : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function clears the Timer wakeup interrupt flag.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
|
||||
{
|
||||
timer->INTSTS = TIMER_INTSTS_TWKF_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function gets the Timer capture data.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return Timer capture data value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
|
||||
{
|
||||
return timer->CAP;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function reports the current timer counter value.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return Timer counter value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
|
||||
{
|
||||
return timer->CNT;
|
||||
}
|
||||
|
||||
uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
|
||||
void TIMER_Close(TIMER_T *timer);
|
||||
void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
|
||||
void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
|
||||
void TIMER_DisableCapture(TIMER_T *timer);
|
||||
void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
|
||||
void TIMER_DisableEventCounter(TIMER_T *timer);
|
||||
uint32_t TIMER_GetModuleClock(TIMER_T *timer);
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_TIMER_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_TIMER_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__TIMER_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,382 @@
|
||||
/**************************************************************************//**
|
||||
* @file UART.h
|
||||
* @version V1.00
|
||||
* $Revision: 3 $
|
||||
* $Date: 15/05/28 4:34p $
|
||||
* @brief Mini58 series UART driver header file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __UART_H__
|
||||
#define __UART_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_UART_Driver UART Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_UART_EXPORTED_CONSTANTS UART Exported Constants
|
||||
@{
|
||||
*/
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UART_FIFO constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
#define UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 bit */
|
||||
#define UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bits */
|
||||
#define UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bits */
|
||||
#define UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bits */
|
||||
|
||||
#define UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 1 bit */
|
||||
#define UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 4 bits */
|
||||
#define UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 8 bits */
|
||||
#define UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 14 bits */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UART_LINE constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UART_WORD_LEN_5 (0) /*!< UART_LINE setting to set UART word length to 5 bits */
|
||||
#define UART_WORD_LEN_6 (1) /*!< UART_LINE setting to set UART word length to 6 bits */
|
||||
#define UART_WORD_LEN_7 (2) /*!< UART_LINE setting to set UART word length to 7 bits */
|
||||
#define UART_WORD_LEN_8 (3) /*!< UART_LINE setting to set UART word length to 8 bits */
|
||||
|
||||
#define UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity */
|
||||
#define UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity */
|
||||
#define UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity */
|
||||
#define UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' */
|
||||
#define UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' */
|
||||
|
||||
#define UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit */
|
||||
#define UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length */
|
||||
#define UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UART RTS LEVEL TRIGGER constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UART_RTS_IS_HIGH_LEV_TRG (0x1 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Trigger */
|
||||
#define UART_RTS_IS_LOW_LEV_TRG (0x0 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Trigger */
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* UA_FUNC_SEL constants definitions */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
#define UART_FUNC_SEL_UART (0x0 << UART_FUNSEL_FUN_SEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) */
|
||||
#define UART_FUNC_SEL_IrDA (0x2 << UART_FUNSEL_FUN_SEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function */
|
||||
#define UART_FUNC_SEL_RS485 (0x3 << UART_FUNSEL_FUN_SEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function */
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_UART_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup Mini58_UART_EXPORTED_FUNCTIONS UART Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Calculate UART baudrate mode0 divider
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return UART baudrate mode0 register setting value
|
||||
*
|
||||
*/
|
||||
#define UART_BAUD_MODE0 (0)
|
||||
|
||||
/**
|
||||
* @brief Calculate UART baudrate mode0 divider
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return UART baudrate mode2 register setting value
|
||||
*
|
||||
*/
|
||||
#define UART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Calculate UART baudrate mode0 divider
|
||||
*
|
||||
* @param[in] u32SrcFreq UART clock frequency
|
||||
* @param[in] u32BaudRate Baudrate of UART module
|
||||
*
|
||||
* @return UART baudrate mode0 divider
|
||||
*
|
||||
*/
|
||||
#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate*8)) / u32BaudRate >> 4)-2)
|
||||
|
||||
/**
|
||||
* @brief Calculate UART baudrate mode2 divider
|
||||
*
|
||||
* @param[in] u32SrcFreq UART clock frequency
|
||||
* @param[in] u32BaudRate Baudrate of UART module
|
||||
*
|
||||
* @return UART baudrate mode2 divider
|
||||
*/
|
||||
#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) (((u32SrcFreq + (u32BaudRate/2)) / u32BaudRate)-2)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write Data to Tx data register
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
* @param[in] u8Data Data byte to transmit
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
#define UART_WRITE(uart, u8Data) (uart->DAT = (u8Data))
|
||||
|
||||
/**
|
||||
* @brief Read Rx data register
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
*
|
||||
* @return The oldest data byte in RX FIFO
|
||||
*/
|
||||
#define UART_READ(uart) (uart->DAT)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Tx empty register value.
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return Tx empty register value.
|
||||
*/
|
||||
#define UART_GET_TX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Rx empty register value.
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return Rx empty register value.
|
||||
*/
|
||||
#define UART_GET_RX_EMPTY(uart) (uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
|
||||
|
||||
/**
|
||||
* @brief Check specified uart port transmission is over.
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return TE_Flag.
|
||||
*/
|
||||
#define UART_IS_TX_EMPTY(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Wait specified uart port transmission is over
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
#define UART_WAIT_TX_EMPTY(uart) while(!(((uart->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
|
||||
|
||||
/**
|
||||
* @brief Check RDA_IF is set or not
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return
|
||||
* 0 : The number of bytes in the RX FIFO is less than the RFITL
|
||||
* 1 : The number of bytes in the RX FIFO equals or larger than RFITL
|
||||
*/
|
||||
#define UART_IS_RX_READY(uart) ((uart->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check TX FIFO is full or not
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return
|
||||
* 1 = TX FIFO is full
|
||||
* 0 = TX FIFO is not full
|
||||
*/
|
||||
#define UART_IS_TX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
|
||||
|
||||
/**
|
||||
* @brief Check RX FIFO is full or not
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return
|
||||
* 1 = RX FIFO is full
|
||||
* 0 = RX FIFO is not full
|
||||
*
|
||||
*/
|
||||
#define UART_IS_RX_FULL(uart) ((uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Tx full register value
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return Tx full register value
|
||||
*/
|
||||
#define UART_GET_TX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get Rx full register value
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
*
|
||||
* @return Rx full register value
|
||||
*/
|
||||
#define UART_GET_RX_FULL(uart) (uart->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable specified interrupt
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
* @param[in] u32eIntSel Interrupt type select
|
||||
* - \ref UART_INTEN_TOCNTEN_Msk : Rx Time Out interrupt
|
||||
* - \ref UART_INTEN_WKCTSIEN_Msk : Wakeup interrupt
|
||||
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
|
||||
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
|
||||
* - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
|
||||
* - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
|
||||
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
|
||||
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
#define UART_ENABLE_INT(uart, u32eIntSel) (uart->INTEN |= (u32eIntSel))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable specified interrupt
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
* @param[in] u32eIntSel Interrupt type select
|
||||
* - \ref UART_INTEN_TOCNTEN_Msk : Rx Time Out interrupt
|
||||
* - \ref UART_INTEN_WKCTSIEN_Msk : Wakeup interrupt
|
||||
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
|
||||
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
|
||||
* - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
|
||||
* - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
|
||||
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
|
||||
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
|
||||
* @return None
|
||||
*/
|
||||
#define UART_DISABLE_INT(uart, u32eIntSel) (uart->INTEN &= ~ (u32eIntSel))
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get specified interrupt flag/status
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
* @param[in] u32eIntTypeFlag Interrupt Type Flag,should be
|
||||
* - \ref UART_INTSTS_CTSWKIF_Msk : nCTS Wake-Up Interrupt Flag
|
||||
* - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator
|
||||
* - \ref UART_INTSTS_RXTOINT_Msk : Time-out Interrupt Indicator
|
||||
* - \ref UART_INTSTS_MODEMINT_Msk : MODEM Status Interrupt Indicator
|
||||
* - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt
|
||||
* - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator
|
||||
* - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator
|
||||
* - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag
|
||||
* - \ref UART_INTSTS_RXTOIF_Msk : Rx time-out interrupt Flag
|
||||
* - \ref UART_INTSTS_MODEMIF_Msk : Modem interrupt Flag
|
||||
* - \ref UART_INTSTS_RLSIF_Msk : Rx Line status interrupt Flag
|
||||
* - \ref UART_INTSTS_THREIF_Msk : Tx empty interrupt Flag
|
||||
* - \ref UART_INTSTS_RDAIF_Msk : Rx ready interrupt Flag
|
||||
*
|
||||
* @return
|
||||
* 0 = The specified interrupt is not happened.
|
||||
* 1 = The specified interrupt is happened.
|
||||
*/
|
||||
#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) ((uart->INTSTS & (u32eIntTypeFlag))?1:0)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set RTS pin is low
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
* @return None
|
||||
*/
|
||||
__INLINE void UART_CLEAR_RTS(UART_T* uart)
|
||||
{
|
||||
uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
|
||||
uart->MODEM &= ~UART_MODEM_RTS_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set RTS pin is high
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
* @return None
|
||||
*/
|
||||
__INLINE void UART_SET_RTS(UART_T* uart)
|
||||
{
|
||||
uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear RS-485 Address Byte Detection Flag
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
* @return None
|
||||
*/
|
||||
#define UART_RS485_CLEAR_ADDR_FLAG(uart) (uart->FIFOSTS |= UART_FIFOSTS_ADDRDETF_Msk)
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get RS-485 Address Byte Detection Flag
|
||||
*
|
||||
* @param[in] uart The base address of UART module
|
||||
* @return RS-485 Address Byte Detection Flag
|
||||
*/
|
||||
#define UART_RS485_GET_ADDR_FLAG(uart) ((uart->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
|
||||
|
||||
|
||||
void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag);
|
||||
void UART_Close(UART_T* uart );
|
||||
void UART_DisableFlowCtrl(UART_T* uart );
|
||||
void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag );
|
||||
void UART_EnableFlowCtrl(UART_T* uart );
|
||||
void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag );
|
||||
void UART_Open(UART_T* uart, uint32_t u32baudrate);
|
||||
uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
|
||||
void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
|
||||
void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
|
||||
void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
|
||||
void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
|
||||
uint32_t UART_Write(UART_T* uart,uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_UART_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_UART_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__UART_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,128 @@
|
||||
/**************************************************************************//**
|
||||
* @file wdt.h
|
||||
* @version V1.00
|
||||
* $Revision: 2 $
|
||||
* $Date: 15/05/28 1:16p $
|
||||
* @brief Mini58 series WDT driver header file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __WDT_H__
|
||||
#define __WDT_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_WDT_Driver WDT Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_WDT_EXPORTED_CONSTANTS WDT Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^4 * WDT clocks */
|
||||
#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^6 * WDT clocks */
|
||||
#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^8 * WDT clocks */
|
||||
#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^10 * WDT clocks */
|
||||
#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^12 * WDT clocks */
|
||||
#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^14 * WDT clocks */
|
||||
#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^16 * WDT clocks */
|
||||
#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< WDT setting for timeout interval = 2^18 * WDT clocks */
|
||||
|
||||
#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT setting reset delay to 3 WDT clocks */
|
||||
#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT setting reset delay to 18 WDT clocks */
|
||||
#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT setting reset delay to 130 WDT clocks */
|
||||
#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT setting reset delay to 1026 WDT clocks */
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_WDT_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup Mini58_WDT_EXPORTED_FUNCTIONS WDT Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This macro clear WDT time-out reset system flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro clear WDT time-out interrupt flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro clear WDT time-out wake-up system flag.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro indicate WDT time-out to reset system or not.
|
||||
* @return WDT reset system or not
|
||||
* @retval 0 WDT did not cause system reset
|
||||
* @retval 1 WDT caused system reset
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_GET_RESET_FLAG() (WDT->CTL & WDT_CTL_RSTF_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief This macro indicate WDT time-out interrupt occurred or not.
|
||||
* @return WDT time-out interrupt occurred or not
|
||||
* @retval 0 WDT time-out interrupt did not occur
|
||||
* @retval 1 WDT time-out interrupt occurred
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_GET_TIMEOUT_INT_FLAG() (WDT->CTL & WDT_CTL_IF_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief This macro indicate WDT time-out waked system up or not
|
||||
* @return WDT time-out waked system up or not
|
||||
* @retval 0 WDT did not wake up system
|
||||
* @retval 1 WDT waked up system
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_GET_TIMEOUT_WAKEUP_FLAG() (WDT->CTL & WDT_CTL_WKF_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to reset 18-bit WDT counter.
|
||||
* @details If WDT is activated and enabled to reset system, software must reset WDT counter
|
||||
* before WDT time-out plus reset delay reached. Or WDT generate a reset signal.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WDT_RESET_COUNTER() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_RSTCNT_Msk)
|
||||
|
||||
|
||||
void WDT_Open(uint32_t u32TimeoutInterval,
|
||||
uint32_t u32ResetDelay,
|
||||
uint32_t u32EnableReset,
|
||||
uint32_t u32EnableWakeup);
|
||||
void WDT_Close(void);
|
||||
|
||||
void WDT_EnableInt(void);
|
||||
void WDT_DisableInt(void);
|
||||
|
||||
/*@}*/ /* end of group Mini58_WDT_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_WDT_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__WDT_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,125 @@
|
||||
/**************************************************************************//**
|
||||
* @file wwdt.h
|
||||
* @version V1.00
|
||||
* $Revision: 1 $
|
||||
* $Date: 15/02/02 3:19p $
|
||||
* @brief Mini58 series WWDT driver header file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#ifndef __WWDT_H__
|
||||
#define __WWDT_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_WWDT_Driver WWDT Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
|
||||
@{
|
||||
*/
|
||||
#define WWDT_PRESCALER_1 (0UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 1 \hideinitializer
|
||||
#define WWDT_PRESCALER_2 (1UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 2 \hideinitializer
|
||||
#define WWDT_PRESCALER_4 (2UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 4 \hideinitializer
|
||||
#define WWDT_PRESCALER_8 (3UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 8 \hideinitializer
|
||||
#define WWDT_PRESCALER_16 (4UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 16 \hideinitializer
|
||||
#define WWDT_PRESCALER_32 (5UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 32 \hideinitializer
|
||||
#define WWDT_PRESCALER_64 (6UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 64 \hideinitializer
|
||||
#define WWDT_PRESCALER_128 (7UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 128 \hideinitializer
|
||||
#define WWDT_PRESCALER_192 (8UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 192 \hideinitializer
|
||||
#define WWDT_PRESCALER_256 (9UL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 256 \hideinitializer
|
||||
#define WWDT_PRESCALER_384 (0xAUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 384 \hideinitializer
|
||||
#define WWDT_PRESCALER_512 (0xBUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 512 \hideinitializer
|
||||
#define WWDT_PRESCALER_768 (0xCUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 768 \hideinitializer
|
||||
#define WWDT_PRESCALER_1024 (0xDUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 1024 \hideinitializer
|
||||
#define WWDT_PRESCALER_1536 (0xEUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 1536 \hideinitializer
|
||||
#define WWDT_PRESCALER_2048 (0xFUL << WWDT_CTL_PSCSEL_Pos) ///< WWDT setting prescaler to 2048 \hideinitializer
|
||||
|
||||
#define WWDT_RELOAD_WORD (0x00005AA5) ///< Fill this value to RLD register to reload WWDT counter \hideinitializer
|
||||
/*@}*/ /* end of group Mini58_WWDT_EXPORTED_CONSTANTS */
|
||||
|
||||
|
||||
/** @addtogroup Mini58_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This macro clear WWDT time-out reset system flag.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro clear WWDT compare match interrupt flag.
|
||||
* @param None
|
||||
* @return None
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
|
||||
|
||||
/**
|
||||
* @brief This macro is use to get WWDT time-out reset system flag.
|
||||
* @return WWDT reset system or not
|
||||
* @retval 0 WWDT did not cause system reset
|
||||
* @retval 1 WWDT caused system reset
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_GET_RESET_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to indicate WWDT compare match interrupt flag.
|
||||
* @return WWDT compare match interrupt occurred or not
|
||||
* @retval 0 WWDT compare match interrupt did not occur
|
||||
* @retval 1 WWDT compare match interrupt occurred
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_GET_INT_FLAG() (WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk ? 1 : 0)
|
||||
|
||||
/**
|
||||
* @brief This macro to reflects current WWDT counter value
|
||||
* @param None
|
||||
* @return Return current WWDT counter value
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_GET_COUNTER() (WWDT->CNT)
|
||||
|
||||
/**
|
||||
* @brief This macro is used to reload the WWDT counter value to 0x3F.
|
||||
* @param None
|
||||
* @return None
|
||||
* @details After WWDT enabled, application must reload WWDT counter while
|
||||
* current counter is less than compare value and larger than 0,
|
||||
* otherwise WWDT will cause system reset.
|
||||
* \hideinitializer
|
||||
*/
|
||||
#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)
|
||||
|
||||
|
||||
void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_WWDT_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_WWDT_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif //__WWDT_H__
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,97 @@
|
||||
/**************************************************************************//**
|
||||
* @file acmp.c
|
||||
* @version V1.00
|
||||
* $Revision: 2 $
|
||||
* $Date: 15/02/24 7:19p $
|
||||
* @brief Mini58 series Analog Comparator(ACMP) driver source file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
|
||||
#include "Mini58Series.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_ACMP_Driver ACMP Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Mini58_ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configure the specified ACMP module
|
||||
*
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum comparator number.
|
||||
* @param[in] u32NegSrc is comparator negative input selection. Including:
|
||||
* - \ref ACMP_VNEG_PIN
|
||||
* - \ref ACMP_VNEG_BANDGAP
|
||||
* - \ref ACMP_VNEG_4_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_5_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_6_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_7_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_8_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_9_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_10_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_11_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_12_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_13_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_14_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_15_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_16_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_17_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_18_OVER_24_VDD
|
||||
* - \ref ACMP_VNEG_19_OVER_24_VDD
|
||||
*
|
||||
* @param[in] u32HysteresisEn is the hysteresis function option. Including:
|
||||
* - \ref ACMP_HYSTERESIS_ENABLE or
|
||||
* - \ref ACMP_HYSTERESIS_DISABLE
|
||||
* @return None
|
||||
*/
|
||||
void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn)
|
||||
{
|
||||
if(u32NegSrc != ACMP_VNEG_PIN)
|
||||
ACMP->VREF = u32NegSrc;
|
||||
ACMP->CTL[u32ChNum] = (ACMP->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) |
|
||||
((u32NegSrc != ACMP_VNEG_PIN ? ACMP_CTL_NEGSEL_Msk : 0) | u32HysteresisEn | ACMP_CTL_ACMPEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function close comparator
|
||||
*
|
||||
* @param[in] acmp The base address of ACMP module
|
||||
* @param[in] u32ChNum comparator number.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum)
|
||||
{
|
||||
ACMP->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_ACMP_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_ACMP_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
|
||||
@@ -0,0 +1,226 @@
|
||||
/**************************************************************************//**
|
||||
* @file adc.c
|
||||
* @version V1.00
|
||||
* $Revision: 4 $
|
||||
* $Date: 15/07/21 3:15p $
|
||||
* @brief Mini58 series ADC driver source file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "Mini58Series.h"
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_ADC_Driver ADC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Mini58_ADC_EXPORTED_FUNCTIONS ADC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This API configures ADC module to be ready for convert the input from selected channel
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32InputMode This parameter is unused
|
||||
* @param[in] u32OpMode This parameter is unused
|
||||
* @param[in] u32ChMask Channel enable bit. Each bit corresponds to a input channel. Bit 0 is channel 0, bit 1 is channel 1...
|
||||
* @return None
|
||||
* @note Mini58 series MCU ADC can only convert 1 channel at a time. If more than 1 channels are enabled, only channel
|
||||
* with smallest number will be convert.
|
||||
* @note This API does not turn on ADC power nor does trigger ADC conversion
|
||||
*/
|
||||
void ADC_Open(ADC_T *adc,
|
||||
uint32_t u32InputMode,
|
||||
uint32_t u32OpMode,
|
||||
uint32_t u32ChMask)
|
||||
{
|
||||
ADC->CHEN = (ADC->CHEN & ~(ADC_CHEN_CHEN0_Msk |
|
||||
ADC_CHEN_CHEN1_Msk |
|
||||
ADC_CHEN_CHEN2_Msk |
|
||||
ADC_CHEN_CHEN3_Msk |
|
||||
ADC_CHEN_CHEN4_Msk |
|
||||
ADC_CHEN_CHEN5_Msk |
|
||||
ADC_CHEN_CHEN6_Msk |
|
||||
ADC_CHEN_CHEN7_Msk)) | u32ChMask;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ADC module
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @return None
|
||||
*/
|
||||
void ADC_Close(ADC_T *adc)
|
||||
{
|
||||
SYS->IPRST1 |= SYS_IPRST1_ADCRST_Msk;
|
||||
SYS->IPRST1 &= ~SYS_IPRST1_ADCRST_Msk;
|
||||
return;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the hardware trigger condition and enable hardware trigger
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32Source Decides the hardware trigger source. Valid values are:
|
||||
* - \ref ADC_TRIGGER_BY_EXT_PIN
|
||||
* - \ref ADC_TRIGGER_BY_PWM
|
||||
* @param[in] u32Param While ADC trigger by PWM, this parameter is used to set the delay between PWM
|
||||
* trigger and ADC conversion. Valid values are from 0 ~ 0xFF, and actual delay
|
||||
* time is (4 * u32Param * HCLK). While ADC trigger by external pin, this parameter
|
||||
* is used to set trigger condition. Valid values are:
|
||||
* - \ref ADC_FALLING_EDGE_TRIGGER
|
||||
* - \ref ADC_RISING_EDGE_TRIGGER
|
||||
* @return None
|
||||
*/
|
||||
void ADC_EnableHWTrigger(ADC_T *adc,
|
||||
uint32_t u32Source,
|
||||
uint32_t u32Param)
|
||||
{
|
||||
ADC->CTL &= ~(ADC_TRIGGER_BY_PWM | ADC_RISING_EDGE_TRIGGER | ADC_CTL_HWTRGEN_Msk);
|
||||
if(u32Source == ADC_TRIGGER_BY_EXT_PIN) {
|
||||
ADC->CTL |= u32Source | u32Param | ADC_CTL_HWTRGEN_Msk;
|
||||
} else {
|
||||
ADC->TRGDLY = (ADC->TRGDLY & ~ADC_TRGDLY_DELAY_Msk) | u32Param;
|
||||
ADC->CTL |= u32Source | ADC_CTL_HWTRGEN_Msk;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable hardware trigger ADC function.
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @return None
|
||||
*/
|
||||
void ADC_DisableHWTrigger(ADC_T *adc)
|
||||
{
|
||||
ADC->CTL &= ~(ADC_TRIGGER_BY_PWM | ADC_RISING_EDGE_TRIGGER | ADC_CTL_HWTRGEN_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set ADC sample time for designated channel.
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32ChNum This parameter is not used
|
||||
* @param[in] u32SampleTime ADC sample ADC time, valid values are
|
||||
* - \ref ADC_SAMPLE_CLOCK_0
|
||||
* - \ref ADC_SAMPLE_CLOCK_1
|
||||
* - \ref ADC_SAMPLE_CLOCK_2
|
||||
* - \ref ADC_SAMPLE_CLOCK_4
|
||||
* - \ref ADC_SAMPLE_CLOCK_8
|
||||
* - \ref ADC_SAMPLE_CLOCK_16
|
||||
* - \ref ADC_SAMPLE_CLOCK_32
|
||||
* - \ref ADC_SAMPLE_CLOCK_64
|
||||
* - \ref ADC_SAMPLE_CLOCK_128
|
||||
* - \ref ADC_SAMPLE_CLOCK_256
|
||||
* - \ref ADC_SAMPLE_CLOCK_512
|
||||
* - \ref ADC_SAMPLE_CLOCK_1024
|
||||
* @return None
|
||||
*/
|
||||
void ADC_SetExtraSampleTime(ADC_T *adc,
|
||||
uint32_t u32ChNum,
|
||||
uint32_t u32SampleTime)
|
||||
{
|
||||
ADC->EXTSMPT = (ADC->EXTSMPT & ~ADC_EXTSMPT_EXTSMPT_Msk) | u32SampleTime;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the interrupt(s) selected by u32Mask parameter.
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
|
||||
* corresponds to a interrupt status. This parameter decides which
|
||||
* interrupts will be enabled.
|
||||
* - \ref ADC_ADIF_INT
|
||||
* - \ref ADC_CMP0_INT
|
||||
* - \ref ADC_CMP1_INT
|
||||
* @return None
|
||||
*/
|
||||
void ADC_EnableInt(ADC_T *adc, uint32_t u32Mask)
|
||||
{
|
||||
if(u32Mask & ADC_ADIF_INT)
|
||||
ADC->CTL |= ADC_CTL_ADCIEN_Msk;
|
||||
if(u32Mask & ADC_CMP0_INT)
|
||||
ADC->CMP0 |= ADC_CMP0_ADCMPIE_Msk;
|
||||
if(u32Mask & ADC_CMP1_INT)
|
||||
ADC->CMP1 |= ADC_CMP1_ADCMPIE_Msk;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the interrupt(s) selected by u32Mask parameter.
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32Mask The combination of interrupt status bits listed below. Each bit
|
||||
* corresponds to a interrupt status. This parameter decides which
|
||||
* interrupts will be disabled.
|
||||
* - \ref ADC_ADIF_INT
|
||||
* - \ref ADC_CMP0_INT
|
||||
* - \ref ADC_CMP1_INT
|
||||
* @return None
|
||||
*/
|
||||
void ADC_DisableInt(ADC_T *adc, uint32_t u32Mask)
|
||||
{
|
||||
if(u32Mask & ADC_ADIF_INT)
|
||||
ADC->CTL &= ~ADC_CTL_ADCIEN_Msk;
|
||||
if(u32Mask & ADC_CMP0_INT)
|
||||
ADC->CMP0 &= ~ADC_CMP0_ADCMPIE_Msk;
|
||||
if(u32Mask & ADC_CMP1_INT)
|
||||
ADC->CMP1 &= ~ADC_CMP1_ADCMPIE_Msk;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ADC PWM Sequential Mode Control.
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32SeqTYPE This parameter decides which type will be selected.
|
||||
* - \ref ADC_SEQMODE_TYPE_23SHUNT
|
||||
* - \ref ADC_SEQMODE_TYPE_1SHUNT
|
||||
* @param[in] u32ModeSel This parameter decides which mode will be selected.
|
||||
* - \ref ADC_SEQMODE_MODESELECT_CH01
|
||||
* - \ref ADC_SEQMODE_MODESELECT_CH12
|
||||
* - \ref ADC_SEQMODE_MODESELECT_CH02
|
||||
* @return None
|
||||
*/
|
||||
void ADC_SeqModeEnable(ADC_T *adc, uint32_t u32SeqTYPE, uint32_t u32ModeSel)
|
||||
{
|
||||
// Enable ADC Sequential Mode
|
||||
ADC->SEQCTL = ADC->SEQCTL | ADC_SEQCTL_SEQEN_Msk;
|
||||
|
||||
// Select ADC Sequential Mode Type
|
||||
ADC->SEQCTL = (ADC->SEQCTL & ~(ADC_SEQCTL_SEQTYPE_Msk)) | (u32SeqTYPE << ADC_SEQCTL_SEQTYPE_Pos);
|
||||
|
||||
// Select ADC Sequential Mode Type
|
||||
ADC->SEQCTL = (ADC->SEQCTL & ~(ADC_SEQCTL_MODESEL_Msk)) | (u32ModeSel << ADC_SEQCTL_MODESEL_Pos);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief ADC PWM Sequential Mode PWM Trigger Source and type.
|
||||
* @param[in] adc Base address of ADC module
|
||||
* @param[in] u32SeqModeTriSrc1 This parameter decides first PWM trigger source and type.
|
||||
* @param[in] u32SeqModeTriSrc2 This parameter decides second PWM trigger source and type.
|
||||
*
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void ADC_SeqModeTriggerSrc(ADC_T *adc, uint32_t u32SeqModeTriSrc1, uint32_t u32SeqModeTriSrc2)
|
||||
{
|
||||
// Select PWM Trigger Source Selection for TRG1CTL or TRG2CTL
|
||||
ADC->SEQCTL = (ADC->SEQCTL & ~(ADC_SEQCTL_TRG1CTL_Msk)) | (u32SeqModeTriSrc1 << ADC_SEQCTL_TRG1CTL_Pos);
|
||||
ADC->SEQCTL = (ADC->SEQCTL & ~(ADC_SEQCTL_TRG2CTL_Msk)) | (u32SeqModeTriSrc2 << ADC_SEQCTL_TRG2CTL_Pos);
|
||||
return;
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group Mini58_ADC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_ADC_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,615 @@
|
||||
/**************************************************************************//**
|
||||
* @file clk.c
|
||||
* @version V1.00
|
||||
* $Revision: 15 $
|
||||
* $Date: 15/06/05 9:39a $
|
||||
* @brief Mini58 series CLK driver source file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "Mini58Series.h"
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_CLK_Driver CLK Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Mini58_CLK_EXPORTED_FUNCTIONS CLK Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function disable frequency output function.
|
||||
* @return None
|
||||
*/
|
||||
void CLK_DisableCKO(void)
|
||||
{
|
||||
/* Disable CKO clock source */
|
||||
CLK->APBCLK &= (~CLK_APBCLK_CLKOCKEN_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enable frequency divider module clock,
|
||||
* enable frequency divider clock function and configure frequency divider.
|
||||
* @param[in] u32ClkSrc is frequency divider function clock source
|
||||
* - \ref CLK_CLKSEL2_CLKOSEL_XTAL
|
||||
* - \ref CLK_CLKSEL2_CLKOSEL_LIRC
|
||||
* - \ref CLK_CLKSEL2_CLKOSEL_HCLK
|
||||
* - \ref CLK_CLKSEL2_CLKOSEL_HIRC
|
||||
* @param[in] u32ClkDiv Set the clock divider to CKO. 0 <= u32ClkDiv <= 15
|
||||
* @param[in] u32ClkDivBy1En is frequency divided by one enable.
|
||||
* @return None
|
||||
*
|
||||
* @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv.
|
||||
* The formula is:
|
||||
* CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1)
|
||||
* This function is just used to set CKO clock.
|
||||
* User must enable I/O for CKO clock output pin by themselves.
|
||||
*/
|
||||
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En)
|
||||
{
|
||||
/* CKO = clock source / 2^(u32ClkDiv + 1) */
|
||||
CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | u32ClkDivBy1En<<CLK_CLKOCTL_DIV1EN_Pos;
|
||||
|
||||
/* Enable CKO clock source */
|
||||
CLK->APBCLK |= CLK_APBCLK_CLKOCKEN_Msk;
|
||||
|
||||
/* Select CKO clock source */
|
||||
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_CLKOSEL_Msk)) | u32ClkSrc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function let system enter to Power-down mode.
|
||||
* @return None
|
||||
*/
|
||||
void CLK_PowerDown(void)
|
||||
{
|
||||
SCB->SCR = SCB_SCR_SLEEPDEEP_Msk;
|
||||
CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk | CLK_PWRCTL_PDWKIF_Msk);
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function let system enter to Idle mode
|
||||
* @return None
|
||||
*/
|
||||
void CLK_Idle(void)
|
||||
{
|
||||
CLK->PWRCTL |= (CLK_PWRCTL_PDEN_Msk | CLK_PWRCTL_PDWKIF_Msk);
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function get external high frequency crystal frequency. The frequency unit is Hz.
|
||||
* @return None
|
||||
*/
|
||||
uint32_t CLK_GetHXTFreq(void)
|
||||
{
|
||||
if((CLK->PWRCTL & CLK_PWRCTL_XTLEN_Msk)==CLK_PWRCTL_XTLEN_HXT )
|
||||
return __HXT;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function get external low frequency crystal frequency. The frequency unit is Hz.
|
||||
* @return LXT frequency
|
||||
*/
|
||||
uint32_t CLK_GetLXTFreq(void)
|
||||
{
|
||||
if((CLK->PWRCTL & CLK_PWRCTL_XTLEN_Msk )==CLK_PWRCTL_XTLEN_LXT )
|
||||
return __XTAL;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function get HCLK frequency. The frequency unit is Hz.
|
||||
* @return HCLK frequency
|
||||
*/
|
||||
uint32_t CLK_GetHCLKFreq(void)
|
||||
{
|
||||
SystemCoreClockUpdate();
|
||||
return SystemCoreClock;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function get CPU frequency. The frequency unit is Hz.
|
||||
* @return CPU frequency
|
||||
*/
|
||||
uint32_t CLK_GetCPUFreq(void)
|
||||
{
|
||||
SystemCoreClockUpdate();
|
||||
return SystemCoreClock;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set HCLK frequency
|
||||
* @param[in] u32Hclk is HCLK frequency. The range of u32Hclk is 26 MHz ~ 50 MHz.
|
||||
* @return HCLK frequency
|
||||
* @details This function is used to set HCLK frequency. The frequency unit is Hz.
|
||||
* It would configure PLL frequency to 100MHz ~ 200MHz,
|
||||
* set HCLK clock divider as 2 and switch HCLK clock source to PLL.
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
|
||||
{
|
||||
uint32_t u32HIRCSTB;
|
||||
|
||||
/* Read HIRC clock source stable flag */
|
||||
u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
|
||||
|
||||
/* The range of u32Hclk is 25 MHz ~ 50 MHz */
|
||||
if(u32Hclk > FREQ_50MHZ)
|
||||
u32Hclk = FREQ_50MHZ;
|
||||
if(u32Hclk < FREQ_25MHZ)
|
||||
u32Hclk = FREQ_25MHZ;
|
||||
|
||||
/* Switch HCLK clock source to HIRC clock for safe */
|
||||
CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
|
||||
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
|
||||
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
|
||||
CLK->CLKDIV &= (~CLK_CLKDIV_HCLKDIV_Msk);
|
||||
|
||||
/* Configure PLL setting if HXT clock is enabled */
|
||||
if( (CLK->PWRCTL & CLK_PWRCTL_XTLEN_Msk)==CLK_PWRCTL_XTLEN_HXT )
|
||||
u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, (u32Hclk << 1));
|
||||
|
||||
/* Configure PLL setting if HXT clock is not enabled */
|
||||
else {
|
||||
u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, (u32Hclk << 1));
|
||||
|
||||
/* Read HIRC clock source stable flag */
|
||||
u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk;
|
||||
}
|
||||
|
||||
/* Select HCLK clock source to PLL,
|
||||
Select HCLK clock source divider as 2
|
||||
and update system core clock
|
||||
*/
|
||||
//CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV_HCLK(2));
|
||||
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV_HCLK(2));
|
||||
/* Disable HIRC if HIRC is disabled before setting core clock */
|
||||
if(u32HIRCSTB == 0)
|
||||
CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk;
|
||||
|
||||
/* Return actually HCLK frequency is PLL frequency divide 2 */
|
||||
return u32Hclk >> 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function set HCLK clock source and HCLK clock divider
|
||||
* @param[in] u32ClkSrc is HCLK clock source. Including :
|
||||
* - \ref CLK_CLKSEL0_HCLKSEL_XTAL
|
||||
* - \ref CLK_CLKSEL0_HCLKSEL_LIRC
|
||||
* - \ref CLK_CLKSEL0_HCLKSEL_HIRC
|
||||
* @param[in] u32ClkDiv is HCLK clock divider. Including :
|
||||
* - \ref CLK_CLKDIV_HCLK(x)
|
||||
* @return None
|
||||
*/
|
||||
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
|
||||
{
|
||||
/* Apply new Divider */
|
||||
CLK->CLKDIV = (CLK->CLKDIV & ~CLK_CLKDIV_HCLKDIV_Msk) | u32ClkDiv;
|
||||
|
||||
/* Switch HCLK to new HCLK source */
|
||||
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_HCLKSEL_Msk) | u32ClkSrc;
|
||||
|
||||
/* Update System Core Clock */
|
||||
SystemCoreClockUpdate();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function set selected module clock source and module clock divider
|
||||
* @param[in] u32ModuleIdx is module index.
|
||||
* @param[in] u32ClkSrc is module clock source.
|
||||
* @param[in] u32ClkDiv is module clock divider.
|
||||
* @return None
|
||||
* @details Valid parameter combinations listed in following table:
|
||||
*
|
||||
* |Module index |Clock source |Divider |
|
||||
* | :---------------- | :----------------------------------- | :--------------------- |
|
||||
* |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_XTAL | x |
|
||||
* |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x |
|
||||
* |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x |
|
||||
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_XTAL | x |
|
||||
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x |
|
||||
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HCLK | x |
|
||||
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_TM0 | x |
|
||||
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x |
|
||||
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_XTAL | x |
|
||||
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x |
|
||||
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HCLK | x |
|
||||
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_TM1 | x |
|
||||
* |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x |
|
||||
* |\ref CLKO_MODULE |\ref CLK_CLKSEL2_CLKOSEL_XTAL | x |
|
||||
* |\ref CLKO_MODULE |\ref CLK_CLKSEL2_CLKOSEL_HCLK | x |
|
||||
* |\ref CLKO_MODULE |\ref CLK_CLKSEL2_CLKOSEL_HIRC | x |
|
||||
* |\ref I2C0_MODULE | x | x |
|
||||
* |\ref I2C1_MODULE | x | x |
|
||||
* |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPISEL_XTAL | x |
|
||||
* |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPISEL_HCLK | x |
|
||||
* |\ref SPI0_MODULE |\ref CLK_CLKSEL1_SPISEL_PLL | x |
|
||||
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_XTAL |\ref CLK_CLKDIV_UART(x) |
|
||||
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV_UART(x) |
|
||||
* |\ref UART0_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV_UART(x) |
|
||||
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_XTAL |\ref CLK_CLKDIV_UART(x) |
|
||||
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_PLL |\ref CLK_CLKDIV_UART(x) |
|
||||
* |\ref UART1_MODULE |\ref CLK_CLKSEL1_UARTSEL_HIRC |\ref CLK_CLKDIV_UART(x) |
|
||||
* |\ref PWMCH01_MODULE |\ref CLK_CLKSEL1_PWMCH01SEL_HCLK | x |
|
||||
* |\ref PWMCH23_MODULE |\ref CLK_CLKSEL1_PWMCH23SEL_HCLK | x |
|
||||
* |\ref PWMCH45_MODULE |\ref CLK_CLKSEL2_PWMCH45SEL_HCLK | x |
|
||||
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_XTAL |\ref CLK_CLKDIV_ADC(x) |
|
||||
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_PLL |\ref CLK_CLKDIV_ADC(x) |
|
||||
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HCLK |\ref CLK_CLKDIV_ADC(x) |
|
||||
* |\ref ADC_MODULE |\ref CLK_CLKSEL1_ADCSEL_HIRC |\ref CLK_CLKDIV_ADC(x) |
|
||||
* |\ref ACMP_MODULE | x | x |
|
||||
* |\ref WWDT_MODULE |\ref CLK_CLKSEL2_WWDTSEL_HCLK_DIV2048 | x |
|
||||
* |\ref WWDT_MODULE |\ref CLK_CLKSEL2_WWDTSEL_LIRC | x |
|
||||
*/
|
||||
|
||||
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
|
||||
{
|
||||
uint32_t u32tmp=0,u32sel=0,u32div=0;
|
||||
|
||||
if(MODULE_CLKSEL_Msk(u32ModuleIdx)!=MODULE_NoMsk) {
|
||||
u32sel = (uint32_t)&CLK->CLKSEL0+((MODULE_CLKSEL(u32ModuleIdx))*4);
|
||||
u32tmp = *(volatile uint32_t *)(u32sel);
|
||||
u32tmp = ( u32tmp & ~(MODULE_CLKSEL_Msk(u32ModuleIdx)<<MODULE_CLKSEL_Pos(u32ModuleIdx)) ) | u32ClkSrc;
|
||||
*(volatile uint32_t *)(u32sel) = u32tmp;
|
||||
}
|
||||
|
||||
if(MODULE_CLKDIV_Msk(u32ModuleIdx)!=MODULE_NoMsk) {
|
||||
u32div =(uint32_t)&CLK->CLKDIV+((MODULE_CLKDIV(u32ModuleIdx))*4);
|
||||
u32tmp = *(volatile uint32_t *)(u32div);
|
||||
u32tmp = ( u32tmp & ~(MODULE_CLKDIV_Msk(u32ModuleIdx)<<MODULE_CLKDIV_Pos(u32ModuleIdx)) ) | u32ClkDiv;
|
||||
*(volatile uint32_t *)(u32div) = u32tmp;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function set SysTick clock source
|
||||
* @param[in] u32ClkSrc is module clock source. Including
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_XTAL
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_XTAL_DIV2
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
|
||||
* @return None
|
||||
*/
|
||||
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc)
|
||||
{
|
||||
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable System Tick counter
|
||||
* @param[in] u32ClkSrc is System Tick clock source. Including:
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_XTAL
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_XTAL_DIV2
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2
|
||||
* - \ref CLK_CLKSEL0_STCLKSEL_HCLK
|
||||
* @param[in] u32Count is System Tick reload value. It should be 0x1~0xFFFFFF.
|
||||
* @return None
|
||||
* @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt.
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count)
|
||||
{
|
||||
SysTick->CTRL=0;
|
||||
if( u32ClkSrc== CLK_CLKSEL0_STCLKSEL_HCLK ) /* Set System Tick clock source */
|
||||
SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk;
|
||||
else {
|
||||
SysTick->CTRL &= ~SysTick_CTRL_CLKSOURCE_Msk;
|
||||
CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc;
|
||||
}
|
||||
SysTick->LOAD = u32Count; /* Set System Tick reload value */
|
||||
SysTick->VAL = 0; /* Clear System Tick current value and counter flag */
|
||||
SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk; /* Set System Tick counter enabled */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable System Tick counter
|
||||
* @return None
|
||||
* @details This function disable System Tick counter.
|
||||
*/
|
||||
void CLK_DisableSysTick(void)
|
||||
{
|
||||
SysTick->CTRL = 0; /* Set System Tick counter disabled */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enable clock source
|
||||
* @param[in] u32ClkMask is clock source mask. Including :
|
||||
* - \ref CLK_PWRCTL_XTLEN_HXT or \ref CLK_PWRCTL_XTLEN_LXT,
|
||||
* - \ref CLK_PWRCTL_LIRCEN_Msk
|
||||
* - \ref CLK_PWRCTL_HIRCEN_Msk
|
||||
* @return None
|
||||
*/
|
||||
void CLK_EnableXtalRC(uint32_t u32ClkMask)
|
||||
{
|
||||
if(u32ClkMask & CLK_PWRCTL_XTLEN_Msk)
|
||||
CLK->PWRCTL = (CLK->PWRCTL & ~CLK_PWRCTL_XTLEN_Msk) | u32ClkMask;
|
||||
else
|
||||
CLK->PWRCTL |= u32ClkMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disable clock source
|
||||
* @param[in] u32ClkMask is clock source mask. Including :
|
||||
* - \ref CLK_PWRCTL_XTLEN_Msk,
|
||||
* - \ref CLK_PWRCTL_LIRCEN_Msk,
|
||||
* - \ref CLK_PWRCTL_HIRCEN_Msk,
|
||||
* @return None
|
||||
*/
|
||||
void CLK_DisableXtalRC(uint32_t u32ClkMask)
|
||||
{
|
||||
CLK->PWRCTL &=~u32ClkMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enable module clock
|
||||
* @param[in] u32ModuleIdx is module index. Including :
|
||||
* - \ref WDT_MODULE
|
||||
* - \ref TMR0_MODULE
|
||||
* - \ref TMR1_MODULE
|
||||
* - \ref CLKO_MODULE
|
||||
* - \ref I2C0_MODULE
|
||||
* - \ref I2C1_MODULE
|
||||
* - \ref SPI0_MODULE
|
||||
* - \ref UART0_MODULE
|
||||
* - \ref UART1_MODULE
|
||||
* - \ref PWMCH01_MODULE
|
||||
* - \ref PWMCH23_MODULE
|
||||
* - \ref PWMCH45_MODULE
|
||||
* - \ref ADC_MODULE
|
||||
* - \ref ACMP_MODULE
|
||||
* - \ref WWDT_MODULE
|
||||
* @return None
|
||||
*/
|
||||
void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
|
||||
{
|
||||
*(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) |= 1<<MODULE_IP_EN_Pos(u32ModuleIdx);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disable module clock
|
||||
* @param[in] u32ModuleIdx is module index
|
||||
* - \ref WDT_MODULE
|
||||
* - \ref TMR0_MODULE
|
||||
* - \ref TMR1_MODULE
|
||||
* - \ref CLKO_MODULE
|
||||
* - \ref I2C0_MODULE
|
||||
* - \ref I2C1_MODULE
|
||||
* - \ref SPI0_MODULE
|
||||
* - \ref UART0_MODULE
|
||||
* - \ref UART1_MODULE
|
||||
* - \ref PWMCH01_MODULE
|
||||
* - \ref PWMCH23_MODULE
|
||||
* - \ref PWMCH45_MODULE
|
||||
* - \ref ADC_MODULE
|
||||
* - \ref ACMP_MODULE
|
||||
* - \ref WWDT_MODULE
|
||||
* @return None
|
||||
*/
|
||||
void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
|
||||
{
|
||||
*(volatile uint32_t *)((uint32_t)&CLK->AHBCLK+(MODULE_APBCLK(u32ModuleIdx)*4)) &= ~(1<<MODULE_IP_EN_Pos(u32ModuleIdx));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set PLL frequency
|
||||
* @param[in] u32PllClkSrc is PLL clock source. Including :
|
||||
* - \ref CLK_PLLCTL_PLLSRC_HXT
|
||||
* - \ref CLK_PLLCTL_PLLSRC_HIRC
|
||||
* @param[in] u32PllFreq is PLL frequency.
|
||||
* @return PLL frequency
|
||||
* @details This function is used to configure PLLCTL register to set specified PLL frequency.
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq)
|
||||
{
|
||||
uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32CLK_SRC , u32NRT;
|
||||
uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR,u32Best;
|
||||
|
||||
/* Disable PLL first to avoid unstable when setting PLL */
|
||||
CLK_DisablePLL();
|
||||
|
||||
/* PLL source clock is from HXT */
|
||||
if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) {
|
||||
/* Enable HXT clock */
|
||||
CLK->PWRCTL = (CLK->PWRCTL & ~CLK_PWRCTL_XTLEN_Msk) | CLK_PWRCTL_XTLEN_HXT ;
|
||||
|
||||
/* Wait for HXT clock ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_XTLSTB_Msk);
|
||||
|
||||
/* Select PLL source clock from HXT */
|
||||
u32CLK_SRC = CLK_PLLCTL_PLLSRC_HXT;
|
||||
u32PllSrcClk = __XTAL;
|
||||
|
||||
/* u32NR start from 2 */
|
||||
u32NRT = 2;
|
||||
}
|
||||
|
||||
/* PLL source clock is from HIRC */
|
||||
else {
|
||||
/* Enable HIRC clock */
|
||||
CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk;
|
||||
|
||||
/* Wait for HIRC clock ready */
|
||||
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
|
||||
|
||||
/* Select PLL source clock from HIRC */
|
||||
u32CLK_SRC = CLK_PLLCTL_PLLSRC_HIRC;
|
||||
u32PllSrcClk = __HIRC;
|
||||
|
||||
/* u32NR start from 4 when FIN = 22.1184MHz to avoid calculation overflow */
|
||||
u32NRT = 4;
|
||||
}
|
||||
|
||||
/* Select "NO" according to request frequency */
|
||||
if((u32PllFreq <= FREQ_200MHZ) && (u32PllFreq > FREQ_100MHZ)) {
|
||||
u32NO = 0;
|
||||
u32PllFreq = u32PllFreq;
|
||||
} else if((u32PllFreq <= FREQ_100MHZ) && (u32PllFreq >= FREQ_50MHZ)) {
|
||||
u32NO = 1;
|
||||
u32PllFreq = u32PllFreq << 1;
|
||||
} else if((u32PllFreq < FREQ_50MHZ) && (u32PllFreq >= FREQ_25MHZ)) {
|
||||
u32NO = 3;
|
||||
u32PllFreq = u32PllFreq << 2;
|
||||
} else {
|
||||
/* Wrong frequency request. Just return default setting. */
|
||||
goto lexit;
|
||||
}
|
||||
|
||||
/* Find best solution */
|
||||
u32Min = (uint32_t) - 1;
|
||||
u32MinNR = 0;
|
||||
u32MinNF = 0;
|
||||
for(u32NR=u32NRT; u32NR <= 33; u32NR++) {
|
||||
u32Tmp = u32PllSrcClk / u32NR;
|
||||
if((u32Tmp > 1600000) && (u32Tmp < 15000000)) {
|
||||
for(u32NF = 2; u32NF <= 513; u32NF++) {
|
||||
u32Tmp2 = u32Tmp * u32NF;
|
||||
if((u32Tmp2 >= 100000000) && (u32Tmp2 <= 200000000)) {
|
||||
u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
|
||||
if(u32Tmp3 < u32Min) {
|
||||
u32Min = u32Tmp3;
|
||||
u32MinNR = u32NR;
|
||||
u32MinNF = u32NF;
|
||||
/* Break when get good results */
|
||||
if(u32Min == 0) {
|
||||
/* Enable and apply new PLL setting. */
|
||||
CLK->PLLCTL = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2);
|
||||
|
||||
/* Wait for PLL clock stable */
|
||||
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
|
||||
|
||||
/* Return actual PLL output clock frequency */
|
||||
return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Find best solution */
|
||||
u32Best = u32Min;
|
||||
u32Min = (uint32_t) - 1;
|
||||
u32MinNR = 0;
|
||||
u32MinNF = 0;
|
||||
for(u32NR=u32NRT; u32NR <= 33; u32NR++) {
|
||||
u32Tmp = u32PllSrcClk / u32NR;
|
||||
if((u32Tmp > 1600000) && (u32Tmp < 15000000)) {
|
||||
for(u32NF = 2; u32NF <= 513; u32NF++) {
|
||||
u32Tmp2 = u32Tmp * u32NF;
|
||||
if((u32Tmp2 >= 100000000) && (u32Tmp2 <= 200000000)) {
|
||||
u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2;
|
||||
if(u32Tmp3 < u32Min) {
|
||||
u32Min = u32Tmp3;
|
||||
u32MinNR = u32NR;
|
||||
u32MinNF = u32NF;
|
||||
|
||||
/* Break when get good results */
|
||||
if(u32Min == u32Best) {
|
||||
/* Enable and apply new PLL setting. */
|
||||
CLK->PLLCTL = u32CLK_SRC | (u32NO << 14) | ((u32MinNR - 2) << 9) | (u32MinNF - 2);
|
||||
|
||||
/* Wait for PLL clock stable */
|
||||
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
|
||||
|
||||
/* Return actual PLL output clock frequency */
|
||||
return u32PllSrcClk / ((u32NO + 1) * u32MinNR) * u32MinNF;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
lexit:
|
||||
|
||||
/* Apply default PLL setting and return */
|
||||
if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT)
|
||||
CLK->PLLCTL = CLK_PLLCTL_72MHz_HXT; /* 72MHz */
|
||||
else
|
||||
CLK->PLLCTL = CLK_PLLCTL_72MHz_HIRC; /* 71.8848MHz */
|
||||
|
||||
/* Wait for PLL clock stable */
|
||||
CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk);
|
||||
|
||||
return CLK_GetPLLClockFreq();
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable PLL
|
||||
* @param None
|
||||
* @return None
|
||||
* @details This function set PLL in Power-down mode.
|
||||
* The register write-protection function should be disabled before using this function.
|
||||
*/
|
||||
void CLK_DisablePLL(void)
|
||||
{
|
||||
CLK->PLLCTL |= CLK_PLLCTL_PD_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function execute delay function.
|
||||
* @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
|
||||
* 50MHz => 335544us, 48MHz => 349525us, 28MHz => 699050us ...
|
||||
* @return None
|
||||
* @details Use the SysTick to generate the delay time and the UNIT is in us.
|
||||
* The SysTick clock source is from HCLK, i.e the same as system core clock.
|
||||
*/
|
||||
void CLK_SysTickDelay(uint32_t us)
|
||||
{
|
||||
SysTick->LOAD = us * CyclesPerUs;
|
||||
SysTick->VAL = (0x00);
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
|
||||
|
||||
/* Waiting for down-count to zero */
|
||||
while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
|
||||
SysTick->CTRL = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function check selected clock source status
|
||||
* @param[in] u32ClkMask is selected clock source. Including
|
||||
* - \ref CLK_STATUS_CLKSFAIL_Msk
|
||||
* - \ref CLK_STATUS_HIRCSTB_Msk
|
||||
* - \ref CLK_STATUS_LIRCSTB_Msk
|
||||
* - \ref CLK_STATUS_XTLSTB_Msk
|
||||
*
|
||||
* @return 0 clock is not stable
|
||||
* 1 clock is stable
|
||||
*
|
||||
* @details To wait for clock ready by specified CLKSTATUS bit or timeout (~5ms)
|
||||
*/
|
||||
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask)
|
||||
{
|
||||
int32_t i32TimeOutCnt = 2160000;
|
||||
|
||||
while((CLK->STATUS & u32ClkMask) != u32ClkMask) {
|
||||
if(i32TimeOutCnt-- <= 0)
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_CLK_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_CLK_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,310 @@
|
||||
/**************************************************************************//**
|
||||
* @file fmc.c
|
||||
* @version V1.00
|
||||
* $Revision: 6 $
|
||||
* $Date: 15/05/26 6:31p $
|
||||
* @brief Mini58 series FMC driver source file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
|
||||
//* Includes ------------------------------------------------------------------*/
|
||||
#include <stdio.h>
|
||||
#include "Mini58Series.h"
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_FMC_Driver FMC Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Mini58_FMC_EXPORTED_FUNCTIONS FMC Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable all FMC functions
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void FMC_Close(void)
|
||||
{
|
||||
FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Erase a page. The page size is 512 bytes.
|
||||
* @param[in] u32PageAddr Flash page address. Must be a 512-byte aligned address.
|
||||
* @retval 0 Success
|
||||
* @retval -1 Erase failed
|
||||
*/
|
||||
int32_t FMC_Erase(uint32_t u32PageAddr)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
|
||||
FMC->ISPADDR = u32PageAddr;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
|
||||
|
||||
if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) {
|
||||
FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief get the current boot source
|
||||
* @retval 0 This chip is currently booting from APROM
|
||||
* @retval 1 This chip is currently booting from LDROM
|
||||
*/
|
||||
int32_t FMC_GetBootSource (void)
|
||||
{
|
||||
if (FMC->ISPCTL & FMC_ISPCTL_BS_Msk)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable FMC ISP function
|
||||
*/
|
||||
void FMC_Open(void)
|
||||
{
|
||||
FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Read a word from specified flash address.
|
||||
* @param[in] u32Addr Flash word address. Must be a word aligned address.
|
||||
* @return The word data stored in the flash address "u32Addr".
|
||||
*/
|
||||
uint32_t FMC_Read(uint32_t u32Addr)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ;
|
||||
FMC->ISPADDR = u32Addr;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
|
||||
|
||||
return FMC->ISPDAT;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Read company ID.
|
||||
* @return The company ID.
|
||||
*/
|
||||
uint32_t FMC_ReadCID(void)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ_CID;
|
||||
FMC->ISPADDR = 0x0;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
|
||||
return FMC->ISPDAT;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Read product ID.
|
||||
* @return The product ID.
|
||||
*/
|
||||
uint32_t FMC_ReadPID(void)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ_PID;
|
||||
FMC->ISPADDR = 0x04;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
|
||||
return FMC->ISPDAT;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function reads one of the four UCID.
|
||||
* @param[in] u32Index index of the UCID to read. u32Index must be 0, 1, 2, or 3.
|
||||
* @return The UCID.
|
||||
*/
|
||||
uint32_t FMC_ReadUCID(uint32_t u32Index)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ_UID;
|
||||
FMC->ISPADDR = (0x04 * u32Index) + 0x10;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
|
||||
|
||||
return FMC->ISPDAT;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function reads one of the three UID.
|
||||
* @param[in] u32Index Index of the UID to read. u32Index must be 0, 1, or 2.
|
||||
* @return The UID.
|
||||
*/
|
||||
uint32_t FMC_ReadUID(uint32_t u32Index)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ_UID;
|
||||
FMC->ISPADDR = 0x04 * u32Index;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
|
||||
|
||||
return FMC->ISPDAT;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get the base address of Data Flash if enabled.
|
||||
* @return The base address of Data Flash
|
||||
*/
|
||||
uint32_t FMC_ReadDataFlashBaseAddr(void)
|
||||
{
|
||||
return FMC->DFBA;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function will force re-map assigned flash page to CPU address 0x0.
|
||||
* @param[in] u32PageAddr Address of the page to be mapped to CPU address 0x0.
|
||||
* @return None
|
||||
*/
|
||||
void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_VECMAP;
|
||||
FMC->ISPADDR = u32PageAddr;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Obtain the current vector page address setting.
|
||||
* @return The vector page address.
|
||||
*/
|
||||
uint32_t FMC_GetVectorPageAddr(void)
|
||||
{
|
||||
return (FMC->ISPSTS & 0x0FFFFF00ul);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Writes a word data to specified flash address.
|
||||
* @param[in] u32Addr Destination address
|
||||
* @param[in] u32Data Word data to be written
|
||||
* @return None
|
||||
*/
|
||||
void FMC_Write(uint32_t u32Addr, uint32_t u32Data)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
|
||||
FMC->ISPADDR = u32Addr;
|
||||
FMC->ISPDAT = u32Data;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Read the User Configuration words.
|
||||
* @param[in] u32Config The word array to store data.
|
||||
* @param[in] u32Count Maximum length of "u32Config".
|
||||
* @retval 0 Success
|
||||
* @retval -1 Failed
|
||||
*/
|
||||
int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count)
|
||||
{
|
||||
if (u32Count < 1)
|
||||
return 0;
|
||||
|
||||
u32Config[0] = FMC_Read(FMC_CONFIG_BASE);
|
||||
if (u32Count < 2)
|
||||
return 0;
|
||||
|
||||
u32Config[1] = FMC_Read(FMC_CONFIG_BASE+4);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write User Configuration
|
||||
* @param[in] u32Config The word array to store data.
|
||||
* @param[in] u32Count Maximum length of "u32Config".
|
||||
* @retval 0 Success
|
||||
* @retval -1 Failed
|
||||
*/
|
||||
int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count)
|
||||
{
|
||||
if (u32Count < 1)
|
||||
return 0;
|
||||
|
||||
FMC_ENABLE_CFG_UPDATE();
|
||||
FMC_Erase(FMC_CONFIG_BASE);
|
||||
FMC_Write(FMC_CONFIG_BASE, u32Config[0]);
|
||||
|
||||
if (u32Count < 2)
|
||||
return 0;
|
||||
|
||||
FMC_Write(FMC_CONFIG_BASE+4, u32Config[1]);
|
||||
FMC_DISABLE_CFG_UPDATE();
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Calculate and read the CRC32 checksum of a specified flash area.
|
||||
* @param[in] addr Start address of the flash area to be executed CRC32 checksum calculation.
|
||||
* @param[in] count Number of bytes to be calculated.
|
||||
* @param[out] chksum If success, it will contain the result of CRC32 checksum calculation.
|
||||
* @retval 0 Success
|
||||
* @retval -1 Invalid parameter.
|
||||
*/
|
||||
int32_t FMC_GetCRC32Sum(uint32_t addr, uint32_t count, uint32_t *chksum)
|
||||
{
|
||||
FMC->ISPCMD = FMC_ISPCMD_CAL_CRC32;
|
||||
FMC->ISPADDR = addr;
|
||||
FMC->ISPDAT = count;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
|
||||
|
||||
if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) {
|
||||
FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
|
||||
return -1;
|
||||
}
|
||||
|
||||
FMC->ISPCMD = FMC_ISPCMD_READ_CRC32;
|
||||
FMC->ISPADDR = addr;
|
||||
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||
|
||||
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ;
|
||||
|
||||
if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) {
|
||||
FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
|
||||
return -1;
|
||||
}
|
||||
|
||||
*chksum = FMC->ISPDAT;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_FMC_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_FMC_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
|
||||
|
||||
@@ -0,0 +1,101 @@
|
||||
/**************************************************************************//**
|
||||
* @file gpio.c
|
||||
* @version V1.00
|
||||
* $Revision: 1 $
|
||||
* $Date: 15/02/02 3:19p $
|
||||
* @brief Mini58 series GPIO driver source file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "Mini58Series.h"
|
||||
|
||||
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_GPIO_Driver GPIO Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Mini58_GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Set GPIO operation mode
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \ref BIT0, \ref BIT1, \ref BIT2,.. \ref BIT7
|
||||
* @param[in] u32Mode Operation mode.
|
||||
* - \ref GPIO_MODE_INPUT,
|
||||
* - \ref GPIO_MODE_OUTPUT,
|
||||
* - \ref GPIO_MODE_OPEN_DRAIN,
|
||||
* - \ref GPIO_MODE_QUASI
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to set specified GPIO operation mode.
|
||||
*/
|
||||
void GPIO_SetMode(GPIO_T *gpio, uint32_t u32PinMask, uint32_t u32Mode)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i=0; i<GPIO_PIN_MAX; i++) {
|
||||
if (u32PinMask & (1 << i)) {
|
||||
gpio->MODE = (gpio->MODE & ~(0x3 << (i << 1))) | (u32Mode << (i << 1));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable GPIO interrupt
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
|
||||
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be \n
|
||||
* - \ref GPIO_INT_RISING,
|
||||
* - \ref GPIO_INT_FALLING,
|
||||
* - \ref GPIO_INT_BOTH_EDGE,
|
||||
* - \ref GPIO_INT_HIGH,
|
||||
* - \ref GPIO_INT_LOW.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
*/
|
||||
void GPIO_EnableInt(GPIO_T *gpio, uint32_t u32Pin, uint32_t u32IntAttribs)
|
||||
{
|
||||
gpio->INTTYPE |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
|
||||
gpio->INTEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Disable GPIO interrupt
|
||||
*
|
||||
* @param[in] gpio GPIO port. It could be \ref P0, \ref P1, \ref P2, \ref P3, \ref P4 or \ref P5.
|
||||
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 7.
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
* @details This function is used to enable specified GPIO pin interrupt.
|
||||
*/
|
||||
void GPIO_DisableInt(GPIO_T *gpio, uint32_t u32Pin)
|
||||
{
|
||||
gpio->INTTYPE &= ~(1UL << u32Pin);
|
||||
gpio->INTEN &= ~((0x00010001UL) << u32Pin);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_GPIO_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_GPIO_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,300 @@
|
||||
/**************************************************************************//**
|
||||
* @file i2c.c
|
||||
* @version V1.00
|
||||
* $Revision: 5 $
|
||||
* $Date: 15/05/26 4:24p $
|
||||
* @brief Mini58 series I2C driver source file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "Mini58Series.h"
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_I2C_Driver I2C Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Mini58_I2C_EXPORTED_FUNCTIONS I2C Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function make I2C module be ready and set the wanted bus clock.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @param[in] u32BusClock is the target bus speed of I2C module.
|
||||
* @return Actual I2C bus clock frequency.
|
||||
*/
|
||||
uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
|
||||
{
|
||||
uint32_t u32Div;
|
||||
|
||||
u32Div = (uint32_t) (((SystemCoreClock * 10)/(u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
|
||||
i2c->CLKDIV = u32Div;
|
||||
|
||||
/* Enable I2C */
|
||||
i2c->CTL |= I2C_CTL_I2CEN_Msk;
|
||||
|
||||
return ( SystemCoreClock / ((u32Div+1)<<2) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function closes the I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
void I2C_Close(I2C_T *i2c)
|
||||
{
|
||||
/* Reset SPI */
|
||||
if(i2c == I2C0) {
|
||||
SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk;
|
||||
SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk;
|
||||
} else {
|
||||
SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk;
|
||||
SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk;
|
||||
}
|
||||
|
||||
/* Disable I2C */
|
||||
i2c->CTL &= ~I2C_CTL_I2CEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function clears the timeout flag.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
void I2C_ClearTimeoutFlag(I2C_T *i2c)
|
||||
{
|
||||
i2c->TOCTL |= I2C_TOCTL_TOIF_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function sets the control bit of the I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @param[in] u8Start sets START bit to I2C module.
|
||||
* @param[in] u8Stop sets STOP bit to I2C module.
|
||||
* @param[in] u8Si sets SI bit to I2C module.
|
||||
* @param[in] u8Ack sets ACK bit to I2C module.
|
||||
* @return none
|
||||
*/
|
||||
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack)
|
||||
{
|
||||
uint32_t u32Reg = 0;
|
||||
|
||||
if (u8Start)
|
||||
u32Reg |= I2C_STA;
|
||||
if (u8Stop)
|
||||
u32Reg |= I2C_STO;
|
||||
if (u8Si)
|
||||
u32Reg |= I2C_SI;
|
||||
if (u8Ack)
|
||||
u32Reg |= I2C_AA;
|
||||
|
||||
i2c->CTL = (i2c->CTL & ~0x3C) | u32Reg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disables the interrupt (EI bit) of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
void I2C_DisableInt(I2C_T *i2c)
|
||||
{
|
||||
i2c->CTL &= ~I2C_CTL_INTEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enables the interrupt (EI bit) of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
void I2C_EnableInt(I2C_T *i2c)
|
||||
{
|
||||
i2c->CTL |= I2C_CTL_INTEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function returns the real bus clock of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return Actual I2C bus clock frequency.
|
||||
*/
|
||||
uint32_t I2C_GetBusClockFreq(I2C_T *i2c)
|
||||
{
|
||||
uint32_t u32Divider = i2c->CLKDIV;
|
||||
|
||||
return ( SystemCoreClock / ((u32Divider+1)<<2) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enables the interrupt (EI bit) of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @param[in] u32BusClock is the target bus speed of I2C module.
|
||||
* @return Actual I2C bus clock frequency.
|
||||
*/
|
||||
uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock)
|
||||
{
|
||||
uint32_t u32Div;
|
||||
|
||||
u32Div = (uint32_t) (((SystemCoreClock * 10)/(u32BusClock * 4) + 5) / 10 - 1); /* Compute proper divider for I2C clock */
|
||||
i2c->CLKDIV = u32Div;
|
||||
|
||||
return ( SystemCoreClock / ((u32Div+1)<<2) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function gets the interrupt flag (SI bit) of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return Interrupt flag.
|
||||
* @retval 0 Flag is not set.
|
||||
* @retval 1 Flag is set.
|
||||
*/
|
||||
uint32_t I2C_GetIntFlag(I2C_T *i2c)
|
||||
{
|
||||
return ( (i2c->CTL & I2C_CTL_SI_Msk) == I2C_CTL_SI_Msk ? 1:0 );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function returns the status of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return Status.
|
||||
*/
|
||||
uint32_t I2C_GetStatus(I2C_T *i2c)
|
||||
{
|
||||
return ( i2c->STATUS );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function returns the data stored in data register of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return Data.
|
||||
*/
|
||||
uint32_t I2C_GetData(I2C_T *i2c)
|
||||
{
|
||||
return ( i2c->DAT );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function writes the data to data register of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @param[in] u8Data is the data which will be write to data register of I2C module.
|
||||
* @return none
|
||||
*/
|
||||
void I2C_SetData(I2C_T *i2c, uint8_t u8Data)
|
||||
{
|
||||
i2c->DAT = u8Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure slave address and enable GC mode.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @param[in] u8SlaveNo is the set number of salve address.
|
||||
* @param[in] u8SlaveAddr is the slave address.
|
||||
* @param[in] u8GCMode enable GC mode.
|
||||
* @return none
|
||||
*/
|
||||
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode)
|
||||
{
|
||||
switch (u8SlaveNo) {
|
||||
case 0:
|
||||
i2c->ADDR0 = (u8SlaveAddr << 1) | u8GCMode;
|
||||
break;
|
||||
case 1:
|
||||
i2c->ADDR1 = (u8SlaveAddr << 1) | u8GCMode;
|
||||
break;
|
||||
case 2:
|
||||
i2c->ADDR2 = (u8SlaveAddr << 1) | u8GCMode;
|
||||
break;
|
||||
case 3:
|
||||
i2c->ADDR3 = (u8SlaveAddr << 1) | u8GCMode;
|
||||
break;
|
||||
default:
|
||||
i2c->ADDR0 = (u8SlaveAddr << 1) | u8GCMode;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the mask of slave address. The corresponding address bit is "Don't Care".
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @param[in] u8SlaveNo is the set number of salve address.
|
||||
* @param[in] u8SlaveAddrMask is the slave address mask.
|
||||
* @return none
|
||||
*/
|
||||
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask)
|
||||
{
|
||||
switch (u8SlaveNo) {
|
||||
case 0:
|
||||
i2c->ADDRMSK0 = u8SlaveAddrMask << 1;
|
||||
break;
|
||||
case 1:
|
||||
i2c->ADDRMSK1 = u8SlaveAddrMask << 1;
|
||||
break;
|
||||
case 2:
|
||||
i2c->ADDRMSK2 = u8SlaveAddrMask << 1;
|
||||
break;
|
||||
case 3:
|
||||
i2c->ADDRMSK3 = u8SlaveAddrMask << 1;
|
||||
break;
|
||||
default:
|
||||
i2c->ADDRMSK0 = u8SlaveAddrMask << 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enables timeout function and configures DIV4 function to support long timeout.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @param[in] u8LongTimeout Enable timeout counter input clock is divide by 4.
|
||||
* @return none.
|
||||
*/
|
||||
void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout)
|
||||
{
|
||||
if(u8LongTimeout)
|
||||
i2c->TOCTL |= I2C_TOCTL_TOCURIEN_Msk;
|
||||
else
|
||||
i2c->TOCTL &= ~I2C_TOCTL_TOCURIEN_Msk;
|
||||
|
||||
i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disables timeout function.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none.
|
||||
*/
|
||||
void I2C_DisableTimeout(I2C_T *i2c)
|
||||
{
|
||||
i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enables the wakeup function of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none.
|
||||
*/
|
||||
void I2C_EnableWakeup(I2C_T *i2c)
|
||||
{
|
||||
if(i2c == I2C0) //only support for port0
|
||||
i2c->CTL1 |= I2C_CTL1_WKEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disables the wakeup function of I2C module.
|
||||
* @param[in] i2c is the base address of I2C module.
|
||||
* @return none.
|
||||
*/
|
||||
void I2C_DisableWakeup(I2C_T *i2c)
|
||||
{
|
||||
if(i2c == I2C0) //only support for port0
|
||||
i2c->CTL1 &= ~I2C_CTL1_WKEN_Msk;
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group Mini58_I2C_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_I2C_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,573 @@
|
||||
/**************************************************************************//**
|
||||
* @file PWM.c
|
||||
* @version V1.00
|
||||
* $Revision: 4 $
|
||||
* $Date: 15/06/05 1:43p $
|
||||
* @brief Mini58 series PWM driver source file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "Mini58Series.h"
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_PWM_Driver PWM Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Mini58_PWM_EXPORTED_FUNCTIONS PWM Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function config PWM generator and get the nearest frequency in edge aligned auto-reload mode
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Frequency Target generator frequency
|
||||
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
|
||||
* @return Nearest frequency clock in nano second
|
||||
* @note Since every two channels, (0 & 1), (2 & 3), (4 & 5), shares a prescaler. Call this API to configure PWM frequency may affect
|
||||
* existing frequency of other channel.
|
||||
*/
|
||||
uint32_t PWM_ConfigOutputChannel (PWM_T *pwm,
|
||||
uint32_t u32ChannelNum,
|
||||
uint32_t u32Frequency,
|
||||
uint32_t u32DutyCycle)
|
||||
{
|
||||
uint32_t i = SystemCoreClock / u32Frequency;
|
||||
uint8_t u8Divider = 1, u8Prescale = 0xFF;
|
||||
uint16_t u16CNR = 0xFFFF;
|
||||
|
||||
for(; u8Divider < 17; u8Divider <<= 1) { // clk divider could only be 1, 2, 4, 8, 16
|
||||
i = (SystemCoreClock / u32Frequency) / u8Divider;
|
||||
// If target value is larger than CNR * prescale, need to use a larger divider
|
||||
if(i > (0x10000 * 0x100))
|
||||
continue;
|
||||
|
||||
// CNR = 0xFFFF + 1, get a prescaler that CNR value is below 0xFFFF
|
||||
u8Prescale = (i + 0xFFFF)/ 0x10000;
|
||||
|
||||
// u8Prescale must at least be 2, otherwise the output stop
|
||||
if(u8Prescale < 3)
|
||||
u8Prescale = 2;
|
||||
|
||||
i /= u8Prescale;
|
||||
|
||||
if(i <= 0x10000) {
|
||||
if(i == 1)
|
||||
u16CNR = 1; // Too fast, and PWM cannot generate expected frequency...
|
||||
else
|
||||
u16CNR = i;
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
// Store return value here 'cos we're gonna change u8Divider & u8Prescale & u16CNR to the real value to fill into register
|
||||
i = SystemCoreClock / (u8Prescale * u8Divider * u16CNR);
|
||||
|
||||
u8Prescale -= 1;
|
||||
u16CNR -= 1;
|
||||
// convert to real register value
|
||||
if(u8Divider == 1)
|
||||
u8Divider = 4;
|
||||
else if (u8Divider == 2)
|
||||
u8Divider = 0;
|
||||
else if (u8Divider == 4)
|
||||
u8Divider = 1;
|
||||
else if (u8Divider == 8)
|
||||
u8Divider = 2;
|
||||
else // 16
|
||||
u8Divider = 3;
|
||||
|
||||
// every two channels share a prescaler
|
||||
PWM->CLKPSC = (PWM->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << ((u32ChannelNum >> 1) * 8))) | (u8Prescale << ((u32ChannelNum >> 1) * 8));
|
||||
PWM->CLKDIV = (PWM->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << (4 * u32ChannelNum))) | (u8Divider << (4 * u32ChannelNum));
|
||||
PWM->CTL = (PWM->CTL & ~PWM_CTL_CNTTYPE_Msk) | (PWM_CTL_CNTMODE0_Msk << ((4 * u32ChannelNum)));
|
||||
|
||||
if(u32DutyCycle == 0)
|
||||
*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4))) = 0;
|
||||
else
|
||||
*((__IO uint32_t *)((((uint32_t) & ((pwm)->CMPDAT0)) + u32ChannelNum * 4))) = u32DutyCycle * (u16CNR + 1) / 100 - 1;
|
||||
|
||||
*((__IO uint32_t *)((((uint32_t) & ((pwm)->PERIOD0)) + (u32ChannelNum) * 4))) = u16CNR;
|
||||
|
||||
return(i);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function start PWM module
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
|
||||
* Bit 0 is channel 0, bit 1 is channel 1...
|
||||
* @return None
|
||||
*/
|
||||
void PWM_Start (PWM_T *pwm, uint32_t u32ChannelMask)
|
||||
{
|
||||
uint32_t u32Mask = 0, i;
|
||||
for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
|
||||
if(u32ChannelMask & (1 << i)) {
|
||||
u32Mask |= (PWM_CTL_CNTEN0_Msk << (i * 4));
|
||||
}
|
||||
}
|
||||
|
||||
PWM->CTL |= u32Mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function stop PWM module
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
|
||||
* Bit 0 is channel 0, bit 1 is channel 1...
|
||||
* @return None
|
||||
*/
|
||||
void PWM_Stop (PWM_T *pwm, uint32_t u32ChannelMask)
|
||||
{
|
||||
uint32_t i;
|
||||
for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
|
||||
if(u32ChannelMask & (1 << i)) {
|
||||
*((__IO uint32_t *)((((uint32_t) & ((pwm)->PERIOD0)) + (i) * 4))) = 0;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function stop PWM generation immediately by clear channel enable bit
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
|
||||
* Bit 0 is channel 0, bit 1 is channel 1...
|
||||
* @return None
|
||||
*/
|
||||
void PWM_ForceStop (PWM_T *pwm, uint32_t u32ChannelMask)
|
||||
{
|
||||
uint32_t u32Mask = 0, i;
|
||||
for(i = 0; i < PWM_CHANNEL_NUM; i ++) {
|
||||
if(u32ChannelMask & (1 << i)) {
|
||||
u32Mask |= (PWM_CTL_CNTEN0_Msk << (i * 4));
|
||||
}
|
||||
}
|
||||
|
||||
PWM->CTL &= ~u32Mask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enable selected channel to trigger ADC
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
|
||||
* - \ref PWM_TRIGGER_ADC_CNTR_IS_0
|
||||
* - \ref PWM_TRIGGER_ADC_CNTR_IS_CMR_D
|
||||
* - \ref PWM_TRIGGER_ADC_CNTR_IS_CNR
|
||||
* - \ref PWM_TRIGGER_ADC_CNTR_IS_CMR_U
|
||||
* @return None
|
||||
*/
|
||||
void PWM_EnableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
|
||||
{
|
||||
if(u32ChannelNum < 4) {
|
||||
PWM->ADCTCTL0 = (PWM->ADCTCTL0 & ~((PWM_TRIGGER_ADC_CNTR_IS_0 |
|
||||
PWM_TRIGGER_ADC_CNTR_IS_CMR_D |
|
||||
PWM_TRIGGER_ADC_CNTR_IS_CNR |
|
||||
PWM_TRIGGER_ADC_CNTR_IS_CMR_U ) << (8 * u32ChannelNum))) | (u32Condition << (8 * u32ChannelNum));
|
||||
} else {
|
||||
PWM->ADCTCTL1 = (PWM->ADCTCTL1 & ~((PWM_TRIGGER_ADC_CNTR_IS_0 |
|
||||
PWM_TRIGGER_ADC_CNTR_IS_CMR_D |
|
||||
PWM_TRIGGER_ADC_CNTR_IS_CNR |
|
||||
PWM_TRIGGER_ADC_CNTR_IS_CMR_U ) << (8 * (u32ChannelNum - 4)))) | (u32Condition << (8 * (u32ChannelNum - 4)));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disable selected channel to trigger ADC
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
*/
|
||||
void PWM_DisableADCTrigger (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
if(u32ChannelNum < 4) {
|
||||
PWM->ADCTCTL0 = (PWM->ADCTCTL0 & ~((PWM_TRIGGER_ADC_CNTR_IS_0 |
|
||||
PWM_TRIGGER_ADC_CNTR_IS_CMR_D |
|
||||
PWM_TRIGGER_ADC_CNTR_IS_CNR |
|
||||
PWM_TRIGGER_ADC_CNTR_IS_CMR_U ) << (8 * u32ChannelNum)));
|
||||
} else {
|
||||
PWM->ADCTCTL1 = (PWM->ADCTCTL1 & ~((PWM_TRIGGER_ADC_CNTR_IS_0 |
|
||||
PWM_TRIGGER_ADC_CNTR_IS_CMR_D |
|
||||
PWM_TRIGGER_ADC_CNTR_IS_CNR |
|
||||
PWM_TRIGGER_ADC_CNTR_IS_CMR_U ) << (8 * (u32ChannelNum - 4))));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function clear selected channel trigger ADC flag
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Condition PWM triggered ADC flag to be cleared.
|
||||
* @return None
|
||||
*/
|
||||
void PWM_ClearADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
|
||||
{
|
||||
if(u32ChannelNum < 4) {
|
||||
PWM->ADCTSTS0 |= (u32Condition << (8 * u32ChannelNum));
|
||||
} else {
|
||||
PWM->ADCTSTS1 |= (u32Condition << (8 * (u32ChannelNum - 4)));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function get selected channel trigger ADC flag
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Condition PWM triggered ADC flag to be selected.
|
||||
* @return Get status of the selected channel trigger ADC
|
||||
*/
|
||||
uint32_t PWM_GetADCTriggerFlag (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition)
|
||||
{
|
||||
if(u32ChannelNum < 4) {
|
||||
return(PWM->ADCTSTS0 & (u32Condition << (8 * u32ChannelNum)) ? 1 : 0);
|
||||
} else {
|
||||
return(PWM->ADCTSTS1 & (u32Condition << (8 * (u32ChannelNum - 4))) ? 1 : 0);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enable fault brake of selected channels
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelMask This parameter is not used
|
||||
* @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel
|
||||
* while fault brake occur. Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||
* , bit 6 represent D6, and bit 7 represents D7
|
||||
* @param[in] u32BrakeSource Fault brake source, could be one of following source
|
||||
* - \ref PWM_FB0_EINT0
|
||||
* - \ref PWM_FB0_ACMP1
|
||||
* - \ref PWM_FB1_EINT1
|
||||
* - \ref PWM_FB1_ACMP0
|
||||
* @return None
|
||||
*/
|
||||
void PWM_EnableFaultBrake (PWM_T *pwm,
|
||||
uint32_t u32ChannelMask,
|
||||
uint32_t u32LevelMask,
|
||||
uint32_t u32BrakeSource)
|
||||
{
|
||||
PWM->BRKCTL = (u32LevelMask << PWM_BRKCTL_BKOD0_Pos) | u32BrakeSource;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function clear fault brake flag
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32BrakeSource This parameter is not used
|
||||
* @return None
|
||||
* @note After fault brake occurred, application must clear fault brake source before re-enable PWM output
|
||||
*/
|
||||
void PWM_ClearFaultBrakeFlag (PWM_T *pwm, uint32_t u32BrakeSource)
|
||||
{
|
||||
PWM->BRKCTL = PWM_BRKCTL_BRKSTS_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enables PWM output generation of selected channels
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
|
||||
* Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
|
||||
* @return None
|
||||
*/
|
||||
void PWM_EnableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
|
||||
{
|
||||
PWM->POEN |= u32ChannelMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disables PWM output generation of selected channels
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||
* Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
|
||||
* @return None
|
||||
*/
|
||||
void PWM_DisableOutput (PWM_T *pwm, uint32_t u32ChannelMask)
|
||||
{
|
||||
PWM->POEN &= ~u32ChannelMask;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enable Dead zone of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32Duration Dead Zone length in PWM clock count, valid values are between 0~0xFF, but 0 means there is no
|
||||
* dead zone.
|
||||
* @return None
|
||||
*/
|
||||
void PWM_EnableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration)
|
||||
{
|
||||
// every two channels shares the same setting
|
||||
u32ChannelNum >>= 1;
|
||||
// set duration
|
||||
PWM->DTCTL = (PWM->DTCTL & ~(PWM_DTCTL_DTI01_Msk << (8 * u32ChannelNum))) | (u32Duration << (8 * u32ChannelNum));
|
||||
// enable dead zone
|
||||
PWM->CTL |= (PWM_CTL_DTCNT01_Msk << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disable Dead zone of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
*/
|
||||
void PWM_DisableDeadZone (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
// every two channels shares the same setting
|
||||
u32ChannelNum >>= 1;
|
||||
// enable dead zone
|
||||
PWM->CTL &= ~(PWM_CTL_DTCNT01_Msk << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enable duty interrupt of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32IntDutyType This parameter is not used
|
||||
* @return None
|
||||
*/
|
||||
void PWM_EnableDutyInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
|
||||
{
|
||||
(pwm)->INTEN |= ((1 << PWM_INTEN_CMPDIEN0_Pos) << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disable duty interrupt of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
*/
|
||||
void PWM_DisableDutyInt (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
(pwm)->INTEN &= ~((1 << PWM_INTEN_CMPDIEN0_Pos) << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function clears duty interrupt flag of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
*/
|
||||
void PWM_ClearDutyIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
PWM->INTSTS = (PWM_INTSTS_CMPDIF0_Msk << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function get duty interrupt flag of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return Duty interrupt flag of specified channel
|
||||
* @retval 0 Duty interrupt did not occurred
|
||||
* @retval 1 Duty interrupt occurred
|
||||
*/
|
||||
uint32_t PWM_GetDutyIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
return(PWM->INTSTS & (PWM_INTSTS_CMPDIF0_Msk << u32ChannelNum) ? 1 : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enable Period interrupt of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
*/
|
||||
void PWM_EnablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
(pwm)->INTEN |= ((1 << PWM_INTEN_ZIEN0_Pos) << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disable Period interrupt of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
*/
|
||||
void PWM_DisablePeriodInt (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
(pwm)->INTEN &= ~((1 << PWM_INTEN_ZIEN0_Pos) << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function clears Period interrupt flag of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
*/
|
||||
void PWM_ClearPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
PWM->INTSTS = (PWM_INTSTS_ZIF0_Msk << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function get Period interrupt flag of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return Period interrupt flag of specified channel
|
||||
* @retval 0 Period interrupt did not occurred
|
||||
* @retval 1 Period interrupt occurred
|
||||
*/
|
||||
uint32_t PWM_GetPeriodIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
return(PWM->INTSTS & (PWM_INTSTS_ZIF0_Msk << u32ChannelNum) ? 1 : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enable Rise interrupt of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
*/
|
||||
void PWM_EnableRiseInt (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
(pwm)->INTEN |= ((1 << PWM_INTEN_CMPUIEN0_Pos) << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disable Rise interrupt of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
*/
|
||||
void PWM_DisableRiseInt (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
(pwm)->INTEN &= ~((1 << PWM_INTEN_CMPUIEN0_Pos) << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function clears Rise interrupt flag of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
*/
|
||||
void PWM_ClearRiseIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
PWM->INTSTS = (PWM_INTSTS_CMPUIF0_Msk << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function get Rise interrupt flag of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return Rise interrupt flag of specified channel
|
||||
* @retval 0 Rise interrupt did not occurred
|
||||
* @retval 1 Rise interrupt occurred
|
||||
*/
|
||||
uint32_t PWM_GetRiseIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
return(PWM->INTSTS & (PWM_INTSTS_CMPUIF0_Msk << u32ChannelNum) ? 1 : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enable fault brake interrupt
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32BrakeSource This parameter is not used
|
||||
* @return None
|
||||
*/
|
||||
void PWM_EnableFaultBrakeInt (PWM_T *pwm, uint32_t u32BrakeSource)
|
||||
{
|
||||
PWM->INTEN |= PWM_INTEN_BRKIEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disable fault brake interrupt
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32BrakeSource This parameter is not used
|
||||
* @return None
|
||||
*/
|
||||
void PWM_DisableFaultBrakeInt (PWM_T *pwm, uint32_t u32BrakeSource)
|
||||
{
|
||||
PWM->INTEN &= ~PWM_INTEN_BRKIEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function clear fault brake interrupt of selected source
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32BrakeSource Fault brake source, could be either
|
||||
* - \ref PWM_INTSTS_BRKIF0_Msk, or
|
||||
* - \ref PWM_INTSTS_BRKIF1_Msk
|
||||
* @return None
|
||||
*/
|
||||
void PWM_ClearFaultBrakeIntFlag (PWM_T *pwm, uint32_t u32BrakeSource)
|
||||
{
|
||||
PWM->INTSTS = u32BrakeSource;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function get fault brake interrupt of selected source
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32BrakeSource Fault brake source, could be either
|
||||
* - \ref PWM_INTSTS_BRKIF0_Msk, or
|
||||
* - \ref PWM_INTSTS_BRKIF1_Msk
|
||||
* @return Fault brake interrupt flag of specified source
|
||||
* @retval 0 Fault brake interrupt did not occurred
|
||||
* @retval 1 Fault brake interrupt occurred
|
||||
*/
|
||||
uint32_t PWM_GetFaultBrakeIntFlag (PWM_T *pwm, uint32_t u32BrakeSource)
|
||||
{
|
||||
return (PWM->INTSTS & u32BrakeSource ? 1 : 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enable Central interrupt of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @param[in] u32IntPeriodType Period interrupt type, could be either
|
||||
* - \ref PWM_PERIOD_INT_UNDERFLOW
|
||||
* - \ref PWM_PERIOD_INT_MATCH_CNR
|
||||
* @return None
|
||||
* @note All channels share the same Central interrupt type setting.
|
||||
*/
|
||||
void PWM_EnableCenterInt (PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
|
||||
{
|
||||
PWM->INTEN = (PWM->INTEN & ~PWM_INTEN_PINTTYPE_Msk & ~(PWM_INTEN_PIEN0_Msk << u32ChannelNum)) | (PWM_INTEN_PIEN0_Msk << u32ChannelNum) | u32IntPeriodType;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disable Central interrupt of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
*/
|
||||
void PWM_DisableCenterInt (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
PWM->INTEN &= ~(PWM_INTEN_PIEN0_Msk << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function clear Central interrupt of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return None
|
||||
*/
|
||||
void PWM_ClearCenterIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
PWM->INTSTS = (PWM_INTSTS_PIF0_Msk << u32ChannelNum);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function get Central interrupt of selected channel
|
||||
* @param[in] pwm The base address of PWM module
|
||||
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||
* @return Central interrupt flag of specified channel
|
||||
* @retval 0 Central interrupt did not occurred
|
||||
* @retval 1 Central interrupt occurred
|
||||
*/
|
||||
uint32_t PWM_GetCenterIntFlag (PWM_T *pwm, uint32_t u32ChannelNum)
|
||||
{
|
||||
return(PWM->INTSTS & (PWM_INTSTS_PIF0_Msk << u32ChannelNum) ? 1 : 0);
|
||||
}
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_PWM_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_PWM_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,493 @@
|
||||
/**************************************************************************//**
|
||||
* @file retarget.c
|
||||
* @version V1.00
|
||||
* $Revision: 4 $
|
||||
* $Date: 15/11/02 2:11p $
|
||||
* @brief Mini58 series retarget source file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include <stdio.h>
|
||||
#include "Mini58Series.h"
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if (__ARMCC_VERSION < 400000)
|
||||
#else
|
||||
/* Insist on keeping widthprec, to avoid X propagation by benign code in C-lib */
|
||||
#pragma import _printf_widthprec
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG_ENABLE_UART1
|
||||
#define DEBUG_PORT UART1
|
||||
#else
|
||||
#define DEBUG_PORT UART0
|
||||
#endif
|
||||
|
||||
/* Un-comment this line to disable all printf and getchar. getchar() will always return 0x00*/
|
||||
//#define DISABLE_UART
|
||||
|
||||
#if defined(DEBUG_ENABLE_SEMIHOST)
|
||||
#ifndef DISABLE_UART
|
||||
#define DISABLE_UART
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* Global variables */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
|
||||
#if !(defined(__ICCARM__) && (__VER__ >= 6010000))
|
||||
struct __FILE { int handle; /* Add whatever you need here */ };
|
||||
#endif
|
||||
FILE __stdout;
|
||||
FILE __stdin;
|
||||
|
||||
enum { r0, r1, r2, r3, r12, lr, pc, psr};
|
||||
|
||||
void stackDump(uint32_t stack[])
|
||||
{
|
||||
printf("r0 = 0x%x\n", stack[r0]);
|
||||
printf("r1 = 0x%x\n", stack[r1]);
|
||||
printf("r2 = 0x%x\n", stack[r2]);
|
||||
printf("r3 = 0x%x\n", stack[r3]);
|
||||
printf("r12 = 0x%x\n", stack[r12]);
|
||||
printf("lr = 0x%x\n", stack[lr]);
|
||||
printf("pc = 0x%x\n", stack[pc]);
|
||||
printf("psr = 0x%x\n", stack[psr]);
|
||||
}
|
||||
|
||||
void Hard_Fault_Handler(uint32_t stack[])
|
||||
{
|
||||
printf("In Hard Fault Handler\n");
|
||||
|
||||
stackDump(stack);
|
||||
|
||||
//Chip Reset
|
||||
//SYS_UnlockReg();
|
||||
//SYS->IPRSTC1 |= SYS_IPRSTC1_CHIP_RST_Msk;
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
|
||||
#if defined(DEBUG_ENABLE_SEMIHOST)
|
||||
/* The static buffer is used to speed up the semihost */
|
||||
static char g_buf[16];
|
||||
static char g_buf_len = 0;
|
||||
|
||||
# if defined(__ICCARM__)
|
||||
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to support semihost
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @returns None
|
||||
*
|
||||
* @details This function is implement to support semihost message print.
|
||||
*
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
asm("MOV R0, lr \n"
|
||||
"LSLS R0, #29 \n" //; Check bit 2
|
||||
"BMI SP_is_PSP \n" //; previous stack is PSP
|
||||
"MRS R0, MSP \n" //; previous stack is MSP, read MSP
|
||||
"B SP_Read_Ready \n"
|
||||
"SP_is_PSP: \n"
|
||||
"MRS R0, PSP \n" //; Read PSP
|
||||
"SP_Read_Ready: \n"
|
||||
"LDR R1, [R0, #24] \n" //; Get previous PC
|
||||
"LDRH R3, [R1] \n" //; Get instruction
|
||||
"LDR R2, [pc, #8] \n" //; The special BKPT instruction
|
||||
"CMP R3, R2 \n" //; Test if the instruction at previous PC is BKPT
|
||||
"BNE HardFault_Handler_Ret\n" //; Not BKPT
|
||||
"ADDS R1, #4 \n" //; Skip BKPT and next line
|
||||
"STR R1, [R0, #24] \n" //; Save previous PC
|
||||
"BX lr \n" //; Return
|
||||
"DCD 0xBEAB \n" //; BKPT instruction code
|
||||
"HardFault_Handler_Ret:\n"
|
||||
"MOVS r0, #4 \n"
|
||||
"MOV r1, LR \n"
|
||||
"TST r0, r1 \n"
|
||||
"BEQ Stack_Use_MSP \n"
|
||||
"MRS R0, PSP \n" //; stack use PSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
"Stack_Use_MSP: \n"
|
||||
"MRS R0, MSP \n" //; stack use MSP
|
||||
"Get_LR_and_Branch: \n"
|
||||
"MOV R1, LR \n" //; LR current value
|
||||
"B Hard_Fault_Handler \n"
|
||||
);
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief The function to process semihosted command
|
||||
* @param[in] n32In_R0 : semihost register 0
|
||||
* @param[in] n32In_R1 : semihost register 1
|
||||
* @param[out] pn32Out_R0: semihost register 0
|
||||
* @retval 0: No ICE debug
|
||||
* @retval 1: ICE debug
|
||||
*
|
||||
*/
|
||||
int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
|
||||
{
|
||||
asm("BKPT 0xAB \n" //; This instruction will cause ICE trap or system HardFault
|
||||
"B SH_ICE \n"
|
||||
"SH_HardFault: \n" //; Captured by HardFault
|
||||
"MOVS R0, #0 \n" //; Set return value to 0
|
||||
"BX lr \n" //; Return
|
||||
"SH_ICE: \n" //; Captured by ICE
|
||||
"CMP R2, #0 \n"
|
||||
"BEQ SH_End \n"
|
||||
"STR R0, [R2]\n" //; Save the return value to *pn32Out_R0
|
||||
"SH_End: \n");
|
||||
|
||||
return 1; //; Return 1 when it is trap by ICE
|
||||
|
||||
}
|
||||
|
||||
|
||||
# else
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to support semihost
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @returns None
|
||||
*
|
||||
* @details This function is implement to support semihost message print.
|
||||
*
|
||||
*/
|
||||
__asm int32_t HardFault_Handler(void)
|
||||
{
|
||||
|
||||
MOV R0, LR
|
||||
LSLS R0, #29 //; Check bit 2
|
||||
BMI SP_is_PSP //; previous stack is PSP
|
||||
MRS R0, MSP //; previous stack is MSP, read MSP
|
||||
B SP_Read_Ready
|
||||
SP_is_PSP
|
||||
MRS R0, PSP //; Read PSP
|
||||
|
||||
SP_Read_Ready
|
||||
LDR R1, [R0, #24] //; Get previous PC
|
||||
LDRH R3, [R1] //; Get instruction
|
||||
LDR R2, =0xBEAB //; The special BKPT instruction
|
||||
CMP R3, R2 //; Test if the instruction at previous PC is BKPT
|
||||
BNE HardFault_Handler_Ret //; Not BKPT
|
||||
|
||||
ADDS R1, #4 //; Skip BKPT and next line
|
||||
STR R1, [R0, #24] //; Save previous PC
|
||||
|
||||
BX LR //; Return
|
||||
HardFault_Handler_Ret
|
||||
|
||||
/* TODO: Implement your own hard fault handler here. */
|
||||
MOVS r0, #4
|
||||
MOV r1, LR
|
||||
TST r0, r1
|
||||
BEQ Stack_Use_MSP
|
||||
MRS R0, PSP ;stack use PSP
|
||||
B Get_LR_and_Branch
|
||||
Stack_Use_MSP
|
||||
MRS R0, MSP ; stack use MSP
|
||||
Get_LR_and_Branch
|
||||
MOV R1, LR ; LR current value
|
||||
LDR R2,=__cpp(Hard_Fault_Handler)
|
||||
BX R2
|
||||
|
||||
B .
|
||||
|
||||
ALIGN
|
||||
}
|
||||
|
||||
/**
|
||||
*
|
||||
* @brief The function to process semihosted command
|
||||
* @param[in] n32In_R0 : semihost register 0
|
||||
* @param[in] n32In_R1 : semihost register 1
|
||||
* @param[out] pn32Out_R0: semihost register 0
|
||||
* @retval 0: No ICE debug
|
||||
* @retval 1: ICE debug
|
||||
*
|
||||
*/
|
||||
__asm int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0)
|
||||
{
|
||||
BKPT 0xAB //; Wait ICE or HardFault
|
||||
//; ICE will step over BKPT directly
|
||||
//; HardFault will step BKPT and the next line
|
||||
B SH_ICE
|
||||
|
||||
SH_HardFault //; Captured by HardFault
|
||||
MOVS R0, #0 //; Set return value to 0
|
||||
BX lr //; Return
|
||||
|
||||
SH_ICE //; Captured by ICE
|
||||
//; Save return value
|
||||
CMP R2, #0
|
||||
BEQ SH_End
|
||||
STR R0, [R2] //; Save the return value to *pn32Out_R0
|
||||
|
||||
SH_End
|
||||
MOVS R0, #1 //; Set return value to 1
|
||||
BX lr //; Return
|
||||
}
|
||||
#endif
|
||||
|
||||
#else
|
||||
|
||||
# if defined(__ICCARM__)
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @returns None
|
||||
*
|
||||
* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr.
|
||||
*
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
asm("MOVS r0, #4 \n"
|
||||
"MOV r1, LR \n"
|
||||
"TST r0, r1 \n"
|
||||
"BEQ Stack_Use_MSP \n"
|
||||
"MRS R0, PSP \n" //; stack use PSP
|
||||
"B Get_LR_and_Branch \n"
|
||||
"Stack_Use_MSP: \n"
|
||||
"MRS R0, MSP \n" //; stack use MSP
|
||||
"Get_LR_and_Branch: \n"
|
||||
"MOV R1, LR \n" //; LR current value
|
||||
"B Hard_Fault_Handler \n"
|
||||
);
|
||||
|
||||
while(1);
|
||||
}
|
||||
|
||||
# else
|
||||
|
||||
/**
|
||||
* @brief This HardFault handler is implemented to show r0, r1, r2, r3, r12, lr, pc, psr
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @returns None
|
||||
*
|
||||
* @details This function is implement to print r0, r1, r2, r3, r12, lr, pc, psr
|
||||
*
|
||||
*/
|
||||
__asm int32_t HardFault_Handler(void)
|
||||
{
|
||||
MOVS r0, #4
|
||||
MOV r1, LR
|
||||
TST r0, r1
|
||||
BEQ Stack_Use_MSP
|
||||
MRS R0, PSP ;stack use PSP
|
||||
B Get_LR_and_Branch
|
||||
Stack_Use_MSP
|
||||
MRS R0, MSP ; stack use MSP
|
||||
Get_LR_and_Branch
|
||||
MOV R1, LR ; LR current value
|
||||
LDR R2,=__cpp(Hard_Fault_Handler)
|
||||
BX R2
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write a char to UART.
|
||||
* @param ch The character sent to UART.
|
||||
* @return None
|
||||
*/
|
||||
|
||||
void SendChar_ToUART(int ch)
|
||||
{
|
||||
#ifndef DISABLE_UART
|
||||
while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
|
||||
DEBUG_PORT->DAT = ch;
|
||||
if(ch == '\n'){
|
||||
while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk);
|
||||
DEBUG_PORT->DAT = '\r';
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Write a char to debug console.
|
||||
* @param ch The character sent to debug console
|
||||
* @return None
|
||||
*/
|
||||
|
||||
void SendChar(int ch)
|
||||
{
|
||||
#if defined(DEBUG_ENABLE_SEMIHOST)
|
||||
g_buf[g_buf_len++] = ch;
|
||||
g_buf[g_buf_len] = '\0';
|
||||
if(g_buf_len + 1 >= sizeof(g_buf) || ch == '\n' || ch == '\0')
|
||||
{
|
||||
|
||||
/* Send the char */
|
||||
|
||||
if(SH_DoCommand(0x04, (int)g_buf, NULL) != 0)
|
||||
{
|
||||
g_buf_len = 0;
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i=0;i<g_buf_len;i++)
|
||||
SendChar_ToUART(g_buf[i]);
|
||||
g_buf_len = 0;
|
||||
}
|
||||
}
|
||||
#else
|
||||
SendChar_ToUART(ch);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Read a char from debug console.
|
||||
* @param None
|
||||
* @return Received character from debug console
|
||||
* @note This API waits until UART debug port or semihost input a character
|
||||
*/
|
||||
|
||||
char GetChar(void)
|
||||
{
|
||||
#if defined(DEBUG_ENABLE_SEMIHOST)
|
||||
# if defined ( __CC_ARM )
|
||||
int nRet;
|
||||
while(SH_DoCommand(0x101, 0, &nRet) != 0)
|
||||
{
|
||||
if(nRet != 0)
|
||||
{
|
||||
SH_DoCommand(0x07, 0, &nRet);
|
||||
return (char)nRet;
|
||||
}
|
||||
}
|
||||
# else
|
||||
int nRet;
|
||||
while(SH_DoCommand(0x7, 0, &nRet) != 0)
|
||||
{
|
||||
if(nRet != 0)
|
||||
return (char)nRet;
|
||||
}
|
||||
# endif
|
||||
#endif
|
||||
#ifndef DISABLE_UART
|
||||
while (1){
|
||||
if(!(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk))
|
||||
{
|
||||
return (DEBUG_PORT->DAT);
|
||||
|
||||
}
|
||||
}
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check whether UART receive FIFO is empty or not.
|
||||
* @param None
|
||||
* @return UART Rx FIFO empty status
|
||||
* @retval 1 Indicates at least one character is available in UART Rx FIFO
|
||||
* @retval 0 UART Rx FIFO is empty
|
||||
*/
|
||||
int kbhit(void)
|
||||
{
|
||||
#ifndef DISABLE_UART
|
||||
return !(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check whether UART transmit FIFO is empty or not.
|
||||
* @param None
|
||||
* @return UART Tx FIFO empty status
|
||||
* @retval 1 UART Tx FIFO is empty
|
||||
* @retval 0 UART Tx FIFO is not empty
|
||||
*/
|
||||
int IsDebugFifoEmpty(void)
|
||||
{
|
||||
#ifndef DISABLE_UART
|
||||
return (DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) ? 1 : 0;
|
||||
#else
|
||||
return(1);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
/* C library retargetting */
|
||||
/*---------------------------------------------------------------------------------------------------------*/
|
||||
void _ttywrch(int ch)
|
||||
{
|
||||
SendChar(ch);
|
||||
return;
|
||||
}
|
||||
|
||||
int fputc(int ch, FILE *f)
|
||||
{
|
||||
SendChar(ch);
|
||||
return ch;
|
||||
}
|
||||
|
||||
int fgetc(FILE *f) {
|
||||
return (GetChar());
|
||||
}
|
||||
|
||||
|
||||
int ferror(FILE *f) {
|
||||
return EOF;
|
||||
}
|
||||
|
||||
#ifdef DEBUG_ENABLE_SEMIHOST
|
||||
# ifdef __ICCARM__
|
||||
void __exit(int return_code) {
|
||||
|
||||
/* Check if link with ICE */
|
||||
|
||||
if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
|
||||
{
|
||||
/* Make sure all message is print out */
|
||||
|
||||
while(IsDebugFifoEmpty() == 0);
|
||||
}
|
||||
label: goto label; /* endless loop */
|
||||
}
|
||||
# else
|
||||
void _sys_exit(int return_code) {
|
||||
|
||||
/* Check if link with ICE */
|
||||
if(SH_DoCommand(0x18, 0x20026, NULL) == 0)
|
||||
{
|
||||
/* Make sure all message is print out */
|
||||
while(IsDebugFifoEmpty() == 0);
|
||||
}
|
||||
label: goto label; /* endless loop */
|
||||
}
|
||||
# endif
|
||||
#endif
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
|
||||
@@ -0,0 +1,260 @@
|
||||
/**************************************************************************//**
|
||||
* @file spi.c
|
||||
* @version V1.00
|
||||
* $Revision: 7 $
|
||||
* $Date: 15/05/28 1:47p $
|
||||
* @brief Mini58 series SPI driver source file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "Mini58Series.h"
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_SPI_Driver SPI Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Mini58_SPI_EXPORTED_FUNCTIONS SPI Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function make SPI module be ready to transfer.
|
||||
* By default, the SPI transfer sequence is MSB first and
|
||||
* the automatic slave select function is disabled. In
|
||||
* Slave mode, the u32BusClock must be NULL and the SPI clock
|
||||
* divider setting will be 0.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @param[in] u32MasterSlave decides the SPI module is operating in master mode or in slave mode. ( \ref SPI_SLAVE, \ref SPI_MASTER)
|
||||
* @param[in] u32SPIMode decides the transfer timing. ( \ref SPI_MODE_0, \ref SPI_MODE_1, \ref SPI_MODE_2, \ref SPI_MODE_3)
|
||||
* @param[in] u32DataWidth decides the data width of a SPI transaction.
|
||||
* @param[in] u32BusClock is the expected frequency of SPI bus clock in Hz.
|
||||
* @return Actual frequency of SPI peripheral clock.
|
||||
*/
|
||||
uint32_t SPI_Open(SPI_T *spi,
|
||||
uint32_t u32MasterSlave,
|
||||
uint32_t u32SPIMode,
|
||||
uint32_t u32DataWidth,
|
||||
uint32_t u32BusClock)
|
||||
{
|
||||
if(u32DataWidth == 32)
|
||||
u32DataWidth = 0;
|
||||
|
||||
spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode);
|
||||
|
||||
if(u32MasterSlave == SPI_SLAVE)
|
||||
spi->SSCTL = SPI_SSCTL_SSLTEN_Msk;
|
||||
|
||||
return ( SPI_SetBusClock(spi, u32BusClock) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reset SPI module and disable SPI peripheral clock.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Close(SPI_T *spi)
|
||||
{
|
||||
/* Reset SPI */
|
||||
SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk;
|
||||
SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Rx FIFO buffer.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
void SPI_ClearRxFIFO(SPI_T *spi)
|
||||
{
|
||||
spi->FIFOCTL |= SPI_FIFOCTL_RXRST_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear Tx FIFO buffer.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
void SPI_ClearTxFIFO(SPI_T *spi)
|
||||
{
|
||||
spi->FIFOCTL |= SPI_FIFOCTL_TXRST_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the automatic slave select function.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
void SPI_DisableAutoSS(SPI_T *spi)
|
||||
{
|
||||
spi->SSCTL &= ~SPI_SSCTL_AUTOSS_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the automatic slave select function. Only available in Master mode.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @param[in] u32SSPinMask specifies slave select pins. ( \ref SPI_SS)
|
||||
* @param[in] u32ActiveLevel specifies the active level of slave select signal. ( \ref SPI_SS_ACTIVE_HIGH, \ref SPI_SS_ACTIVE_LOW)
|
||||
* @return none
|
||||
*/
|
||||
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
|
||||
{
|
||||
spi->SSCTL = (spi->SSCTL & ~(SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI_SSCTL_AUTOSS_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the SPI bus clock. Only available in Master mode.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @param[in] u32BusClock is the expected frequency of SPI bus clock.
|
||||
* @return Actual frequency of SPI peripheral clock.
|
||||
*/
|
||||
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock)
|
||||
{
|
||||
uint32_t u32Div = 0;
|
||||
uint32_t u32ClkSrc;
|
||||
|
||||
if((CLK->CLKSEL1 & CLK_CLKSEL1_SPISEL_Msk) == CLK_CLKSEL1_SPISEL_XTAL) {
|
||||
if((u32ClkSrc = CLK_GetHXTFreq()) == 0)
|
||||
u32ClkSrc = CLK_GetLXTFreq();
|
||||
} else if((CLK->CLKSEL1 & CLK_CLKSEL1_SPISEL_Msk) == CLK_CLKSEL1_SPISEL_PLL)
|
||||
u32ClkSrc = CLK_GetPLLClockFreq();
|
||||
else
|
||||
u32ClkSrc = CLK_GetHCLKFreq();
|
||||
|
||||
if(u32BusClock > u32ClkSrc)
|
||||
u32BusClock = u32ClkSrc;
|
||||
|
||||
if(u32BusClock != 0) {
|
||||
u32Div = (((u32ClkSrc / u32BusClock) + 1) >> 1) - 1;
|
||||
if(u32Div > SPI_CLKDIV_DIVIDER_Msk)
|
||||
u32Div = SPI_CLKDIV_DIVIDER_Msk;
|
||||
} else
|
||||
return 0;
|
||||
|
||||
spi->CLKDIV = (spi->CLKDIV & ~SPI_CLKDIV_DIVIDER_Msk) | u32Div;
|
||||
|
||||
return ( u32ClkSrc / ((u32Div+1)*2) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable FIFO mode with user-specified Tx FIFO threshold and Rx FIFO threshold configurations.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @param[in] u32TxThreshold decides the Tx FIFO threshold.
|
||||
* @param[in] u32RxThreshold decides the Rx FIFO threshold.
|
||||
* @return none
|
||||
*/
|
||||
void SPI_EnableFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
|
||||
{
|
||||
spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk) |
|
||||
(u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) |
|
||||
(u32RxThreshold << SPI_FIFOCTL_RXTH_Pos));
|
||||
|
||||
spi->CTL |= SPI_CTL_FIFOEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable FIFO mode.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return none
|
||||
*/
|
||||
void SPI_DisableFIFO(SPI_T *spi)
|
||||
{
|
||||
spi->CTL &= ~SPI_CTL_FIFOEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the actual frequency of SPI bus clock. Only available in Master mode.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @return Actual SPI bus clock frequency.
|
||||
*/
|
||||
uint32_t SPI_GetBusClock(SPI_T *spi)
|
||||
{
|
||||
uint32_t u32Div;
|
||||
uint32_t u32ClkSrc;
|
||||
|
||||
if((CLK->CLKSEL1 & CLK_CLKSEL1_SPISEL_Msk) == CLK_CLKSEL1_SPISEL_XTAL) {
|
||||
if((u32ClkSrc = CLK_GetHXTFreq()) == 0)
|
||||
u32ClkSrc = CLK_GetLXTFreq();
|
||||
} else if((CLK->CLKSEL1 & CLK_CLKSEL1_SPISEL_Msk) == CLK_CLKSEL1_SPISEL_PLL)
|
||||
u32ClkSrc = CLK_GetPLLClockFreq();
|
||||
else
|
||||
u32ClkSrc = CLK_GetHCLKFreq();
|
||||
|
||||
u32Div = spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk;
|
||||
|
||||
return ( u32ClkSrc / ((u32Div + 1)*2) );
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable FIFO related interrupts specified by u32Mask parameter.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @param[in] u32Mask is the combination of all related interrupt enable bits.
|
||||
* Each bit corresponds to a interrupt bit.
|
||||
* This parameter decides which interrupts will be enabled.
|
||||
* ( \ref SPI_IE_MASK, \ref SPI_SSTA_INTEN_MASK, \ref SPI_FIFO_TX_INTEN_MASK,
|
||||
* \ref SPI_FIFO_RX_INTEN_MASK, \ref SPI_FIFO_RXOV_INTEN_MASK, \ref SPI_FIFO_TIMEOUT_INTEN_MASK)
|
||||
* @return none
|
||||
*/
|
||||
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask)
|
||||
{
|
||||
if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
|
||||
spi->CTL |= SPI_CTL_UNITIEN_Msk;
|
||||
|
||||
if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
|
||||
spi->SLVCTL |= SPI_SLVCTL_SLVSTIEN_Msk;
|
||||
|
||||
if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
|
||||
spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk;
|
||||
|
||||
if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
|
||||
spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk;
|
||||
|
||||
if((u32Mask & SPI_FIFO_RXOV_INTEN_MASK) == SPI_FIFO_RXOV_INTEN_MASK)
|
||||
spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk;
|
||||
|
||||
if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
|
||||
spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable FIFO related interrupts specified by u32Mask parameter.
|
||||
* @param[in] spi is the base address of SPI module.
|
||||
* @param[in] u32Mask is the combination of all related interrupt enable bits.
|
||||
* Each bit corresponds to a interrupt bit.
|
||||
* This parameter decides which interrupts will be disabled.
|
||||
* ( \ref SPI_IE_MASK, \ref SPI_SSTA_INTEN_MASK, \ref SPI_FIFO_TX_INTEN_MASK,
|
||||
* \ref SPI_FIFO_RX_INTEN_MASK, \ref SPI_FIFO_RXOV_INTEN_MASK, \ref SPI_FIFO_TIMEOUT_INTEN_MASK)
|
||||
* @return none
|
||||
*/
|
||||
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask)
|
||||
{
|
||||
if((u32Mask & SPI_IE_MASK) == SPI_IE_MASK)
|
||||
spi->CTL &= ~SPI_CTL_UNITIEN_Msk;
|
||||
|
||||
if((u32Mask & SPI_SSTA_INTEN_MASK) == SPI_SSTA_INTEN_MASK)
|
||||
spi->SLVCTL &= ~SPI_SLVCTL_SLVSTIEN_Msk;
|
||||
|
||||
if((u32Mask & SPI_FIFO_TX_INTEN_MASK) == SPI_FIFO_TX_INTEN_MASK)
|
||||
spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk;
|
||||
|
||||
if((u32Mask & SPI_FIFO_RX_INTEN_MASK) == SPI_FIFO_RX_INTEN_MASK)
|
||||
spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk;
|
||||
|
||||
if((u32Mask & SPI_FIFO_RXOV_INTEN_MASK) == SPI_FIFO_RXOV_INTEN_MASK)
|
||||
spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk;
|
||||
|
||||
if((u32Mask & SPI_FIFO_TIMEOUT_INTEN_MASK) == SPI_FIFO_TIMEOUT_INTEN_MASK)
|
||||
spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk;
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group Mini58_SPI_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_SPI_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,153 @@
|
||||
/**************************************************************************//**
|
||||
* @file sys.c
|
||||
* @version V1.00
|
||||
* $Revision: 9 $
|
||||
* $Date: 15/06/05 1:13p $
|
||||
* @brief Mini58 series SYS driver source file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "Mini58Series.h"
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_SYS_Driver SYS Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Mini58_SYS_EXPORTED_FUNCTIONS SYS Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function clear the selected system reset source
|
||||
* @param[in] u32Src is system reset source
|
||||
* @return None
|
||||
*/
|
||||
void SYS_ClearResetSrc(uint32_t u32Src)
|
||||
{
|
||||
SYS->RSTSTS |= u32Src;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function get Brown-out detector output status
|
||||
* @return 0: System voltage is higher than BOD_VL setting or BOD_EN is 0.
|
||||
* 1: System voltage is lower than BOD_VL setting.
|
||||
* Note : If the BOD_EN is 0, this function always return 0.
|
||||
*/
|
||||
uint32_t SYS_GetBODStatus(void)
|
||||
{
|
||||
return (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk)?1:0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function get the system reset source register value
|
||||
* @return Reset source
|
||||
*/
|
||||
uint32_t SYS_GetResetSrc(void)
|
||||
{
|
||||
return (SYS->RSTSTS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function check register write-protection bit setting
|
||||
* @return 0: Write-protection function is disabled.
|
||||
* 1: Write-protection function is enabled.
|
||||
*/
|
||||
uint32_t SYS_IsRegLocked(void)
|
||||
{
|
||||
return !(SYS->REGLCTL & SYS_REGLCTL_REGLCTL_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function get product ID.
|
||||
* @return Product ID
|
||||
*/
|
||||
uint32_t SYS_ReadPDID(void)
|
||||
{
|
||||
return SYS->PDID;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function reset chip.
|
||||
* @return None
|
||||
*/
|
||||
void SYS_ResetChip(void)
|
||||
{
|
||||
SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function reset CPU.
|
||||
* @return None
|
||||
*/
|
||||
void SYS_ResetCPU(void)
|
||||
{
|
||||
SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function reset selected modules.
|
||||
* @param[in] u32ModuleIndex is module index. Including :
|
||||
* - \ref ADC_RST
|
||||
* - \ref ACMP_RST
|
||||
* - \ref PWM0_RST
|
||||
* - \ref UART0_RST
|
||||
* - \ref UART1_RST
|
||||
* - \ref SPI0_RST
|
||||
* - \ref I2C0_RST
|
||||
* - \ref I2C1_RST
|
||||
* - \ref TMR1_RST
|
||||
* - \ref TMR0_RST
|
||||
* - \ref GPIO_RST
|
||||
* @return None
|
||||
*/
|
||||
void SYS_ResetModule(uint32_t u32ModuleIndex)
|
||||
{
|
||||
*(volatile uint32_t *)(&(SYS->IPRST0) + (u32ModuleIndex>>24)) |= 1<<(u32ModuleIndex & 0x00ffffff);
|
||||
*(volatile uint32_t *)(&(SYS->IPRST0) + (u32ModuleIndex>>24)) &= ~(1<<(u32ModuleIndex & 0x00ffffff));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function configure BOD function.
|
||||
* Configure BOD reset or interrupt mode and set Brown-out voltage level.
|
||||
* Enable Brown-out function
|
||||
* @param[in] i32Mode is reset or interrupt mode. Including :
|
||||
* - \ref SYS_BODCTL_BOD_RST_EN
|
||||
* - \ref SYS_BODCTL_BOD_INTERRUPT_EN
|
||||
* @param[in] u32BODLevel is Brown-out voltage level. Including :
|
||||
* - \ref SYS_BODCTL_BODVL_4_4V
|
||||
* - \ref SYS_BODCTL_BODVL_3_7V
|
||||
* - \ref SYS_BODCTL_BODVL_2_7V
|
||||
* - \ref SYS_BODCTL_BODVL_2_2V
|
||||
* @return None
|
||||
*/
|
||||
void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
|
||||
{
|
||||
SYS->BODCTL |= SYS_BODCTL_BODEN_Msk;
|
||||
SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | i32Mode;
|
||||
SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disable BOD function.
|
||||
* @return None
|
||||
*/
|
||||
void SYS_DisableBOD(void)
|
||||
{
|
||||
SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;
|
||||
SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | SYS_BODCTL_BODVL_Msk ;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_SYS_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_SYS_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,217 @@
|
||||
/**************************************************************************//**
|
||||
* @file timer.c
|
||||
* @version V1.00
|
||||
* $Revision: 3 $
|
||||
* $Date: 15/05/27 11:56a $
|
||||
* @brief Mini58 series TIMER driver source file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "Mini58Series.h"
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_TIMER_Driver TIMER Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Mini58_TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This API is used to configure timer to operate in specified mode
|
||||
* and frequency. If timer cannot work in target frequency, a closest
|
||||
* frequency will be chose and returned.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @param[in] u32Mode Operation mode. Possible options are
|
||||
* - \ref TIMER_ONESHOT_MODE
|
||||
* - \ref TIMER_PERIODIC_MODE
|
||||
* - \ref TIMER_TOGGLE_MODE
|
||||
* - \ref TIMER_CONTINUOUS_MODE
|
||||
* @param[in] u32Freq Target working frequency
|
||||
* @return Real Timer working frequency
|
||||
* @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling
|
||||
* \ref TIMER_Start macro or program registers directly
|
||||
*/
|
||||
uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
|
||||
{
|
||||
uint32_t u32Clk = TIMER_GetModuleClock(timer);
|
||||
uint32_t u32Cmpr = 0, u32Prescale = 0;
|
||||
|
||||
// Fastest possible timer working freq is u32Clk / 2. While cmpr = 2, pre-scale = 0
|
||||
if(u32Freq > (u32Clk / 2)) {
|
||||
u32Cmpr = 2;
|
||||
} else {
|
||||
if(u32Clk >= 0x2000000) {
|
||||
u32Prescale = 3; // real prescaler value is 4
|
||||
u32Clk >>= 2;
|
||||
} else if(u32Clk >= 0x1000000) {
|
||||
u32Prescale = 1; // real prescaler value is 2
|
||||
u32Clk >>= 1;
|
||||
}
|
||||
u32Cmpr = u32Clk / u32Freq;
|
||||
}
|
||||
|
||||
timer->CTL = u32Mode | u32Prescale;
|
||||
timer->CMP = u32Cmpr;
|
||||
|
||||
return(u32Clk / (u32Cmpr * (u32Prescale + 1)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This API stops Timer counting and disable the Timer interrupt function
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
void TIMER_Close(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL = 0;
|
||||
timer->EXTCTL = 0;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This API is used to create a delay loop for u32usec micro seconds
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @param[in] u32Usec Delay period in micro seconds with 10 usec every step. Valid values are between 10~1000000 (10 micro second ~ 1 second)
|
||||
* @return None
|
||||
* @note This API overwrites the register setting of the timer used to count the delay time.
|
||||
* @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay
|
||||
*/
|
||||
void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
|
||||
{
|
||||
uint32_t u32Clk = TIMER_GetModuleClock(timer);
|
||||
uint32_t u32Prescale = 0, delay = SystemCoreClock / u32Clk;
|
||||
float fCmpr;
|
||||
|
||||
// Clear current timer configuration
|
||||
timer->CTL = 0;
|
||||
timer->EXTCTL = 0;
|
||||
|
||||
if(u32Clk == 10000) { // min delay is 100us if timer clock source is LIRC 10k
|
||||
u32Usec = ((u32Usec + 99) / 100) * 100;
|
||||
} else { // 10 usec every step
|
||||
u32Usec = ((u32Usec + 9) / 10) * 10;
|
||||
}
|
||||
|
||||
if(u32Clk >= 0x2000000) {
|
||||
u32Prescale = 3; // real prescaler value is 4
|
||||
u32Clk >>= 2;
|
||||
} else if(u32Clk >= 0x1000000) {
|
||||
u32Prescale = 1; // real prescaler value is 2
|
||||
u32Clk >>= 1;
|
||||
}
|
||||
|
||||
// u32Usec * u32Clk might overflow if using uint32_t
|
||||
fCmpr = ((float)u32Usec * (float)u32Clk) / 1000000.0;
|
||||
|
||||
timer->CMP = (uint32_t)fCmpr;
|
||||
timer->CTL = TIMER_CTL_CNTEN_Msk | u32Prescale; // one shot mode
|
||||
|
||||
// When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
|
||||
// And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
|
||||
for(; delay > 0; delay--) {
|
||||
__NOP();
|
||||
}
|
||||
|
||||
while(timer->CTL & TIMER_CTL_ACTSTS_Msk);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This API is used to enable timer capture function with specified mode and capture edge
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @param[in] u32CapMode Timer capture mode. Could be
|
||||
* - \ref TIMER_CAPTURE_FREE_COUNTING_MODE
|
||||
* - \ref TIMER_CAPTURE_TRIGGER_COUNTING_MODE
|
||||
* - \ref TIMER_CAPTURE_COUNTER_RESET_MODE
|
||||
* @param[in] u32Edge Timer capture edge. Possible values are
|
||||
* - \ref TIMER_CAPTURE_FALLING_EDGE
|
||||
* - \ref TIMER_CAPTURE_RISING_EDGE
|
||||
* - \ref TIMER_CAPTURE_FALLING_THEN_RISING_EDGE
|
||||
* - \ref TIMER_CAPTURE_RISING_THEN_FALLING_EDGE
|
||||
* @return None
|
||||
* @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly
|
||||
*/
|
||||
void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
|
||||
{
|
||||
|
||||
timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPSEL_Msk |
|
||||
TIMER_EXTCTL_CAPFUNCS_Msk |
|
||||
TIMER_EXTCTL_CAPEDGE_Msk)) |
|
||||
u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This API is used to disable the Timer capture function
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
void TIMER_DisableCapture(TIMER_T *timer)
|
||||
{
|
||||
timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function is used to enable the Timer counter function with specify detection edge
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @param[in] u32Edge Detection edge of counter pin. Could be ether
|
||||
* - \ref TIMER_COUNTER_RISING_EDGE, or
|
||||
* - \ref TIMER_COUNTER_FALLING_EDGE
|
||||
* @return None
|
||||
* @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly
|
||||
*/
|
||||
void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
|
||||
{
|
||||
timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge;
|
||||
timer->CTL |= TIMER_CTL_EXTCNTEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This API is used to disable the Timer event counter function.
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return None
|
||||
*/
|
||||
void TIMER_DisableEventCounter(TIMER_T *timer)
|
||||
{
|
||||
timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This API is used to get the clock frequency of Timer
|
||||
* @param[in] timer The base address of Timer module
|
||||
* @return Timer clock frequency
|
||||
* @note This API cannot return correct clock rate if timer source is external clock input.
|
||||
*/
|
||||
uint32_t TIMER_GetModuleClock(TIMER_T *timer)
|
||||
{
|
||||
uint32_t u32Src;
|
||||
if(timer == TIMER0)
|
||||
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR0SEL_Msk) >> CLK_CLKSEL1_TMR0SEL_Pos;
|
||||
else
|
||||
u32Src = (CLK->CLKSEL1 & CLK_CLKSEL1_TMR1SEL_Msk) >> CLK_CLKSEL1_TMR1SEL_Pos;
|
||||
|
||||
if(u32Src == 0)
|
||||
return((CLK->PWRCTL & CLK_PWRCTL_XTLEN_Msk) == 1 ? __XTAL12M : __XTAL32K);
|
||||
else if(u32Src == 1)
|
||||
return __IRC10K;
|
||||
else if(u32Src == 2)
|
||||
return SystemCoreClock;
|
||||
else
|
||||
return __HSI;
|
||||
|
||||
}
|
||||
|
||||
/*@}*/ /* end of group Mini58_TIMER_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_TIMER_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,364 @@
|
||||
/**************************************************************************//**
|
||||
* @file uart.c
|
||||
* @version V1.00
|
||||
* $Revision: 3 $
|
||||
* $Date: 15/05/28 4:34p $
|
||||
* @brief Mini58 series UART driver source file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include "Mini58Series.h"
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_UART_Driver UART Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Mini58_UART_EXPORTED_FUNCTIONS UART Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief The function is used to clear UART specified interrupt flag.
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
* @param[in] u32InterruptFlag The specified interrupt of UART module.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag)
|
||||
{
|
||||
|
||||
if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) { /* clear Receive Line Status Interrupt */
|
||||
uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_FEF_Msk;
|
||||
uart->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk;
|
||||
}
|
||||
|
||||
if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* clear Modem Interrupt */
|
||||
uart->MODEMSTS = UART_MODEMSTS_CTSDETF_Msk;
|
||||
|
||||
if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) { /* clear Buffer Error Interrupt */
|
||||
uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
|
||||
}
|
||||
|
||||
if(u32InterruptFlag & UART_INTSTS_RXTOINT_Msk) /* clear Modem Interrupt */
|
||||
uart->INTSTS = UART_INTSTS_RXTOIF_Msk;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief The function is used to disable UART.
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void UART_Close(UART_T* uart)
|
||||
{
|
||||
uart->INTEN = 0;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief The function is used to disable UART auto flow control.
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void UART_DisableFlowCtrl(UART_T* uart)
|
||||
{
|
||||
uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
* @param[in] u32InterruptFlag The specified interrupt of UART module.
|
||||
* - \ref UART_INTEN_TOCNTEN_Msk : Rx Time Out interrupt
|
||||
* - \ref UART_INTEN_WKCTSIEN_Msk : Wakeup interrupt
|
||||
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
|
||||
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
|
||||
* - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
|
||||
* - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
|
||||
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
|
||||
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag )
|
||||
{
|
||||
uart->INTEN &= ~ u32InterruptFlag;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief The function is used to Enable UART auto flow control.
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void UART_EnableFlowCtrl(UART_T* uart )
|
||||
{
|
||||
uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
|
||||
uart->MODEM &= ~UART_MODEM_RTS_Msk;
|
||||
uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
|
||||
uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief The function is used to enable UART specified interrupt and disable NVIC UART IRQ.
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
* @param[in] u32InterruptFlag The specified interrupt of UART module:
|
||||
* - \ref UART_INTEN_TOCNTEN_Msk : Rx Time Out interrupt
|
||||
* - \ref UART_INTEN_WKCTSIEN_Msk : Wakeup interrupt
|
||||
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
|
||||
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
|
||||
* - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
|
||||
* - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
|
||||
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
|
||||
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag )
|
||||
{
|
||||
uart->INTEN |= u32InterruptFlag;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function use to enable UART function and set baud-rate.
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
* @param[in] u32baudrate The baudrate of UART module.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void UART_Open(UART_T* uart, uint32_t u32baudrate)
|
||||
{
|
||||
uint8_t u8UartClkSrcSel;
|
||||
uint32_t u32Clk = 0;
|
||||
uint32_t u32ClkDiv = 0;
|
||||
uint32_t u32Baud_Div;
|
||||
|
||||
u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
|
||||
uart->FUNSEL = UART_FUNC_SEL_UART;
|
||||
uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
|
||||
uart->FIFO = UART_FIFO_RFITL_1BYTE | UART_FIFO_RTSTRGLV_1BYTE;
|
||||
|
||||
if(u8UartClkSrcSel == 0)
|
||||
u32Clk = __XTAL;
|
||||
else if(u8UartClkSrcSel == 1)
|
||||
u32Clk = CLK_GetPLLClockFreq();
|
||||
else if(u8UartClkSrcSel >= 2)
|
||||
u32Clk = __HSI;
|
||||
|
||||
u32ClkDiv = ( (CLK->CLKDIV & CLK_CLKDIV_UARTDIV_Msk) >> CLK_CLKDIV_UARTDIV_Pos );
|
||||
u32Clk = u32Clk/(u32ClkDiv + 1);
|
||||
|
||||
if(u32baudrate != 0) {
|
||||
u32Baud_Div = UART_BAUD_MODE2_DIVIDER(u32Clk, u32baudrate);
|
||||
|
||||
if(u32Baud_Div > 0xFFFF)
|
||||
uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(u32Clk, u32baudrate));
|
||||
else
|
||||
uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
* @param[in] pu8RxBuf The buffer to receive the data of receive FIFO.
|
||||
* @param[in] u32ReadBytes The the read bytes number of data.
|
||||
*
|
||||
* @return u32Count: Receive byte count
|
||||
*
|
||||
*/
|
||||
uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
|
||||
{
|
||||
uint32_t u32Count, u32delayno;
|
||||
|
||||
for(u32Count=0; u32Count < u32ReadBytes; u32Count++) {
|
||||
u32delayno = 0;
|
||||
|
||||
while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) { /* Check RX empty => failed */
|
||||
u32delayno++;
|
||||
if( u32delayno >= 0x40000000 )
|
||||
return FALSE;
|
||||
}
|
||||
pu8RxBuf[u32Count] = uart->DAT; /* Get Data from UART RX */
|
||||
}
|
||||
|
||||
return u32Count;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function use to config UART line setting.
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
* @param[in] u32baudrate The register value of baudrate of UART module.
|
||||
* if u32baudrate = 0, UART baudrate will not change.
|
||||
* @param[in] u32data_width The data length of UART module.
|
||||
* @param[in] u32parity The parity setting (odd/even/none) of UART module.
|
||||
* @param[in] u32stop_bits The stop bit length (1/1.5 bit) of UART module.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
|
||||
{
|
||||
uint8_t u8UartClkSrcSel;
|
||||
uint32_t u32Clk = 0;
|
||||
uint32_t u32ClkDiv = 0;
|
||||
uint32_t u32Baud_Div = 0;
|
||||
|
||||
u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
|
||||
|
||||
if(u8UartClkSrcSel == 0)
|
||||
u32Clk = __XTAL;
|
||||
else if(u8UartClkSrcSel == 1)
|
||||
u32Clk = CLK_GetPLLClockFreq();
|
||||
else if(u8UartClkSrcSel >= 2)
|
||||
u32Clk = __HSI;
|
||||
|
||||
u32ClkDiv = ( (CLK->CLKDIV & CLK_CLKDIV_UARTDIV_Msk) >> CLK_CLKDIV_UARTDIV_Pos );
|
||||
u32Clk = u32Clk/(u32ClkDiv + 1);
|
||||
|
||||
if(u32baudrate != 0) {
|
||||
u32Baud_Div = UART_BAUD_MODE2_DIVIDER(u32Clk, u32baudrate);
|
||||
|
||||
if(u32Baud_Div > 0xFFFF)
|
||||
uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(u32Clk, u32baudrate));
|
||||
else
|
||||
uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
|
||||
}
|
||||
|
||||
uart->LINE = u32data_width | u32parity | u32stop_bits;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function use to set Rx timeout count.
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
* @param[in] u32TOC Rx timeout counter.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
|
||||
{
|
||||
uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk)| (u32TOC);
|
||||
uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
* @param[in] u32Buadrate The baudrate of UART module.
|
||||
* @param[in] u32Direction The direction(transmit:1/receive:0) of UART module in IrDA mode.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
|
||||
{
|
||||
uint8_t u8UartClkSrcSel;
|
||||
uint32_t u32Clk = 0;
|
||||
uint32_t u32ClkDiv = 0;
|
||||
|
||||
u8UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UARTSEL_Msk) >> CLK_CLKSEL1_UARTSEL_Pos;
|
||||
|
||||
if(u8UartClkSrcSel == 0)
|
||||
u32Clk = __XTAL;
|
||||
else if(u8UartClkSrcSel == 1)
|
||||
u32Clk = CLK_GetPLLClockFreq();
|
||||
else if(u8UartClkSrcSel >= 2)
|
||||
u32Clk = __HSI;
|
||||
|
||||
u32ClkDiv = ( (CLK->CLKDIV & CLK_CLKDIV_UARTDIV_Msk) >> CLK_CLKDIV_UARTDIV_Pos );
|
||||
u32Clk = u32Clk/(u32ClkDiv + 1);
|
||||
|
||||
uart->BAUD = UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER(u32Clk, u32Buadrate);
|
||||
|
||||
uart->IRDA &= ~UART_IRDA_TXINV_Msk;
|
||||
uart->IRDA |= UART_IRDA_RXINV_Msk;
|
||||
uart->IRDA = u32Direction ? uart->IRDA | UART_IRDA_TXEN_Msk : uart->IRDA &~ UART_IRDA_TXEN_Msk;
|
||||
uart->FUNSEL = (0x2 << UART_FUNSEL_FUN_SEL_Pos);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief The function is used to set RS485 relative setting.
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
* @param[in] u32Mode The operation mode(NMM/AUD/AAD).
|
||||
* @param[in] u32Addr The RS485 address.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
|
||||
{
|
||||
uart->FUNSEL = UART_FUNC_SEL_RS485;
|
||||
uart->ALTCTL = 0;
|
||||
uart->ALTCTL |= u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief The function is to write data into TX buffer to transmit data by UART.
|
||||
*
|
||||
* @param[in] uart The base address of UART module.
|
||||
* @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO.
|
||||
* @param[in] u32WriteBytes The byte number of data.
|
||||
*
|
||||
* @return u32Count: transfer byte count
|
||||
*/
|
||||
uint32_t UART_Write(UART_T* uart,uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
|
||||
{
|
||||
uint32_t u32Count, u32delayno;
|
||||
|
||||
for(u32Count=0; u32Count != u32WriteBytes; u32Count++) {
|
||||
u32delayno = 0;
|
||||
while((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) == 0) { /* Wait Tx empty and Time-out manner */
|
||||
u32delayno++;
|
||||
if( u32delayno >= 0x40000000 )
|
||||
return FALSE;
|
||||
}
|
||||
uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */
|
||||
}
|
||||
|
||||
return u32Count;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_UART_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_UART_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2012 Nuvoton Technology Corp. ***/
|
||||
|
||||
|
||||
|
||||
@@ -0,0 +1,100 @@
|
||||
/**************************************************************************//**
|
||||
* @file wdt.c
|
||||
* @version V1.00
|
||||
* $Revision: 3 $
|
||||
* $Date: 15/05/28 1:16p $
|
||||
* @brief Mini58 series WDT driver source file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "Mini58Series.h"
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_WDT_Driver WDT Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Mini58_WDT_EXPORTED_FUNCTIONS WDT Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function make WDT module start counting with different time-out interval
|
||||
* @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are:
|
||||
* - \ref WDT_TIMEOUT_2POW4
|
||||
* - \ref WDT_TIMEOUT_2POW6
|
||||
* - \ref WDT_TIMEOUT_2POW8
|
||||
* - \ref WDT_TIMEOUT_2POW10
|
||||
* - \ref WDT_TIMEOUT_2POW12
|
||||
* - \ref WDT_TIMEOUT_2POW14
|
||||
* - \ref WDT_TIMEOUT_2POW16
|
||||
* - \ref WDT_TIMEOUT_2POW18
|
||||
* @param[in] u32ResetDelay Reset delay period while WDT time-out happened. Valid values are:
|
||||
* - \ref WDT_RESET_DELAY_3CLK
|
||||
* - \ref WDT_RESET_DELAY_18CLK
|
||||
* - \ref WDT_RESET_DELAY_130CLK
|
||||
* - \ref WDT_RESET_DELAY_1026CLK
|
||||
* @param[in] u32EnableReset Enable WDT reset system function. Valid values are TRUE and FALSE
|
||||
* @param[in] u32EnableWakeup Enable WDT wake-up system function. Valid values are TRUE and FALSE
|
||||
* @return None
|
||||
*/
|
||||
void WDT_Open(uint32_t u32TimeoutInterval,
|
||||
uint32_t u32ResetDelay,
|
||||
uint32_t u32EnableReset,
|
||||
uint32_t u32EnableWakeup)
|
||||
{
|
||||
|
||||
WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk |
|
||||
(u32EnableReset << WDT_CTL_RSTEN_Pos) |
|
||||
(u32EnableWakeup << WDT_CTL_WKEN_Pos);
|
||||
WDT->ALTCTL = u32ResetDelay;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function stops WDT counting and disable WDT module
|
||||
* @param None
|
||||
* @return None
|
||||
*/
|
||||
void WDT_Close(void)
|
||||
{
|
||||
WDT->CTL = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function enables the WDT time-out interrupt
|
||||
* @param None
|
||||
* @return None
|
||||
*/
|
||||
void WDT_EnableInt(void)
|
||||
{
|
||||
WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk)) | WDT_CTL_INTEN_Msk;
|
||||
return;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief This function disables the WDT time-out interrupt
|
||||
* @param None
|
||||
* @return None
|
||||
*/
|
||||
void WDT_DisableInt(void)
|
||||
{
|
||||
WDT->CTL &= ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_INTEN_Msk);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_WDT_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_WDT_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
@@ -0,0 +1,68 @@
|
||||
/**************************************************************************//**
|
||||
* @file wwdt.c
|
||||
* @version V1.00
|
||||
* $Revision: 1 $
|
||||
* $Date: 15/02/02 3:19p $
|
||||
* @brief Mini58 series WWDT driver source file
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 Nuvoton Technology Corp. All rights reserved.
|
||||
*****************************************************************************/
|
||||
#include "mini58Series.h"
|
||||
|
||||
/** @addtogroup Mini58_Device_Driver Mini58 Device Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
/** @addtogroup Mini58_WWDT_Driver WWDT Driver
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup Mini58_WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief This function make WWDT module start counting with different counter period and compared window value
|
||||
* @param[in] u32PreScale Prescale period for the WWDT counter period. Valid values are:
|
||||
* - \ref WWDT_PRESCALER_1
|
||||
* - \ref WWDT_PRESCALER_2
|
||||
* - \ref WWDT_PRESCALER_4
|
||||
* - \ref WWDT_PRESCALER_8
|
||||
* - \ref WWDT_PRESCALER_16
|
||||
* - \ref WWDT_PRESCALER_32
|
||||
* - \ref WWDT_PRESCALER_64
|
||||
* - \ref WWDT_PRESCALER_128
|
||||
* - \ref WWDT_PRESCALER_192
|
||||
* - \ref WWDT_PRESCALER_256
|
||||
* - \ref WWDT_PRESCALER_384
|
||||
* - \ref WWDT_PRESCALER_512
|
||||
* - \ref WWDT_PRESCALER_768
|
||||
* - \ref WWDT_PRESCALER_1024
|
||||
* - \ref WWDT_PRESCALER_1536
|
||||
* - \ref WWDT_PRESCALER_2048
|
||||
* @param[in] u32CmpValue Window compared value. Valid values are between 0x0 to 0x3F
|
||||
* @param[in] u32EnableInt Enable WWDT interrupt or not. Valid values are \ref TRUE and \ref FALSE
|
||||
* @return None
|
||||
* @note Application can call this function can only once after boot up
|
||||
*/
|
||||
void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt)
|
||||
{
|
||||
WWDT->CTL = u32PreScale |
|
||||
(u32CmpValue << WWDT_CTL_CMPDAT_Pos)|
|
||||
WWDT_CTL_WWDTEN_Msk |
|
||||
(u32EnableInt ? WWDT_CTL_INTEN_Msk : 0);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/*@}*/ /* end of group Mini58_WWDT_EXPORTED_FUNCTIONS */
|
||||
|
||||
/*@}*/ /* end of group Mini58_WWDT_Driver */
|
||||
|
||||
/*@}*/ /* end of group Mini58_Device_Driver */
|
||||
|
||||
/*** (C) COPYRIGHT 2015 Nuvoton Technology Corp. ***/
|
||||
Reference in New Issue
Block a user