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 <span id="projectnumber">Version 4.30</span>
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<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
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<div class="title">MISRA-C:2004 Compliance Exceptions </div> </div>
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<div class="textblock"><p>CMSIS-CORE uses the common coding rules for CMSIS components that are documented under <a href="../../General/html/index.html"><b>Introduction</b></a>.</p>
|
||||
<p>CMSIS-CORE violates the following MISRA-C:2004 rules:</p>
|
||||
<ul>
|
||||
<li>Required Rule 8.5, object/function definition in header file.<br/>
|
||||
Violated since function definitions in header files are used for function inlining'.</li>
|
||||
</ul>
|
||||
<ul>
|
||||
<li>Advisory Rule 12.4, Side effects on right hand side of logical operator.<br/>
|
||||
Violated because volatile is used for core register definitions.</li>
|
||||
</ul>
|
||||
<ul>
|
||||
<li>Advisory Rule 14.7, Return statement before end of function.<br/>
|
||||
Violated to simplify code logic.</li>
|
||||
</ul>
|
||||
<ul>
|
||||
<li>Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br/>
|
||||
Violated since unions are used for effective representation of core registers.</li>
|
||||
</ul>
|
||||
<ul>
|
||||
<li>Advisory Rule 19.4, Disallowed definition for macro.<br/>
|
||||
Violated since macros are used for assembler keywords.</li>
|
||||
</ul>
|
||||
<ul>
|
||||
<li>Advisory Rule 19.7, Function-like macro defined.<br/>
|
||||
Violated since function-like macros are used to generate more efficient code.</li>
|
||||
</ul>
|
||||
<ul>
|
||||
<li>Advisory Rule 19.16, all preprocessing directives must be valid.<br/>
|
||||
Violated to set default settings for macros.</li>
|
||||
</ul>
|
||||
<p><device>.h files generated by <b>SVDConv.exe</b> violate the following MISRA-C:2004 rules:</p>
|
||||
<ul>
|
||||
<li>Advisory Rule 20.2, Re-use of C90 identifier pattern.<br/>
|
||||
Violated since CMSIS macros begin with '__'. Since CMSIS is developed and verified with various compilers this approach is acceptable and avoids conflicts with user symbols.</li>
|
||||
</ul>
|
||||
<ul>
|
||||
<li>Advisory Rule 19.1, Declaration before #include.<br/>
|
||||
Violated since Interrupt Number Definition Type (IRQn_Type) must be defined before including the core header file. </li>
|
||||
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<li class="footer">Generated on Tue Oct 27 2015 14:35:21 for CMSIS-CORE by ARM Ltd. All rights reserved.
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<title>CMSIS-CORE: Register Mapping</title>
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 <span id="projectnumber">Version 4.30</span>
|
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</div>
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<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
|
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<div class="title">Register Mapping </div> </div>
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<div class="textblock"><p>The table below associates some common register names used in CMSIS to the register names used in Technical Reference Manuals.</p>
|
||||
<table class="cmtable" summary="Register Mapping">
|
||||
<tr>
|
||||
<th>CMSIS Register Name </th><th>Cortex-M3, Cortex-M4, and Cortex-M7 </th><th>Cortex-M0 and Cortex-M0+ </th><th>Register Name </th></tr>
|
||||
<tr>
|
||||
<th colspan="4">Nested Vectored Interrupt Controller (NVIC) Register Access </th></tr>
|
||||
<tr>
|
||||
<td>NVIC->ISER[] </td><td>NVIC_ISER0..7 </td><td>ISER </td><td>Interrupt Set-Enable Registers </td></tr>
|
||||
<tr>
|
||||
<td>NVIC->ICER[] </td><td>NVIC_ICER0..7 </td><td>ICER </td><td>Interrupt Clear-Enable Registers </td></tr>
|
||||
<tr>
|
||||
<td>NVIC->ISPR[] </td><td>NVIC_ISPR0..7 </td><td>ISPR </td><td>Interrupt Set-Pending Registers </td></tr>
|
||||
<tr>
|
||||
<td>NVIC->ICPR[] </td><td>NVIC_ICPR0..7 </td><td>ICPR </td><td>Interrupt Clear-Pending Registers </td></tr>
|
||||
<tr>
|
||||
<td>NVIC->IABR[] </td><td>NVIC_IABR0..7 </td><td>- </td><td>Interrupt Active Bit Register </td></tr>
|
||||
<tr>
|
||||
<td>NVIC->IP[] </td><td>NVIC_IPR0..59 </td><td>IPR0..7 </td><td>Interrupt Priority Register </td></tr>
|
||||
<tr>
|
||||
<td>NVIC->STIR </td><td>STIR </td><td>- </td><td>Software Triggered Interrupt Register </td></tr>
|
||||
<tr>
|
||||
<th colspan="4">System Control Block (SCB) Register Access </th></tr>
|
||||
<tr>
|
||||
<td>SCB->CPUID </td><td>CPUID </td><td>CPUID </td><td>CPUID Base Register </td></tr>
|
||||
<tr>
|
||||
<td>SCB->ICSR </td><td>ICSR </td><td>ICSR </td><td>Interrupt Control and State Register </td></tr>
|
||||
<tr>
|
||||
<td>SCB->VTOR </td><td>VTOR </td><td>- </td><td>Vector Table Offset Register </td></tr>
|
||||
<tr>
|
||||
<td>SCB->AIRCR </td><td>AIRCR </td><td>AIRCR </td><td>Application Interrupt and Reset Control Register </td></tr>
|
||||
<tr>
|
||||
<td>SCB->SCR </td><td>SCR </td><td>SCR </td><td>System Control Register </td></tr>
|
||||
<tr>
|
||||
<td>SCB->CCR </td><td>CCR </td><td>CCR </td><td>Configuration and Control Register </td></tr>
|
||||
<tr>
|
||||
<td>SCB->SHP[] </td><td>SHPR1..3 </td><td>SHPR2..3 </td><td>System Handler Priority Registers </td></tr>
|
||||
<tr>
|
||||
<td>SCB->SHCSR </td><td>SHCSR </td><td>SHCSR </td><td>System Handler Control and State Register </td></tr>
|
||||
<tr>
|
||||
<td>SCB->CFSR </td><td>CFSR </td><td>- </td><td>Configurable Fault Status Registers </td></tr>
|
||||
<tr>
|
||||
<td>SCB->HFSR </td><td>HFSR </td><td>- </td><td>HardFault Status Register </td></tr>
|
||||
<tr>
|
||||
<td>SCB->DFSR </td><td>DFSR </td><td>- </td><td>Debug Fault Status Register </td></tr>
|
||||
<tr>
|
||||
<td>SCB->MMFAR </td><td>MMFAR </td><td>- </td><td>MemManage Fault Address Register </td></tr>
|
||||
<tr>
|
||||
<td>SCB->BFAR </td><td>BFAR </td><td>- </td><td>BusFault Address Register </td></tr>
|
||||
<tr>
|
||||
<td>SCB->AFSR </td><td>AFSR </td><td>- </td><td>Auxiliary Fault Status Register </td></tr>
|
||||
<tr>
|
||||
<td>SCB->PFR[] </td><td>ID_PFR0..1 </td><td>- </td><td>Processor Feature Registers </td></tr>
|
||||
<tr>
|
||||
<td>SCB->DFR </td><td>ID_DFR0 </td><td>- </td><td>Debug Feature Register </td></tr>
|
||||
<tr>
|
||||
<td>SCB->ADR </td><td>ID_AFR0 </td><td>- </td><td>Auxiliary Feature Register </td></tr>
|
||||
<tr>
|
||||
<td>SCB->MMFR[] </td><td>ID_MMFR0..3 </td><td>- </td><td>Memory Model Feature Registers </td></tr>
|
||||
<tr>
|
||||
<td>SCB->ISAR[] </td><td>ID_ISAR0..4 </td><td>- </td><td>Instruction Set Attributes Registers </td></tr>
|
||||
<tr>
|
||||
<td>SCB->CPACR </td><td>CPACR </td><td>- </td><td>Coprocessor Access Control Register </td></tr>
|
||||
<tr>
|
||||
<th colspan="4">System Control and ID Registers not in the SCB (SCnSCB) Register Access </th></tr>
|
||||
<tr>
|
||||
<td>SCnSCB->ICTR </td><td>ICTR </td><td>- </td><td>Interrupt Controller Type Register </td></tr>
|
||||
<tr>
|
||||
<td>SCnSCB->ACTLR </td><td>ACTLR </td><td>- </td><td>Auxiliary Control Register </td></tr>
|
||||
<tr>
|
||||
<th colspan="4">System Timer (SysTick) Control and Status Register Access </th></tr>
|
||||
<tr>
|
||||
<td>SysTick->CTRL </td><td>STCSR </td><td>SYST_CSR </td><td>SysTick Control and Status Register </td></tr>
|
||||
<tr>
|
||||
<td>SysTick->LOAD </td><td>STRVR </td><td>SYST_RVR </td><td>SysTick Reload Value Register </td></tr>
|
||||
<tr>
|
||||
<td>SysTick->VAL </td><td>STCVR </td><td>SYST_CVR </td><td>SysTick Current Value Register </td></tr>
|
||||
<tr>
|
||||
<td>SysTick->CALIB </td><td>STCR </td><td>SYST_CALIB </td><td>SysTick Calibaration Value Register </td></tr>
|
||||
<tr>
|
||||
<th colspan="4">Data Watchpoint and Trace (DWT) Register Access </th></tr>
|
||||
<tr>
|
||||
<td>DWT->CTRL </td><td>DWT_CTRL </td><td>- </td><td>Control Register </td></tr>
|
||||
<tr>
|
||||
<td>DWT->CYCCNT </td><td>DWT_CYCCNT </td><td>- </td><td>Cycle Count Register </td></tr>
|
||||
<tr>
|
||||
<td>DWT->CPICNT </td><td>DWT_CPICNT </td><td>- </td><td>CPI Count Register </td></tr>
|
||||
<tr>
|
||||
<td>DWT->EXCCNT </td><td>DWT_EXCCNT </td><td>- </td><td>Exception Overhead Count Register </td></tr>
|
||||
<tr>
|
||||
<td>DWT->SLEEPCNT </td><td>DWT_SLEEPCNT </td><td>- </td><td>Sleep Count Register </td></tr>
|
||||
<tr>
|
||||
<td>DWT->LSUCNT </td><td>DWT_LSUCNT </td><td>- </td><td>LSU Count Register </td></tr>
|
||||
<tr>
|
||||
<td>DWT->FOLDCNT </td><td>DWT_FOLDCNT </td><td>- </td><td>Folded-instruction Count Register </td></tr>
|
||||
<tr>
|
||||
<td>DWT->PCSR </td><td>DWT_PCSR </td><td>- </td><td>Program Counter Sample Register </td></tr>
|
||||
<tr>
|
||||
<td>DWT->COMP0..3 </td><td>DWT_COMP0..3 </td><td>- </td><td>Comparator Register 0..3 </td></tr>
|
||||
<tr>
|
||||
<td>DWT->MASK0..3 </td><td>DWT_MASK0..3 </td><td>- </td><td>Mask Register 0..3 </td></tr>
|
||||
<tr>
|
||||
<td>DWT->FUNCTION0..3 </td><td>DWT_FUNCTION0..3 </td><td>- </td><td>Function Register 0..3 </td></tr>
|
||||
<tr>
|
||||
<th colspan="4">Instrumentation Trace Macrocell (ITM) Register Access </th></tr>
|
||||
<tr>
|
||||
<td>ITM->PORT[] </td><td>ITM_STIM0..31 </td><td>- </td><td>Stimulus Port Registers </td></tr>
|
||||
<tr>
|
||||
<td>ITM->TER </td><td>ITM_TER </td><td>- </td><td>Trace Enable Register </td></tr>
|
||||
<tr>
|
||||
<td>ITM->TPR </td><td>ITM_TPR </td><td>- </td><td>ITM Trace Privilege Register </td></tr>
|
||||
<tr>
|
||||
<td>ITM->TCR </td><td>ITM_TCR </td><td>- </td><td>Trace Control Register </td></tr>
|
||||
<tr>
|
||||
<th colspan="4">Trace Port Interface (TPIU) Register Access </th></tr>
|
||||
<tr>
|
||||
<td>TPI->SSPSR </td><td>TPIU_SSPR </td><td>- </td><td>Supported Parallel Port Size Register </td></tr>
|
||||
<tr>
|
||||
<td>TPI->CSPSR </td><td>TPIU_CSPSR </td><td>- </td><td>Current Parallel Port Size Register </td></tr>
|
||||
<tr>
|
||||
<td>TPI->ACPR </td><td>TPIU_ACPR </td><td>- </td><td>Asynchronous Clock Prescaler Register </td></tr>
|
||||
<tr>
|
||||
<td>TPI->SPPR </td><td>TPIU_SPPR </td><td>- </td><td>Selected Pin Protocol Register </td></tr>
|
||||
<tr>
|
||||
<td>TPI->FFSR </td><td>TPIU_FFSR </td><td>- </td><td>Formatter and Flush Status Register </td></tr>
|
||||
<tr>
|
||||
<td>TPI->FFCR </td><td>TPIU_FFCR </td><td>- </td><td>Formatter and Flush Control Register </td></tr>
|
||||
<tr>
|
||||
<td>TPI->FSCR </td><td>TPIU_FSCR </td><td>- </td><td>Formatter Synchronization Counter Register </td></tr>
|
||||
<tr>
|
||||
<td>TPI->TRIGGER </td><td>TRIGGER </td><td>- </td><td>TRIGGER </td></tr>
|
||||
<tr>
|
||||
<td>TPI->FIFO0 </td><td>FIFO data 0 </td><td>- </td><td>Integration ETM Data </td></tr>
|
||||
<tr>
|
||||
<td>TPI->ITATBCTR2 </td><td>ITATBCTR2 </td><td>- </td><td>ITATBCTR2 </td></tr>
|
||||
<tr>
|
||||
<td>TPI->ITATBCTR0 </td><td>ITATBCTR0 </td><td>- </td><td>ITATBCTR0 </td></tr>
|
||||
<tr>
|
||||
<td>TPI->FIFO1 </td><td>FIFO data 1 </td><td>- </td><td>Integration ITM Data </td></tr>
|
||||
<tr>
|
||||
<td>TPI->ITCTRL </td><td>TPIU_ITCTRL </td><td>- </td><td>Integration Mode Control </td></tr>
|
||||
<tr>
|
||||
<td>TPI->CLAIMSET </td><td>CLAIMSET </td><td>- </td><td>Claim tag set </td></tr>
|
||||
<tr>
|
||||
<td>TPI->CLAIMCLR </td><td>CLAIMCLR </td><td>- </td><td>Claim tag clear </td></tr>
|
||||
<tr>
|
||||
<td>TPI->DEVID </td><td>TPIU_DEVID </td><td>- </td><td>TPIU_DEVID </td></tr>
|
||||
<tr>
|
||||
<td>TPI->DEVTYPE </td><td>TPIU_DEVTYPE </td><td>- </td><td>TPIU_DEVTYPE </td></tr>
|
||||
<tr>
|
||||
<th colspan="4">Memory Protection Unit (MPU) Register Access </th></tr>
|
||||
<tr>
|
||||
<td>MPU->TYPE </td><td>MPU_TYPE </td><td>- </td><td>MPU Type Register </td></tr>
|
||||
<tr>
|
||||
<td>MPU->CTRL </td><td>MPU_CTRL </td><td>- </td><td>MPU Control Register </td></tr>
|
||||
<tr>
|
||||
<td>MPU->RNR </td><td>MPU_RNR </td><td>- </td><td>MPU Region Number Register </td></tr>
|
||||
<tr>
|
||||
<td>MPU->RBAR </td><td>MPU_RBAR </td><td>- </td><td>MPU Region Base Address Register </td></tr>
|
||||
<tr>
|
||||
<td>MPU->RASR </td><td>MPU_RASR </td><td>- </td><td>MPU Region Attribute and Size Register </td></tr>
|
||||
<tr>
|
||||
<td>MPU->RBAR_A1..3 </td><td>MPU_RBAR_A1..3 </td><td>- </td><td>MPU alias Register </td></tr>
|
||||
<tr>
|
||||
<td>MPU->RSAR_A1..3 </td><td>MPU_RSAR_A1..3 </td><td>- </td><td>MPU alias Register </td></tr>
|
||||
<tr>
|
||||
<th colspan="4">Floating Point Unit (FPU) Register Access [only Cortex-M4 and Cortex-M7 both with FPU] </th></tr>
|
||||
<tr>
|
||||
<td>FPU->FPCCR </td><td>FPCCR </td><td>- </td><td>FP Context Control Register </td></tr>
|
||||
<tr>
|
||||
<td>FPU->FPCAR </td><td>FPCAR </td><td>- </td><td>FP Context Address Register </td></tr>
|
||||
<tr>
|
||||
<td>FPU->FPDSCR </td><td>FPDSCR </td><td>- </td><td>FP Default Status Control Register </td></tr>
|
||||
<tr>
|
||||
<td>FPU->MVFR0..1 </td><td>MVFR0..1 </td><td>- </td><td>Media and VFP Feature Registers </td></tr>
|
||||
</table>
|
||||
</div></div><!-- contents -->
|
||||
</div><!-- doc-content -->
|
||||
<!-- start footer part -->
|
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<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
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||||
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|
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<li class="footer">Generated on Tue Oct 27 2015 14:35:21 for CMSIS-CORE by ARM Ltd. All rights reserved.
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||||
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<a href="http://www.doxygen.org/index.html">
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<td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
|
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<td style="padding-left: 0.5em;">
|
||||
<div id="projectname">CMSIS-CORE
|
||||
 <span id="projectnumber">Version 4.30</span>
|
||||
</div>
|
||||
<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
|
||||
</td>
|
||||
</tr>
|
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</tbody>
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</table>
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<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div>
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<div class="header">
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<div class="headertitle">
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<div class="title">Template Files </div> </div>
|
||||
</div><!--header-->
|
||||
<div class="contents">
|
||||
<div class="textblock"><p>ARM supplies CMSIS-CORE template files for the all supported Cortex-M processors and various compiler vendors. Refer to the list of <a class="el" href="index.html#tested_tools_sec">Tested and Verified Toolchains</a> for compliance. These template files include the following:</p>
|
||||
<ul>
|
||||
<li>Register names of the Core Peripherals and names of the Core Exception Vectors.</li>
|
||||
<li>Functions to access core peripherals, special CPU instructions and SIMD instructions (for Cortex-M4 and Cortex-M7)</li>
|
||||
<li>Generic startup code and system configuration code.</li>
|
||||
</ul>
|
||||
<p>The detailed file structure of the CMSIS-CORE is shown in the following picture.</p>
|
||||
<div class="image">
|
||||
<img src="CMSIS_CORE_Files.png" alt="CMSIS_CORE_Files.png"/>
|
||||
<div class="caption">
|
||||
CMSIS-CORE File Structure</div></div>
|
||||
<h1><a class="anchor" id="template_files_sec"></a>
|
||||
Template Files</h1>
|
||||
<p>The CMSIS-CORE template files should be extended by the silicon vendor to reflect the actual device and device peripherals. Silicon vendors add in this context the:</p>
|
||||
<ul>
|
||||
<li><b>Device Peripheral Access Layer</b> that provides definitions for device-specific peripherals.</li>
|
||||
<li><b>Access Functions for Peripherals</b> (optional) that provides additional helper functions to access device-specific peripherals.</li>
|
||||
<li><b>Interrupt vectors</b> in the startup file that are device specific.</li>
|
||||
</ul>
|
||||
<table class="cmtable">
|
||||
<tr>
|
||||
<th>Template File </th><th>Description </th></tr>
|
||||
<tr>
|
||||
<td>.\Device\_Template_Vendor\Vendor\Device\Source\ARM\startup_Device.s </td><td>Startup file template for ARM C/C++ Compiler. </td></tr>
|
||||
<tr>
|
||||
<td>.\Device\_Template_Vendor\Vendor\Device\Source\GCC\startup_Device.s </td><td>Startup file template for GNU GCC ARM Embedded Compiler. </td></tr>
|
||||
<tr>
|
||||
<td>.\Device\_Template_Vendor\Vendor\Device\Source\IAR\startup_Device.s </td><td>Startup file template for IAR C/C++ Compiler. </td></tr>
|
||||
<tr>
|
||||
<td>.\Device\_Template_Vendor\Vendor\Device\Source\system_Device.c </td><td>Generic system_Device.c file for system configuration (i.e. processor clock and memory bus system). </td></tr>
|
||||
<tr>
|
||||
<td>.\Device\_Template_Vendor\Vendor\Device\Include\Device.h </td><td>Generic device header file. Needs to be extended with the device-specific peripheral registers. Optionally functions that access the peripherals can be part of that file. </td></tr>
|
||||
<tr>
|
||||
<td>.\Device\_Template_Vendor\Vendor\Device\Include\system_Device.h </td><td>Generic system device configuration include file. </td></tr>
|
||||
</table>
|
||||
<p>In addition ARM provides the following core header files that do not need any modifications.</p>
|
||||
<table class="cmtable">
|
||||
<tr>
|
||||
<th>Core Header Files </th><th>Description </th></tr>
|
||||
<tr>
|
||||
<td><b>core_<cpu>.h</b> </td><td>Defines the core peripherals and provides helper functions that access the core registers. This file is available for all supported processors:<ul>
|
||||
<li>core_cm0.h: for the Cortex-M0 processor</li>
|
||||
<li>core_cm0plus.h: for the Cortex-M0+ processor</li>
|
||||
<li>core_cm3.h: for the Cortex-M3 processor</li>
|
||||
<li>core_cm4.h: for the Cortex-M4 processor</li>
|
||||
<li>core_cm7.h: for the Cortex-M7 processor</li>
|
||||
<li>core_sc000.h: for the SecurCore SC000 processor</li>
|
||||
<li>core_sc300.h: for the SecurCore SC300 processor </li>
|
||||
</ul>
|
||||
</td></tr>
|
||||
<tr>
|
||||
<td><b>core_cmInstr.h</b> </td><td>Defines intrinsic functions to access special Cortex-M instructions. </td></tr>
|
||||
<tr>
|
||||
<td><b>core_cmFunc.h</b> </td><td>Defines functions to access the Cortex-M core peripherals. </td></tr>
|
||||
<tr>
|
||||
<td><b>core_cm4_simd.h</b> </td><td>Defines intrinsic functions to access the SIMD instructions for Cortex-M4 and Cortex-M7. </td></tr>
|
||||
</table>
|
||||
<h1><a class="anchor" id="adapt_template_files_sec"></a>
|
||||
Adaption of Template Files to Devices</h1>
|
||||
<p>Copy the complete folder including files and replace:</p>
|
||||
<ul>
|
||||
<li>folder name 'Vendor' with the abbreviation for the device vendor e.g.: NXP.</li>
|
||||
<li>folder name 'Device' with the specific device name e.g.: LPC17xx.</li>
|
||||
<li>in the filenames 'Device' with the specific device name e.g.: LPC17xx.</li>
|
||||
</ul>
|
||||
<p>Each template file contains comments that start with <b>ToDo:</b> that describe a required modification. The template files contain placeholders:</p>
|
||||
<table class="cmtable">
|
||||
<tr>
|
||||
<th>Placeholder </th><th>Replaced with </th></tr>
|
||||
<tr>
|
||||
<td><Device> </td><td>the specific device name or device family name; i.e. LPC17xx. </td></tr>
|
||||
<tr>
|
||||
<td><DeviceInterrupt> </td><td>a specific interrupt name of the device; i.e. TIM1 for Timer 1. </td></tr>
|
||||
<tr>
|
||||
<td><DeviceAbbreviation> </td><td>short name or abbreviation of the device family; i.e. LPC. </td></tr>
|
||||
<tr>
|
||||
<td>Cortex-M# </td><td>the specific Cortex-M processor name; i.e. Cortex-M3. </td></tr>
|
||||
</table>
|
||||
<p>The adaption of the template files is described in detail on the following pages:</p>
|
||||
<ul>
|
||||
<li><a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a></li>
|
||||
<li><a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a></li>
|
||||
<li><a class="el" href="device_h_pg.html">Device Header File <device.h></a> </li>
|
||||
</ul>
|
||||
</div></div><!-- contents -->
|
||||
</div><!-- doc-content -->
|
||||
<!-- start footer part -->
|
||||
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
|
||||
<ul>
|
||||
<li class="footer">Generated on Tue Oct 27 2015 14:35:21 for CMSIS-CORE by ARM Ltd. All rights reserved.
|
||||
<!--
|
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<a href="http://www.doxygen.org/index.html">
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.2
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|
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|
||||
var _templates_pg =
|
||||
[
|
||||
[ "Template Files", "_templates_pg.html#template_files_sec", null ],
|
||||
[ "Adaption of Template Files to Devices", "_templates_pg.html#adapt_template_files_sec", null ],
|
||||
[ "Startup File startup_<device>.s", "startup_s_pg.html", [
|
||||
[ "startup_Device.s Template File", "startup_s_pg.html#startup_s_sec", null ]
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[ "System Configuration Files system_<device>.c and system_<device>.h", "system_c_pg.html", [
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[ "system_Device.c Template File", "system_c_pg.html#system_Device_sec", null ],
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[ "system_Device.h Template File", "system_c_pg.html#system_Device_h_sec", null ]
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[ "Device Header File <device.h>", "device_h_pg.html", [
|
||||
[ "Interrupt Number Definition", "device_h_pg.html#interrupt_number_sec", null ],
|
||||
[ "Configuration of the Processor and Core Peripherals", "device_h_pg.html#core_config_sect", null ],
|
||||
[ "CMSIS Version and Processor Information", "device_h_pg.html#core_version_sect", null ],
|
||||
[ "Device Peripheral Access Layer", "device_h_pg.html#device_access", null ],
|
||||
[ "Device.h Template File", "device_h_pg.html#device_h_sec", null ]
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||||
] ]
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||||
];
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||||
@@ -0,0 +1,169 @@
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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||||
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<title>Using CMSIS with generic ARM Processors</title>
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<title>CMSIS-CORE: Using CMSIS with generic ARM Processors</title>
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$(document).ready(initResizable);
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|
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|
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<td style="padding-left: 0.5em;">
|
||||
<div id="projectname">CMSIS-CORE
|
||||
 <span id="projectnumber">Version 4.30</span>
|
||||
</div>
|
||||
<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
|
||||
</td>
|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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<li><a href="index.html"><span>Main Page</span></a></li>
|
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|
||||
<li><a href="modules.html"><span>Reference</span></a></li>
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|
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|
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|
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|
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|
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<div id="side-nav" class="ui-resizable side-nav-resizable">
|
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|
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|
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<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div>
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<div class="header">
|
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<div class="headertitle">
|
||||
<div class="title">Using CMSIS with generic ARM Processors </div> </div>
|
||||
</div><!--header-->
|
||||
<div class="contents">
|
||||
<div class="textblock"><p>ARM provides CMSIS-CORE files for the supported ARM Processors and for various compiler vendors. These files can be used when standard ARM processors should be used in a project. The table below lists the folder and device names of the ARM processors.</p>
|
||||
<table class="cmtable">
|
||||
<tr>
|
||||
<th>Folder </th><th>Processor </th><th>Description </th></tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM0" </td><td>Cortex-M0 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M0 processor. The device name is ARMCM0 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM0.h>. </td></tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM0plus" </td><td>Cortex-M0+ </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M0+ processor. The device name is ARMCM0plus and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM0plus.h>. </td></tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM3" </td><td>Cortex-M3 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M3 processor. The device name is ARMCM3 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM3.h>. </td></tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM4" </td><td>Cortex-M4 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M4 processor. The device name is ARMCM4 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM4.h>. </td></tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM7" </td><td>Cortex-M7 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the Cortex-M7 processor. The device name is ARMCM7 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMCM7.h>. </td></tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMSC000" </td><td>SecurCore SC000 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the SecurCore SC000 processor. The device name is ARMSC000 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMSC000.h>. </td></tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMSC300" </td><td>SecurCore SC300 </td><td>Contains <b>Include</b> and <b>Source</b> template files configured for the SecurCore SC300 processor. The device name is ARMSC300 and the name of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is <ARMSC300.h>. </td></tr>
|
||||
</table>
|
||||
<h1><a class="anchor" id="Using_ARM_Lib_sec"></a>
|
||||
Create generic Libraries with CMSIS</h1>
|
||||
<p>The CMSIS Processor and Core Peripheral files allow also to create generic libraries. The <a href="../../DSP/html/index.html"><b>CMSIS-DSP</b> </a> Libraries are an example for such a generic library.</p>
|
||||
<p>To build a generic Library set the define <b><b>CMSIS_GENERIC</b> and include the relevant <b>core_<cpu>.h</b> CMSIS CPU & Core Access header file for the processor. The define <b></b>CMSIS_GENERIC</b> disables device-dependent features such as the <b>SysTick</b> timer and the <b>Interrupt System</b>. Refer to <a class="el" href="device_h_pg.html#core_config_sect">Configuration of the Processor and Core Peripherals</a> for a list of the available <b>core_<cpu>.h</b> header files.</p>
|
||||
<p><b>Example:</b> </p>
|
||||
<p>The following code section shows the usage of the <b>core_<cpu>.h</b> header files to build a generic library for Cortex-M0, Cortex-M3, Cortex-M4, or Cortex-M7. To select the processor, the source code uses the define <b>CORTEX_M7</b>, <b>CORTEX_M4</b>, <b>CORTEX_M3</b>, <b>CORTEX_M0</b>, or <b>CORTEX_M0PLUS</b>. By using this header file, the source code can access the functions for <a class="el" href="group___core___register__gr.html">Core Register Access</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html">Intrinsic Functions for CPU Instructions</a>, <a class="el" href="group__intrinsic___s_i_m_d__gr.html">Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</a>, and <a class="el" href="group___i_t_m___debug__gr.html">Debug Access</a>.</p>
|
||||
<div class="fragment"><div class="line"><span class="preprocessor">#define __CMSIS_GENERIC </span><span class="comment">/* disable NVIC and Systick functions */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor">#if defined (CORTEX_M7)</span></div>
|
||||
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|
||||
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|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #include "core_cm4.h"</span></div>
|
||||
<div class="line"><span class="preprocessor">#elif defined (CORTEX_M3)</span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #include "core_cm3.h"</span></div>
|
||||
<div class="line"><span class="preprocessor">#elif defined (CORTEX_M0)</span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #include "core_cm0.h"</span></div>
|
||||
<div class="line"><span class="preprocessor">#elif defined (CORTEX_M0PLUS)</span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #include "core_cm0plus.h"</span></div>
|
||||
<div class="line"><span class="preprocessor">#else</span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor"> #error "Processor not specified or unsupported."</span></div>
|
||||
<div class="line"><span class="preprocessor">#endif</span></div>
|
||||
</div><!-- fragment --> </div></div><!-- contents -->
|
||||
</div><!-- doc-content -->
|
||||
<!-- start footer part -->
|
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<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
|
||||
<ul>
|
||||
<li class="navelem"><a class="el" href="_using_pg.html">Using CMSIS in Embedded Applications</a></li>
|
||||
<li class="footer">Generated on Tue Oct 27 2015 14:35:21 for CMSIS-CORE by ARM Ltd. All rights reserved.
|
||||
<!--
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<a href="http://www.doxygen.org/index.html">
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|
||||
<title>CMSIS-CORE: Basic CMSIS Example</title>
|
||||
<link href="tabs.css" rel="stylesheet" type="text/css"/>
|
||||
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<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
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|
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|
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|
||||
<td style="padding-left: 0.5em;">
|
||||
<div id="projectname">CMSIS-CORE
|
||||
 <span id="projectnumber">Version 4.30</span>
|
||||
</div>
|
||||
<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
|
||||
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|
||||
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|
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<div class="fragment"><div class="line"><span class="preprocessor">#include <stm32f10x.h></span> <span class="comment">// File name depends on device used</span></div>
|
||||
<div class="line"> </div>
|
||||
<div class="line">uint32_t <span class="keyword">volatile</span> msTicks; <span class="comment">// Counter for millisecond Interval</span></div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"><span class="keywordtype">void</span> SysTick_Handler (<span class="keywordtype">void</span>) { <span class="comment">// SysTick Interrupt Handler</span></div>
|
||||
<div class="line"> msTicks++; <span class="comment">// Increment Counter</span></div>
|
||||
<div class="line">}</div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"><span class="keywordtype">void</span> WaitForTick (<span class="keywordtype">void</span>) {</div>
|
||||
<div class="line"> uint32_t curTicks;</div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"> curTicks = msTicks; <span class="comment">// Save Current SysTick Value</span></div>
|
||||
<div class="line"> <span class="keywordflow">while</span> (msTicks == curTicks) { <span class="comment">// Wait for next SysTick Interrupt</span></div>
|
||||
<div class="line"> <a class="code" href="group__intrinsic___c_p_u__gr.html#gad3efec76c3bfa2b8528ded530386c563" title="Wait For Event.">__WFE</a> (); <span class="comment">// Power-Down until next Event/Interrupt</span></div>
|
||||
<div class="line"> }</div>
|
||||
<div class="line">}</div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"><span class="keywordtype">void</span> TIM1_UP_IRQHandler (<span class="keywordtype">void</span>) { <span class="comment">// Timer Interrupt Handler</span></div>
|
||||
<div class="line"> ; <span class="comment">// Add user code here</span></div>
|
||||
<div class="line">}</div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"><span class="keywordtype">void</span> timer1_init(<span class="keywordtype">int</span> frequency) { <span class="comment">// Set up Timer (device specific)</span></div>
|
||||
<div class="line"> <a class="code" href="group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798" title="Set the priority for an interrupt.">NVIC_SetPriority</a> (TIM1_UP_IRQn, 1); <span class="comment">// Set Timer priority</span></div>
|
||||
<div class="line"> <a class="code" href="group___n_v_i_c__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f" title="Enable an external interrupt.">NVIC_EnableIRQ</a> (TIM1_UP_IRQn); <span class="comment">// Enable Timer Interrupt</span></div>
|
||||
<div class="line">}</div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"><span class="keywordtype">void</span> Device_Initialization (<span class="keywordtype">void</span>) { <span class="comment">// Configure & Initialize MCU</span></div>
|
||||
<div class="line"> <span class="keywordflow">if</span> (<a class="code" href="group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427" title="System Tick Timer Configuration.">SysTick_Config</a> (<a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6" title="Variable to hold the system core clock value.">SystemCoreClock</a> / 1000)) { <span class="comment">// SysTick 1mSec</span></div>
|
||||
<div class="line"> : <span class="comment">// Handle Error </span></div>
|
||||
<div class="line"> }</div>
|
||||
<div class="line"> timer1_init (); <span class="comment">// setup device-specific timer</span></div>
|
||||
<div class="line">}</div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"><span class="comment">// The processor clock is initialized by CMSIS startup + system file</span></div>
|
||||
<div class="line"><span class="keywordtype">void</span> main (<span class="keywordtype">void</span>) { <span class="comment">// user application starts here</span></div>
|
||||
<div class="line"> Device_Initialization (); <span class="comment">// Configure & Initialize MCU</span></div>
|
||||
<div class="line"> <span class="keywordflow">while</span> (1) { <span class="comment">// Endless Loop (the Super-Loop)</span></div>
|
||||
<div class="line"> <a class="code" href="group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013" title="Globally disables interrupts and configurable fault handlers.">__disable_irq</a> (); <span class="comment">// Disable all interrupts</span></div>
|
||||
<div class="line"> Get_InputValues (); <span class="comment">// Read Values</span></div>
|
||||
<div class="line"> <a class="code" href="group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27" title="Globally enables interrupts and configurable fault handlers.">__enable_irq</a> (); <span class="comment">// Enable all interrupts </span></div>
|
||||
<div class="line"> Calculation_Response (); <span class="comment">// Calculate Results</span></div>
|
||||
<div class="line"> Output_Response (); <span class="comment">// Output Results</span></div>
|
||||
<div class="line"> WaitForTick (); <span class="comment">// Synchronize to SysTick Timer</span></div>
|
||||
<div class="line"> }</div>
|
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 <span id="projectnumber">Version 4.30</span>
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<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
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<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div>
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<div class="title">Using Interrupt Vector Remap </div> </div>
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||||
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||||
<div class="contents">
|
||||
<div class="textblock"><p>Most Cortex-M processors provide VTOR register for remapping interrupt vectors. The following example shows a typical use case where the interrupt vectors are copied to RAM and the SysTick_Handler is replaced.</p>
|
||||
<div class="fragment"><div class="line"><span class="preprocessor">#include "ARMCM3.h"</span> <span class="comment">// Device header</span></div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"><span class="comment">/* externals from startup_ARMCM3.s */</span></div>
|
||||
<div class="line"><span class="keyword">extern</span> uint32_t __Vectors[]; <span class="comment">/* vector table ROM */</span></div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"><span class="preprocessor">#define VECTORTABLE_SIZE (256) </span><span class="comment">/* size Cortex-M3 vector table */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define VECTORTABLE_ALIGNMENT (0x100ul) </span><span class="comment">/* 16 Cortex + 32 ARMCM3 = 48 words */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span> <span class="comment">/* next power of 2 = 256 */</span></div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"><span class="comment">/* new vector table in RAM */</span></div>
|
||||
<div class="line">uint32_t vectorTable_RAM[VECTORTABLE_SIZE] __attribute__(( aligned (VECTORTABLE_ALIGNMENT) ));</div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"><span class="comment">/*----------------------------------------------------------------------------</span></div>
|
||||
<div class="line"><span class="comment"> SysTick_Handler</span></div>
|
||||
<div class="line"><span class="comment"> *----------------------------------------------------------------------------*/</span></div>
|
||||
<div class="line"><span class="keyword">volatile</span> uint32_t msTicks = 0; <span class="comment">/* counts 1ms timeTicks */</span></div>
|
||||
<div class="line"><span class="keywordtype">void</span> SysTick_Handler(<span class="keywordtype">void</span>) {</div>
|
||||
<div class="line"> msTicks++; <span class="comment">/* increment counter */</span></div>
|
||||
<div class="line">}</div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"><span class="comment">/*----------------------------------------------------------------------------</span></div>
|
||||
<div class="line"><span class="comment"> SysTick_Handler (RAM)</span></div>
|
||||
<div class="line"><span class="comment"> *----------------------------------------------------------------------------*/</span></div>
|
||||
<div class="line"><span class="keyword">volatile</span> uint32_t msTicks_RAM = 0; <span class="comment">/* counts 1ms timeTicks */</span></div>
|
||||
<div class="line"><span class="keywordtype">void</span> SysTick_Handler_RAM(<span class="keywordtype">void</span>) {</div>
|
||||
<div class="line"> msTicks_RAM++; <span class="comment">/* increment counter */</span></div>
|
||||
<div class="line">}</div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"><span class="comment">/*----------------------------------------------------------------------------</span></div>
|
||||
<div class="line"><span class="comment"> MAIN function</span></div>
|
||||
<div class="line"><span class="comment"> *----------------------------------------------------------------------------*/</span></div>
|
||||
<div class="line"><span class="keywordtype">int</span> main (<span class="keywordtype">void</span>) {</div>
|
||||
<div class="line"> uint32_t i;</div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"> <span class="keywordflow">for</span> (i = 0; i < VECTORTABLE_SIZE; i++) {</div>
|
||||
<div class="line"> vectorTable_RAM[i] = __Vectors[i]; <span class="comment">/* copy vector table to RAM */</span></div>
|
||||
<div class="line"> }</div>
|
||||
<div class="line"> <span class="comment">/* replace SysTick Handler */</span></div>
|
||||
<div class="line"> vectorTable_RAM[<a class="code" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7" title="Exception 15: System Tick Interrupt.">SysTick_IRQn</a> + 16] = (uint32_t)SysTick_Handler_RAM;</div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"> <span class="comment">/* relocate vector table */</span> </div>
|
||||
<div class="line"> <a class="code" href="group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013" title="Globally disables interrupts and configurable fault handlers.">__disable_irq</a>();</div>
|
||||
<div class="line"> SCB->VTOR = (uint32_t)&vectorTable_RAM;</div>
|
||||
<div class="line"> <a class="code" href="group__intrinsic___c_p_u__gr.html#gacb2a8ca6eae1ba4b31161578b720c199" title="Data Synchronization Barrier.">__DSB</a>();</div>
|
||||
<div class="line"> <a class="code" href="group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27" title="Globally enables interrupts and configurable fault handlers.">__enable_irq</a>();</div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"> <a class="code" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f" title="Function to update the variable SystemCoreClock.">SystemCoreClockUpdate</a>(); <span class="comment">/* Get Core Clock Frequency */</span></div>
|
||||
<div class="line"> <a class="code" href="group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427" title="System Tick Timer Configuration.">SysTick_Config</a>(<a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6" title="Variable to hold the system core clock value.">SystemCoreClock</a> / 1000ul); <span class="comment">/* Setup SysTick Timer for 1 msec */</span></div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"> <span class="keywordflow">while</span>(1);</div>
|
||||
<div class="line">}</div>
|
||||
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||||
<div class="textblock"><p>To use the CMSIS-CORE the following files are added to the embedded application:</p>
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
<dl class="section note"><dt>Note</dt><dd>The files <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a> and <a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a> may require application specific adaptations and therefore should be copied into the application project folder prior configuration. The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is included in all source files that need device access and can be stored on a central include folder that is generic for all projects.</dd></dl>
|
||||
<p>The <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a> is executed after reset and calls <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a>. After the system initialization control is transferred to the C/C++ run-time library which performs initialization and calls the <b>main</b> function in the user code. In addition the <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a> contains all exception and interrupt vectors and implements a default function for every interrupt. It may also contain stack and heap configurations for the user application.</p>
|
||||
<p>The <a class="el" href="system_c_pg.html">System Configuration Files system_<device>.c and system_<device>.h</a> performs the setup for the processor clock. The variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> indicates the CPU clock speed. <a class="el" href="group__system__init__gr.html">System and Clock Configuration</a> describes the minimum feature set. In addition the file may contain functions for the memory BUS setup and clock re-configuration.</p>
|
||||
<p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> is the central include file that the application programmer is using in the C source code. It provides the following features:</p>
|
||||
<ul>
|
||||
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|
||||
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|
||||
<li><a class="el" href="group__intrinsic___c_p_u__gr.html">Intrinsic Functions for CPU Instructions</a> allow to access special instructions, for example for activating sleep mode or the NOP instruction.</li>
|
||||
<li><a class="el" href="group__intrinsic___s_i_m_d__gr.html">Intrinsic Functions for SIMD Instructions [only Cortex-M4 and Cortex-M7]</a> provide access to the DSP-oriented instructions.</li>
|
||||
<li><a class="el" href="group___sys_tick__gr.html">Systick Timer (SYSTICK)</a> function to configure and start a periodic timer interrupt.</li>
|
||||
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|
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|
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|
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|
||||
CMSIS-CORE User Files</div></div>
|
||||
<p> The CMSIS-CORE are device specific. In addition, the <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a> is also compiler vendor specific. The various compiler vendor tool chains may provide folders that contain the CMSIS files for each supported device.</p>
|
||||
<p>For example, the following files are provided in MDK-ARM to support the STM32F10x Connectivity Line device variants:</p>
|
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|
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|
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|
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|
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|
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|
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|
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<p>Thereafter, the functions described under <a href="Modules.html"><b>Reference</b> </a> can be used in the application.</p>
|
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|
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|
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<li><a class="el" href="_using__v_t_o_r_pg.html">Using Interrupt Vector Remap</a> shows how to remap the interrupt vector table.</li>
|
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<li><a class="el" href="_using__a_r_m_pg.html">Using CMSIS with generic ARM Processors</a> explains how to use CMSIS-CORE for ARM processors. </li>
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<div class="title">Data Structures</div> </div>
|
||||
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|
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<div class="contents">
|
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<div class="textblock">Here are the data structures with brief descriptions:</div><div class="directory">
|
||||
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|
||||
<tr id="row_0_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="union_a_p_s_r___type.html" target="_self">APSR_Type</a></td><td class="desc">Union type to access the Application Program Status Register (APSR)</td></tr>
|
||||
<tr id="row_1_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="union_c_o_n_t_r_o_l___type.html" target="_self">CONTROL_Type</a></td><td class="desc">Union type to access the Control Registers (CONTROL)</td></tr>
|
||||
<tr id="row_2_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_core_debug___type.html" target="_self">CoreDebug_Type</a></td><td class="desc">Structure type to access the Core Debug Register (CoreDebug)</td></tr>
|
||||
<tr id="row_3_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_d_w_t___type.html" target="_self">DWT_Type</a></td><td class="desc">Structure type to access the Data Watchpoint and Trace Register (DWT)</td></tr>
|
||||
<tr id="row_4_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_f_p_u___type.html" target="_self">FPU_Type</a></td><td class="desc">Structure type to access the Floating Point Unit (FPU)</td></tr>
|
||||
<tr id="row_5_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="union_i_p_s_r___type.html" target="_self">IPSR_Type</a></td><td class="desc">Union type to access the Interrupt Program Status Register (IPSR)</td></tr>
|
||||
<tr id="row_6_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_i_t_m___type.html" target="_self">ITM_Type</a></td><td class="desc">Structure type to access the Instrumentation Trace Macrocell Register (ITM)</td></tr>
|
||||
<tr id="row_7_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_m_p_u___type.html" target="_self">MPU_Type</a></td><td class="desc">Structure type to access the Memory Protection Unit (MPU)</td></tr>
|
||||
<tr id="row_8_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_n_v_i_c___type.html" target="_self">NVIC_Type</a></td><td class="desc">Structure type to access the Nested Vectored Interrupt Controller (NVIC)</td></tr>
|
||||
<tr id="row_9_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_s_c_b___type.html" target="_self">SCB_Type</a></td><td class="desc">Structure type to access the System Control Block (SCB)</td></tr>
|
||||
<tr id="row_10_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_s_cn_s_c_b___type.html" target="_self">SCnSCB_Type</a></td><td class="desc">Structure type to access the System Control and ID Register not in the SCB</td></tr>
|
||||
<tr id="row_11_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_sys_tick___type.html" target="_self">SysTick_Type</a></td><td class="desc">Structure type to access the System Timer (SysTick)</td></tr>
|
||||
<tr id="row_12_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_t_p_i___type.html" target="_self">TPI_Type</a></td><td class="desc">Structure type to access the Trace Port Interface Register (TPI)</td></tr>
|
||||
<tr id="row_13_"><td class="entry"><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="unionx_p_s_r___type.html" target="_self">xPSR_Type</a></td><td class="desc">Union type to access the Special-Purpose Program Status Registers (xPSR)</td></tr>
|
||||
</table>
|
||||
</div><!-- directory -->
|
||||
</div><!-- contents -->
|
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</div><!-- doc-content -->
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<!-- start footer part -->
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 <span id="projectnumber">Version 4.30</span>
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<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
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<div class="qindex"><a class="qindex" href="#letter_A">A</a> | <a class="qindex" href="#letter_C">C</a> | <a class="qindex" href="#letter_D">D</a> | <a class="qindex" href="#letter_F">F</a> | <a class="qindex" href="#letter_I">I</a> | <a class="qindex" href="#letter_M">M</a> | <a class="qindex" href="#letter_N">N</a> | <a class="qindex" href="#letter_S">S</a> | <a class="qindex" href="#letter_T">T</a> | <a class="qindex" href="#letter_X">X</a></div>
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</td><td valign="top"><a class="el" href="struct_i_t_m___type.html">ITM_Type</a>   </td><td rowspan="2" valign="bottom"><a name="letter_S"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">  S  </div></td></tr></table>
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<tr><td valign="top"><a class="el" href="union_a_p_s_r___type.html">APSR_Type</a>   </td><td valign="top"><a class="el" href="struct_d_w_t___type.html">DWT_Type</a>   </td><td valign="top"><a class="el" href="struct_s_c_b___type.html">SCB_Type</a>   </td><td valign="top"><a class="el" href="unionx_p_s_r___type.html">xPSR_Type</a>   </td></tr>
|
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|
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</td><td rowspan="2" valign="bottom"><a name="letter_F"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">  F  </div></td></tr></table>
|
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</td><td valign="top"><a class="el" href="struct_m_p_u___type.html">MPU_Type</a>   </td><td valign="top"><a class="el" href="struct_s_cn_s_c_b___type.html">SCnSCB_Type</a>   </td><td></td></tr>
|
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<tr><td rowspan="2" valign="bottom"><a name="letter_N"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">  N  </div></td></tr></table>
|
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</td><td valign="top"><a class="el" href="struct_sys_tick___type.html">SysTick_Type</a>   </td><td></td></tr>
|
||||
<tr><td valign="top"><a class="el" href="union_c_o_n_t_r_o_l___type.html">CONTROL_Type</a>   </td><td valign="top"><a class="el" href="struct_f_p_u___type.html">FPU_Type</a>   </td><td rowspan="2" valign="bottom"><a name="letter_T"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">  T  </div></td></tr></table>
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<tr><td valign="top"><a class="el" href="struct_core_debug___type.html">CoreDebug_Type</a>   </td><td rowspan="2" valign="bottom"><a name="letter_I"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">  I  </div></td></tr></table>
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</td><td valign="top"><a class="el" href="struct_n_v_i_c___type.html">NVIC_Type</a>   </td><td></td></tr>
|
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|
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<div id="projectname">CMSIS-CORE
|
||||
 <span id="projectnumber">Version 4.30</span>
|
||||
</div>
|
||||
<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
|
||||
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<div class="title">Revision History of CMSIS-CORE </div> </div>
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||||
</div><!--header-->
|
||||
<div class="contents">
|
||||
<div class="textblock"><table class="cmtable" summary="Core Exception Name">
|
||||
<tr>
|
||||
<th>Version </th><th>Description </th></tr>
|
||||
<tr>
|
||||
<td>V4.30 </td><td>Corrected: DoxyGen function parameter comments.<br/>
|
||||
Corrected: IAR toolchain: removed for <a class="el" href="group___n_v_i_c__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46">NVIC_SystemReset</a> the attribute(noreturn).<br/>
|
||||
Corrected: GCC toolchain: supressed irrelevant compiler warnings.<br/>
|
||||
Added: Support files for ARM Compiler v6 (cmsis_armcc_v6.h). </td></tr>
|
||||
<tr>
|
||||
<td>V4.20 </td><td>Corrected: MISRA-C:2004 violations. <br/>
|
||||
Corrected: predefined macro for TI CCS Compiler. <br/>
|
||||
Corrected: function <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga15d8899a173effb8ad8c7268da32b60e">__SHADD16</a> in arm_math.h. <br/>
|
||||
Updated: cache functions for Cortex-M7. <br/>
|
||||
Added: macros <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>, <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a> to core_*.h. <br/>
|
||||
Updated: functions <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga87618799672e1511e33964bc71467eb3">__QASX</a>, <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab41eb2b17512ab01d476fc9d5bd19520">__QSAX</a>, <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae0a649035f67627464fd80e7218c89d5">__SHASX</a>, <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafadbd89c36b5addcf1ca10dd392db3e9">__SHSAX</a>. <br/>
|
||||
Corrected: potential bug in function <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga15d8899a173effb8ad8c7268da32b60e">__SHADD16</a>. </td></tr>
|
||||
<tr>
|
||||
<td>V4.10 </td><td>Corrected: MISRA-C:2004 violations. <br/>
|
||||
Corrected: intrinsic functions <a class="el" href="group__intrinsic___c_p_u__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">__DSB</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">__DMB</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga93c09b4709394d81977300d5f84950e5">__ISB</a>. <br/>
|
||||
Corrected: register definitions for ITCMCR register. <br/>
|
||||
Corrected: register definitions for <a class="el" href="union_c_o_n_t_r_o_l___type.html">CONTROL_Type</a> register. <br/>
|
||||
Added: functions <a class="el" href="group__fpu__functions__m7.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a>, <a class="el" href="group___dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09">SCB_InvalidateDCache_by_Addr</a> to core_cm7.h. <br/>
|
||||
Added: register definitions for <a class="el" href="union_a_p_s_r___type.html">APSR_Type</a>, <a class="el" href="union_i_p_s_r___type.html">IPSR_Type</a>, <a class="el" href="unionx_p_s_r___type.html">xPSR_Type</a> register. <br/>
|
||||
Added: <a class="el" href="group___core___register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9">__set_BASEPRI_MAX</a> function to core_cmFunc.h. <br/>
|
||||
Added: intrinsic functions <a class="el" href="group__intrinsic___c_p_u__gr.html#gad6f9f297f6b91a995ee199fbc796b863">__RBIT</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga90884c591ac5d73d6069334eba9d6c02">__CLZ</a> for Cortex-M0/CortexM0+. <br/>
|
||||
</td></tr>
|
||||
<tr>
|
||||
<td>V4.00 </td><td>Added: Cortex-M7 support.<br/>
|
||||
Added: intrinsic functions for <a class="el" href="group__intrinsic___c_p_u__gr.html#gac09134f1bf9c49db07282001afcc9380">__RRX</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9464d75db32846aa8295c3c3adfacb41">__LDRBT</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gaa762b8bc5634ce38cb14d62a6b2aee32">__LDRHT</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga616504f5da979ba8a073d428d6e8d5c7">__LDRT</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gad41aa59c92c0a165b7f98428d3320cd5">__STRBT</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga2b5d93b8e461755b1072a03df3f1722e">__STRHT</a>, and <a class="el" href="group__intrinsic___c_p_u__gr.html#ga625bc4ac0b1d50de9bcd13d9f050030e">__STRT</a> <br/>
|
||||
</td></tr>
|
||||
<tr>
|
||||
<td>V3.40 </td><td>Corrected: C++ include guard settings.<br/>
|
||||
</td></tr>
|
||||
<tr>
|
||||
<td>V3.30 </td><td>Added: COSMIC tool chain support.<br/>
|
||||
Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.<br/>
|
||||
Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.<br/>
|
||||
Corrected: GCC/CLang warnings.<br/>
|
||||
</td></tr>
|
||||
<tr>
|
||||
<td>V3.20 </td><td>Added: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga92f5621626711931da71eaa8bf301af7">__BKPT</a> instruction intrinsic.<br/>
|
||||
Added: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaea60757232f740ec6b09980eebb614ff">__SMMLA</a> instruction intrinsic for Cortex-M4.<br/>
|
||||
Corrected: <a class="el" href="group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a>.<br/>
|
||||
Corrected: <a class="el" href="group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">__enable_irq</a>, <a class="el" href="group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">__disable_irq</a> and inline assembly for GCC Compiler.<br/>
|
||||
Corrected: <a class="el" href="group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">NVIC_GetPriority</a> and VTOR_TBLOFF for Cortex-M0/M0+, SC000. Corrected: rework of in-line assembly functions to remove potential compiler warnings.<br/>
|
||||
</td></tr>
|
||||
<tr>
|
||||
<td>V3.01 </td><td>Added support for Cortex-M0+ processor. <br/>
|
||||
</td></tr>
|
||||
<tr>
|
||||
<td>V3.00 </td><td>Added support for GNU GCC ARM Embedded Compiler. <br/>
|
||||
Added function <a class="el" href="group__intrinsic___c_p_u__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">__ROR</a>.<br/>
|
||||
Added <a class="el" href="_reg_map_pg.html">Register Mapping</a> for TPIU, DWT. <br/>
|
||||
Added support for <a class="el" href="device_h_pg.html#core_config_sect">SC000 and SC300 processors</a>.<br/>
|
||||
Corrected <a class="el" href="group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a> function. <br/>
|
||||
Corrected the functions <a class="el" href="group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a> for the GNU GCC compiler section. <br/>
|
||||
Documentation restructured. </td></tr>
|
||||
<tr>
|
||||
<td>V2.10 </td><td>Updated documentation.<br/>
|
||||
Updated CMSIS core include files.<br/>
|
||||
Changed CMSIS/Device folder structure.<br/>
|
||||
Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.<br/>
|
||||
Reworked CMSIS DSP library examples. </td></tr>
|
||||
<tr>
|
||||
<td>V2.00 </td><td>Added support for Cortex-M4 processor. </td></tr>
|
||||
<tr>
|
||||
<td>V1.30 </td><td>Reworked Startup Concept.<br/>
|
||||
Added additional Debug Functionality.<br/>
|
||||
Changed folder structure.<br/>
|
||||
Added doxygen comments.<br/>
|
||||
Added definitions for bit. </td></tr>
|
||||
<tr>
|
||||
<td>V1.01 </td><td>Added support for Cortex-M0 processor. </td></tr>
|
||||
<tr>
|
||||
<td>V1.01 </td><td>Added intrinsic functions for <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">__LDREXB</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">__LDREXH</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">__LDREXW</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">__STREXB</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">__STREXH</a>, <a class="el" href="group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">__STREXW</a>, and <a class="el" href="group__intrinsic___c_p_u__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">__CLREX</a> </td></tr>
|
||||
<tr>
|
||||
<td>V1.00 </td><td>Initial Release for Cortex-M3 processor. </td></tr>
|
||||
</table>
|
||||
</div></div><!-- contents -->
|
||||
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<!-- start footer part -->
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<li class="footer">Generated on Tue Oct 27 2015 14:35:21 for CMSIS-CORE by ARM Ltd. All rights reserved.
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<div id="projectname">CMSIS-CORE
|
||||
 <span id="projectnumber">Version 4.30</span>
|
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<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
|
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<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div>
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<div class="title">Device Header File <device.h> </div> </div>
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</div><!--header-->
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<div class="contents">
|
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<div class="textblock"><p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains the following sections that are device specific:</p>
|
||||
<ul>
|
||||
<li><a class="el" href="device_h_pg.html#interrupt_number_sec">Interrupt Number Definition</a> provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.</li>
|
||||
<li><a class="el" href="device_h_pg.html#core_config_sect">Configuration of the Processor and Core Peripherals</a> reflect the features of the device.</li>
|
||||
<li><a class="el" href="device_h_pg.html#device_access">Device Peripheral Access Layer</a> provides definitions for the <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.</li>
|
||||
<li><b>Access Functions for Peripherals (optional)</b> provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.</li>
|
||||
</ul>
|
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<p><a href="Modules.html"><b>Reference</b> </a> describes the standard features and functions of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</p>
|
||||
<h1><a class="anchor" id="interrupt_number_sec"></a>
|
||||
Interrupt Number Definition</h1>
|
||||
<p><a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains the enumeration <a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> that defines all exceptions and interrupts of the device.</p>
|
||||
<ul>
|
||||
<li>Negative IRQn values represent processor core exceptions (internal interrupts).</li>
|
||||
<li>Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the <a class="el" href="startup_s_pg.html">Startup File startup_<device>.s</a>.</li>
|
||||
</ul>
|
||||
<p><b>Example:</b> </p>
|
||||
<p>The following example shows the extension of the interrupt vector table for the LPC1100 device family.</p>
|
||||
<div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">enum</span> IRQn</div>
|
||||
<div class="line">{</div>
|
||||
<div class="line"><span class="comment">/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/</span></div>
|
||||
<div class="line"> <a class="code" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30" title="Exception 2: Non Maskable Interrupt.">NonMaskableInt_IRQn</a> = -14, </div>
|
||||
<div class="line"> <a class="code" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85" title="Exception 3: Hard Fault Interrupt.">HardFault_IRQn</a> = -13, </div>
|
||||
<div class="line"> <a class="code" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237" title="Exception 11: SV Call Interrupt.">SVCall_IRQn</a> = -5, </div>
|
||||
<div class="line"> <a class="code" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2" title="Exception 14: Pend SV Interrupt [not on Cortex-M0 variants].">PendSV_IRQn</a> = -2, </div>
|
||||
<div class="line"> <a class="code" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7" title="Exception 15: System Tick Interrupt.">SysTick_IRQn</a> = -1, </div>
|
||||
<div class="line"><span class="comment">/****** LPC11xx/LPC11Cxx Specific Interrupt Numbers **********************************************/</span></div>
|
||||
<div class="line"> WAKEUP0_IRQn = 0, </div>
|
||||
<div class="line"> WAKEUP1_IRQn = 1, </div>
|
||||
<div class="line"> WAKEUP2_IRQn = 2,</div>
|
||||
<div class="line"> : :</div>
|
||||
<div class="line"> : :</div>
|
||||
<div class="line"> EINT1_IRQn = 30, </div>
|
||||
<div class="line"> EINT0_IRQn = 31, </div>
|
||||
<div class="line">} <a class="code" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8" title="Definition of IRQn numbers.">IRQn_Type</a>;</div>
|
||||
</div><!-- fragment --><h1><a class="anchor" id="core_config_sect"></a>
|
||||
Configuration of the Processor and Core Peripherals</h1>
|
||||
<p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> configures the Cortex-M or SecurCore processor and the core peripherals with <em>#defines</em> that are set prior to including the file <b>core_<cpu>.h</b>.</p>
|
||||
<p>The following tables list the <em>#defines</em> along with the possible values for each processor core. If these <em>#defines</em> are missing default values are used.</p>
|
||||
<p><b>core_cm0.h</b> </p>
|
||||
<table class="cmtable">
|
||||
<tr>
|
||||
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
|
||||
<tr>
|
||||
<td>__CM0_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
|
||||
<tr>
|
||||
<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
|
||||
<tr>
|
||||
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
|
||||
</table>
|
||||
<p><b>core_cm0plus.h</b> </p>
|
||||
<table class="cmtable">
|
||||
<tr>
|
||||
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
|
||||
<tr>
|
||||
<td>__CM0PLUS_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
|
||||
<tr>
|
||||
<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
|
||||
<tr>
|
||||
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
|
||||
</table>
|
||||
<p><b>core_cm3.h</b> </p>
|
||||
<table class="cmtable">
|
||||
<tr>
|
||||
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
|
||||
<tr>
|
||||
<td>__CM3_REV </td><td>0x0101 | 0x0200 </td><td>0x0200 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
|
||||
<tr>
|
||||
<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
|
||||
<tr>
|
||||
<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr>
|
||||
<tr>
|
||||
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
|
||||
</table>
|
||||
<p><b>core_cm4.h</b> </p>
|
||||
<table class="cmtable">
|
||||
<tr>
|
||||
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
|
||||
<tr>
|
||||
<td>__CM4_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
|
||||
<tr>
|
||||
<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
|
||||
<tr>
|
||||
<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr>
|
||||
<tr>
|
||||
<td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not </td></tr>
|
||||
<tr>
|
||||
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
|
||||
</table>
|
||||
<p><b>core_cm7.h</b> </p>
|
||||
<table class="cmtable">
|
||||
<tr>
|
||||
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
|
||||
<tr>
|
||||
<td>__CM7_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
|
||||
<tr>
|
||||
<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr>
|
||||
<tr>
|
||||
<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
|
||||
<tr>
|
||||
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
|
||||
<tr>
|
||||
<td>__FPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a FPU is present or not. See <b>__FPU_DP</b> description below. </td></tr>
|
||||
<tr>
|
||||
<td>__FPU_DP </td><td>0 .. 1 </td><td>0 </td><td>The combination of the defines <b>__FPU_PRESENT</b> and <b>__FPU_DP</b> determine the whether the FPU is with single or double precision as shown in the table below. <br/>
|
||||
<br/>
|
||||
<table class="cmtable">
|
||||
<tr bgcolor="cyan">
|
||||
<td><b>__FPU_PRESENT</b> </td><td><b>__FPU_DP</b> </td><td><b>Description</b> </td></tr>
|
||||
<tr>
|
||||
<td align="center">0 </td><td align="center"><em>ignored</em> </td><td>Processor has no FPU. The value set for <b>__FPU_DP</b> has no influence. </td></tr>
|
||||
<tr>
|
||||
<td align="center">1 </td><td align="center">0 </td><td>Processor with FPU with single precision. The file <b>ARMCM7_SP.h</b> has preconfigured settings for this combination. </td></tr>
|
||||
<tr>
|
||||
<td align="center">1 </td><td align="center">1 </td><td>Processor with FPU with double precision. The file <b>ARMCM7_DP.h</b> has preconfigured settings for this combination. </td></tr>
|
||||
</table>
|
||||
</td></tr>
|
||||
<tr>
|
||||
<td>__ICACHE_PRESENT </td><td>0 .. 1 </td><td>1 </td><td>Instruction Chache present or not </td></tr>
|
||||
<tr>
|
||||
<td>__DCACHE_PRESENT </td><td>0 .. 1 </td><td>1 </td><td>Data Chache present or not </td></tr>
|
||||
<tr>
|
||||
<td>__DTCM_PRESENT </td><td>0 .. 1 </td><td>1 </td><td><p class="starttd">Data Tightly Coupled Memory is present or not </p>
|
||||
<p class="endtd"></p>
|
||||
</td></tr>
|
||||
</table>
|
||||
<p><b>core_sc000.h</b> </p>
|
||||
<table class="cmtable">
|
||||
<tr>
|
||||
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
|
||||
<tr>
|
||||
<td>__SC000_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
|
||||
<tr>
|
||||
<td>__NVIC_PRIO_BITS </td><td>2 </td><td>2 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
|
||||
<tr>
|
||||
<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr>
|
||||
<tr>
|
||||
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
|
||||
</table>
|
||||
<p><b>core_sc300.h</b> </p>
|
||||
<table class="cmtable">
|
||||
<tr>
|
||||
<th>#define </th><th>Value Range </th><th>Default </th><th>Description </th></tr>
|
||||
<tr>
|
||||
<td>__SC300_REV </td><td>0x0000 </td><td>0x0000 </td><td>Core revision number ([15:8] revision number, [7:0] patch number) </td></tr>
|
||||
<tr>
|
||||
<td>__NVIC_PRIO_BITS </td><td>2 .. 8 </td><td>4 </td><td>Number of priority bits implemented in the NVIC (device specific) </td></tr>
|
||||
<tr>
|
||||
<td>__MPU_PRESENT </td><td>0 .. 1 </td><td>0 </td><td>Defines if a MPU is present or not </td></tr>
|
||||
<tr>
|
||||
<td>__Vendor_SysTickConfig </td><td>0 .. 1 </td><td>0 </td><td>If this define is set to 1, then the default <b>SysTick_Config</b> function is excluded. In this case, the file <em><b>device.h</b></em> must contain a vendor specific implementation of this function. </td></tr>
|
||||
</table>
|
||||
<p><b>Example</b> </p>
|
||||
<p>The following code exemplifies the configuration of the Cortex-M4 Processor and Core Peripherals.</p>
|
||||
<div class="fragment"><div class="line"><span class="preprocessor">#define __CM4_REV 0x0001 </span><span class="comment">/* Core revision r0p1 */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __MPU_PRESENT 1 </span><span class="comment">/* MPU present or not */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __NVIC_PRIO_BITS 3 </span><span class="comment">/* Number of Bits used for Priority Levels */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __Vendor_SysTickConfig 0 </span><span class="comment">/* Set to 1 if different SysTick Config is used */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __FPU_PRESENT 1 </span><span class="comment">/* FPU present or not */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span>.</div>
|
||||
<div class="line">.</div>
|
||||
<div class="line"><span class="preprocessor">#include <core_cm4.h></span> <span class="comment">/* Cortex-M4 processor and core peripherals */</span></div>
|
||||
</div><!-- fragment --><h1><a class="anchor" id="core_version_sect"></a>
|
||||
CMSIS Version and Processor Information</h1>
|
||||
<p>Defines in the core_<em>cpu</em>.h file identify the version of the CMSIS-CORE and the processor used. The following shows the defines in the various core_<em>cpu</em>.h files that may be used in the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> to verify a minimum version or ensure that the right processor core is used.</p>
|
||||
<p><b>core_cm0.h</b> </p>
|
||||
<div class="fragment"><div class="line"><span class="preprocessor">#define __CM0_CMSIS_VERSION_MAIN (0x03) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0_CMSIS_VERSION_SUB (0x00) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \</span></div>
|
||||
<div class="line"><span class="preprocessor"> __CM0_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span>... </div>
|
||||
<div class="line"><span class="preprocessor">#define __CORTEX_M (0x00) </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
|
||||
</div><!-- fragment --><p><b>core_cm0plus.h</b> </p>
|
||||
<div class="fragment"><div class="line"><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION_SUB (0x00) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM0PLUS_CMSIS_VERSION ((__CM0P_CMSIS_VERSION_MAIN << 16) | \</span></div>
|
||||
<div class="line"><span class="preprocessor"> __CM0P_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span>... </div>
|
||||
<div class="line"><span class="preprocessor">#define __CORTEX_M (0x00) </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
|
||||
</div><!-- fragment --><p><b>core_cm3.h</b> </p>
|
||||
<div class="fragment"><div class="line"><span class="preprocessor">#define __CM3_CMSIS_VERSION_MAIN (0x03) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM3_CMSIS_VERSION_SUB (0x00) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \</span></div>
|
||||
<div class="line"><span class="preprocessor"> __CM3_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span>... </div>
|
||||
<div class="line"><span class="preprocessor">#define __CORTEX_M (0x03) </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
|
||||
</div><!-- fragment --><p><b>core_cm4.h</b> </p>
|
||||
<div class="fragment"><div class="line"><span class="preprocessor">#define __CM4_CMSIS_VERSION_MAIN (0x04) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM4_CMSIS_VERSION_SUB (0x00) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \</span></div>
|
||||
<div class="line"><span class="preprocessor"> __CM4_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span>... </div>
|
||||
<div class="line"><span class="preprocessor">#define __CORTEX_M (0x04) </span><span class="comment">/* Cortex-M Core */</span><span class="preprocessor"></span></div>
|
||||
</div><!-- fragment --><p><b>core_cm7.h</b> </p>
|
||||
<div class="fragment"><div class="line"><span class="preprocessor">#define __CM7_CMSIS_VERSION_MAIN (0x04) </span></div>
|
||||
<div class="line"><span class="preprocessor">#define __CM7_CMSIS_VERSION_SUB (0x00) </span></div>
|
||||
<div class="line"><span class="preprocessor">#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \</span></div>
|
||||
<div class="line"><span class="preprocessor"> __CM7_CMSIS_VERSION_SUB ) </span></div>
|
||||
<div class="line"><span class="preprocessor">#define __CORTEX_M (0x07) </span></div>
|
||||
</div><!-- fragment --><p><b>core_sc000.h</b> </p>
|
||||
<div class="fragment"><div class="line"><span class="preprocessor">#define __SC000_CMSIS_VERSION_MAIN (0x04) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC000_CMSIS_VERSION_SUB (0x00) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \</span></div>
|
||||
<div class="line"><span class="preprocessor"> __SC000_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span>... </div>
|
||||
<div class="line"><span class="preprocessor">#define __CORTEX_SC (000) </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div>
|
||||
</div><!-- fragment --><p><b>core_sc300.h</b> </p>
|
||||
<div class="fragment"><div class="line"><span class="preprocessor">#define __SC300_CMSIS_VERSION_MAIN (0x04) </span><span class="comment">/* [31:16] CMSIS HAL main version */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC300_CMSIS_VERSION_SUB (0x00) </span><span class="comment">/* [15:0] CMSIS HAL sub version */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span><span class="preprocessor">#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \</span></div>
|
||||
<div class="line"><span class="preprocessor"> __SC300_CMSIS_VERSION_SUB ) </span><span class="comment">/* CMSIS HAL version number */</span><span class="preprocessor"></span></div>
|
||||
<div class="line"><span class="preprocessor"></span>... </div>
|
||||
<div class="line"><span class="preprocessor">#define __CORTEX_SC (300) </span><span class="comment">/* Cortex secure core */</span><span class="preprocessor"></span></div>
|
||||
</div><!-- fragment --><h1><a class="anchor" id="device_access"></a>
|
||||
Device Peripheral Access Layer</h1>
|
||||
<p>The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains for each peripheral:</p>
|
||||
<ul>
|
||||
<li>Register Layout Typedef</li>
|
||||
<li>Base Address</li>
|
||||
<li>Access Definitions</li>
|
||||
</ul>
|
||||
<p>The section <a class="el" href="group__peripheral__gr.html">Peripheral Access</a> shows examples for peripheral definitions.</p>
|
||||
<h1><a class="anchor" id="device_h_sec"></a>
|
||||
Device.h Template File</h1>
|
||||
<p>The silicon vendor needs to extend the Device.h template file with the CMSIS features described above. In addition the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> may contain functions to access device-specific peripherals. The <a class="el" href="system_c_pg.html#system_Device_h_sec">system_Device.h Template File</a> which is provided as part of the CMSIS specification is shown below.</p>
|
||||
<pre class="fragment">/**************************************************************************//**
|
||||
* @file <Device>.h
|
||||
* @brief CMSIS Cortex-M# Core Peripheral Access Layer Header File for
|
||||
* Device <Device>
|
||||
* @version V3.10
|
||||
* @date 23. November 2012
|
||||
*
|
||||
* @note
|
||||
*
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef <Device>_H /* ToDo: replace '<Device>' with your device name */
|
||||
#define <Device>_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* ToDo: replace '<Device>' with your device name; add your doxyGen comment */
|
||||
/** @addtogroup <Device>_Definitions <Device> Definitions
|
||||
This file defines all structures and symbols for <Device>:
|
||||
- registers and bitfields
|
||||
- peripheral base address
|
||||
- peripheral ID
|
||||
- Peripheral definitions
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Processor and Core Peripherals */
|
||||
/******************************************************************************/
|
||||
/** @addtogroup <Device>_CMSIS Device CMSIS Definitions
|
||||
Configuration of the Cortex-M# Processor and Core Peripherals
|
||||
@{
|
||||
*/
|
||||
|
||||
/*
|
||||
* ==========================================================================
|
||||
* ---------- Interrupt Number Definition -----------------------------------
|
||||
* ==========================================================================
|
||||
*/
|
||||
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M# Processor Exceptions Numbers ***************************************************/
|
||||
|
||||
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M0 device */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 Hard Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
|
||||
|
||||
/* ToDo: use this Cortex interrupt numbers if your device is a CORTEX-M3 / Cortex-M4 device */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
|
||||
|
||||
/****** Device Specific Interrupt Numbers ********************************************************/
|
||||
/* ToDo: add here your device specific external interrupt numbers
|
||||
according the interrupt handlers defined in startup_Device.s
|
||||
eg.: Interrupt for Timer#1 TIM1_IRQHandler -> TIM1_IRQn */
|
||||
<DeviceInterrupt>_IRQn = 0, /*!< Device Interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
|
||||
/*
|
||||
* ==========================================================================
|
||||
* ----------- Processor and Core Peripheral Section ------------------------
|
||||
* ==========================================================================
|
||||
*/
|
||||
|
||||
/* Configuration of the Cortex-M# Processor and Core Peripherals */
|
||||
/* ToDo: set the defines according your Device */
|
||||
/* ToDo: define the correct core revision
|
||||
__CM0_REV if your device is a CORTEX-M0 device
|
||||
__CM3_REV if your device is a CORTEX-M3 device
|
||||
__CM4_REV if your device is a CORTEX-M4 device */
|
||||
#define __CM#_REV 0x0201 /*!< Core Revision r2p1 */
|
||||
#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
|
||||
#define __MPU_PRESENT 0 /*!< MPU present or not */
|
||||
/* ToDo: define __FPU_PRESENT if your devise is a CORTEX-M4 */
|
||||
#define __FPU_PRESENT 0 /*!< FPU present or not */
|
||||
|
||||
/*@}*/ /* end of group <Device>_CMSIS */
|
||||
|
||||
|
||||
/* ToDo: include the correct core_cm#.h file
|
||||
core_cm0.h if your device is a CORTEX-M0 device
|
||||
core_cm3.h if your device is a CORTEX-M3 device
|
||||
core_cm4.h if your device is a CORTEX-M4 device */
|
||||
#include <core_cm#.h> /* Cortex-M# processor and core peripherals */
|
||||
/* ToDo: include your system_<Device>.h file
|
||||
replace '<Device>' with your device name */
|
||||
#include "system_<Device>.h" /* <Device> System include file */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Device Specific Peripheral registers structures */
|
||||
/******************************************************************************/
|
||||
/** @addtogroup <Device>_Peripherals <Device> Peripherals
|
||||
<Device> Device Specific Peripheral registers structures
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/* ToDo: add here your device specific peripheral access structure typedefs
|
||||
following is an example for a timer */
|
||||
|
||||
/*------------- 16-bit Timer/Event Counter (TMR) -----------------------------*/
|
||||
/** @addtogroup <Device>_TMR <Device> 16-bit Timer/Event Counter (TMR)
|
||||
@{
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t EN; /*!< Offset: 0x0000 Timer Enable Register */
|
||||
__IO uint32_t RUN; /*!< Offset: 0x0004 Timer RUN Register */
|
||||
__IO uint32_t CR; /*!< Offset: 0x0008 Timer Control Register */
|
||||
__IO uint32_t MOD; /*!< Offset: 0x000C Timer Mode Register */
|
||||
uint32_t RESERVED0[1];
|
||||
__IO uint32_t ST; /*!< Offset: 0x0014 Timer Status Register */
|
||||
__IO uint32_t IM; /*!< Offset: 0x0018 Interrupt Mask Register */
|
||||
__IO uint32_t UC; /*!< Offset: 0x001C Timer Up Counter Register */
|
||||
__IO uint32_t RG0 /*!< Offset: 0x0020 Timer Register */
|
||||
uint32_t RESERVED1[2];
|
||||
__IO uint32_t CP; /*!< Offset: 0x002C Capture register */
|
||||
} <DeviceAbbreviation>_TMR_TypeDef;
|
||||
/*@}*/ /* end of group <Device>_TMR */
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#pragma no_anon_unions
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group <Device>_Peripherals */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral memory map */
|
||||
/******************************************************************************/
|
||||
/* ToDo: add here your device peripherals base addresses
|
||||
following is an example for timer */
|
||||
/** @addtogroup <Device>_MemoryMap <Device> Memory Mapping
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Peripheral and SRAM base address */
|
||||
#define <DeviceAbbreviation>_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
|
||||
#define <DeviceAbbreviation>_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
|
||||
#define <DeviceAbbreviation>_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
|
||||
|
||||
/* Peripheral memory map */
|
||||
#define <DeviceAbbreviation>TIM0_BASE (<DeviceAbbreviation>_PERIPH_BASE) /*!< (Timer0 ) Base Address */
|
||||
#define <DeviceAbbreviation>TIM1_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (Timer1 ) Base Address */
|
||||
#define <DeviceAbbreviation>TIM2_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (Timer2 ) Base Address */
|
||||
/*@}*/ /* end of group <Device>_MemoryMap */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* Peripheral declaration */
|
||||
/******************************************************************************/
|
||||
/* ToDo: add here your device peripherals pointer definitions
|
||||
following is an example for timer */
|
||||
|
||||
/** @addtogroup <Device>_PeripheralDecl <Device> Peripheral Declaration
|
||||
@{
|
||||
*/
|
||||
|
||||
#define <DeviceAbbreviation>_TIM0 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
|
||||
#define <DeviceAbbreviation>_TIM1 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
|
||||
#define <DeviceAbbreviation>_TIM2 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>TIM0_BASE)
|
||||
/*@}*/ /* end of group <Device>_PeripheralDecl */
|
||||
|
||||
/*@}*/ /* end of group <Device>_Definitions */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* <Device>_H */
|
||||
</pre> </div></div><!-- contents -->
|
||||
</div><!-- doc-content -->
|
||||
<!-- start footer part -->
|
||||
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
|
||||
<ul>
|
||||
<li class="navelem"><a class="el" href="_templates_pg.html">Template Files</a></li>
|
||||
<li class="footer">Generated on Tue Oct 27 2015 14:35:21 for CMSIS-CORE by ARM Ltd. All rights reserved.
|
||||
<!--
|
||||
<a href="http://www.doxygen.org/index.html">
|
||||
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.2
|
||||
-->
|
||||
</li>
|
||||
</ul>
|
||||
</div>
|
||||
</body>
|
||||
</html>
|
||||
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|
After Width: | Height: | Size: 3.7 KiB |
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|
||||
function toggleVisibility(linkObj)
|
||||
{
|
||||
var base = $(linkObj).attr('id');
|
||||
var summary = $('#'+base+'-summary');
|
||||
var content = $('#'+base+'-content');
|
||||
var trigger = $('#'+base+'-trigger');
|
||||
var src=$(trigger).attr('src');
|
||||
if (content.is(':visible')===true) {
|
||||
content.hide();
|
||||
summary.show();
|
||||
$(linkObj).addClass('closed').removeClass('opened');
|
||||
$(trigger).attr('src',src.substring(0,src.length-8)+'closed.png');
|
||||
} else {
|
||||
content.show();
|
||||
summary.hide();
|
||||
$(linkObj).removeClass('closed').addClass('opened');
|
||||
$(trigger).attr('src',src.substring(0,src.length-10)+'open.png');
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
function updateStripes()
|
||||
{
|
||||
$('table.directory tr').
|
||||
removeClass('even').filter(':visible:even').addClass('even');
|
||||
}
|
||||
function toggleLevel(level)
|
||||
{
|
||||
$('table.directory tr').each(function(){
|
||||
var l = this.id.split('_').length-1;
|
||||
var i = $('#img'+this.id.substring(3));
|
||||
var a = $('#arr'+this.id.substring(3));
|
||||
if (l<level+1) {
|
||||
i.attr('src','ftv2folderopen.png');
|
||||
a.attr('src','ftv2mnode.png');
|
||||
$(this).show();
|
||||
} else if (l==level+1) {
|
||||
i.attr('src','ftv2folderclosed.png');
|
||||
a.attr('src','ftv2pnode.png');
|
||||
$(this).show();
|
||||
} else {
|
||||
$(this).hide();
|
||||
}
|
||||
});
|
||||
updateStripes();
|
||||
}
|
||||
function toggleFolder(id)
|
||||
{
|
||||
var n = $('[id^=row_'+id+']');
|
||||
var i = $('[id^=img_'+id+']');
|
||||
var a = $('[id^=arr_'+id+']');
|
||||
var c = n.slice(1);
|
||||
if (c.filter(':first').is(':visible')===true) {
|
||||
i.attr('src','ftv2folderclosed.png');
|
||||
a.attr('src','ftv2pnode.png');
|
||||
c.hide();
|
||||
} else {
|
||||
i.attr('src','ftv2folderopen.png');
|
||||
a.attr('src','ftv2mnode.png');
|
||||
c.show();
|
||||
}
|
||||
updateStripes();
|
||||
}
|
||||
|
||||
function toggleInherit(id)
|
||||
{
|
||||
var rows = $('tr.inherit.'+id);
|
||||
var img = $('tr.inherit_header.'+id+' img');
|
||||
var src = $(img).attr('src');
|
||||
if (rows.filter(':first').is(':visible')===true) {
|
||||
rows.css('display','none');
|
||||
$(img).attr('src',src.substring(0,src.length-8)+'closed.png');
|
||||
} else {
|
||||
rows.css('display','table-row'); // using show() causes jump in firefox
|
||||
$(img).attr('src',src.substring(0,src.length-10)+'open.png');
|
||||
}
|
||||
}
|
||||
|
||||
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|
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<td style="padding-left: 0.5em;">
|
||||
<div id="projectname">CMSIS-CORE
|
||||
 <span id="projectnumber">Version 4.30</span>
|
||||
</div>
|
||||
<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
|
||||
</td>
|
||||
</tr>
|
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</tbody>
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</table>
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<input type="text" id="MSearchField" value="Search" accesskey="S"
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<a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
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<li><a href="#index_a"><span>a</span></a></li>
|
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<li><a href="#index_b"><span>b</span></a></li>
|
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<li><a href="#index_c"><span>c</span></a></li>
|
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<li><a href="#index_d"><span>d</span></a></li>
|
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<li><a href="#index_e"><span>e</span></a></li>
|
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<li><a href="#index_f"><span>f</span></a></li>
|
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<li><a href="#index_h"><span>h</span></a></li>
|
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<li><a href="#index_i"><span>i</span></a></li>
|
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<li><a href="#index_l"><span>l</span></a></li>
|
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<li><a href="#index_m"><span>m</span></a></li>
|
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<li><a href="#index_n"><span>n</span></a></li>
|
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<li><a href="#index_p"><span>p</span></a></li>
|
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<li><a href="#index_q"><span>q</span></a></li>
|
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<li><a href="#index_r"><span>r</span></a></li>
|
||||
<li><a href="#index_s"><span>s</span></a></li>
|
||||
<li><a href="#index_t"><span>t</span></a></li>
|
||||
<li><a href="#index_u"><span>u</span></a></li>
|
||||
<li><a href="#index_v"><span>v</span></a></li>
|
||||
<li><a href="#index_w"><span>w</span></a></li>
|
||||
<li><a href="#index_z"><span>z</span></a></li>
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</ul>
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class="ui-resizable-handle">
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onmouseover="return searchBox.OnSearchSelectShow()"
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onmouseout="return searchBox.OnSearchSelectHide()"
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onkeydown="return searchBox.OnSearchSelectKey(event)">
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<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div>
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name="MSearchResults" id="MSearchResults">
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</iframe>
|
||||
</div>
|
||||
|
||||
<div class="contents">
|
||||
<div class="textblock">Here is a list of all struct and union fields with links to the structures/unions they belong to:</div>
|
||||
|
||||
<h3><a class="anchor" id="index__"></a>- _ -</h3><ul>
|
||||
<li>_reserved0
|
||||
: <a class="el" href="union_a_p_s_r___type.html#afbce95646fd514c10aa85ec0a33db728">APSR_Type</a>
|
||||
, <a class="el" href="union_c_o_n_t_r_o_l___type.html#af8c314273a1e4970a5671bd7f8184f50">CONTROL_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#af438e0f407357e914a70b5bd4d6a97c5">xPSR_Type</a>
|
||||
, <a class="el" href="union_i_p_s_r___type.html#ad2eb0a06de4f03f58874a727716aa9aa">IPSR_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_a"></a>- a -</h3><ul>
|
||||
<li>ACPR
|
||||
: <a class="el" href="struct_t_p_i___type.html#a9e5e4421ef9c3d5b7ff8b24abd4e99b3">TPI_Type</a>
|
||||
</li>
|
||||
<li>ACTLR
|
||||
: <a class="el" href="struct_s_cn_s_c_b___type.html#a13af9b718dde7481f1c0344f00593c23">SCnSCB_Type</a>
|
||||
</li>
|
||||
<li>ADR
|
||||
: <a class="el" href="struct_s_c_b___type.html#af084e1b2dad004a88668efea1dfe7fa1">SCB_Type</a>
|
||||
</li>
|
||||
<li>AFSR
|
||||
: <a class="el" href="struct_s_c_b___type.html#ab65372404ce64b0f0b35e2709429404e">SCB_Type</a>
|
||||
</li>
|
||||
<li>AIRCR
|
||||
: <a class="el" href="struct_s_c_b___type.html#ad3e5b8934c647eb1b7383c1894f01380">SCB_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_b"></a>- b -</h3><ul>
|
||||
<li>b
|
||||
: <a class="el" href="union_a_p_s_r___type.html#a7dbc79a057ded4b11ca5323fc2d5ab14">APSR_Type</a>
|
||||
, <a class="el" href="union_i_p_s_r___type.html#add0d6497bd50c25569ea22b48a03ec50">IPSR_Type</a>
|
||||
, <a class="el" href="union_c_o_n_t_r_o_l___type.html#adc6a38ab2980d0e9577b5a871da14eb9">CONTROL_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#a3b1063bb5cdad67e037cba993b693b70">xPSR_Type</a>
|
||||
</li>
|
||||
<li>BFAR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a3f8e7e58be4e41c88dfa78f54589271c">SCB_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_c"></a>- c -</h3><ul>
|
||||
<li>C
|
||||
: <a class="el" href="union_a_p_s_r___type.html#a86e2c5b891ecef1ab55b1edac0da79a6">APSR_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#a40213a6b5620410cac83b0d89564609d">xPSR_Type</a>
|
||||
</li>
|
||||
<li>CALIB
|
||||
: <a class="el" href="struct_sys_tick___type.html#afcadb0c6d35b21cdc0018658a13942de">SysTick_Type</a>
|
||||
</li>
|
||||
<li>CCR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a2d6653b0b70faac936046a02809b577f">SCB_Type</a>
|
||||
</li>
|
||||
<li>CFSR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a0cda9e061b42373383418663092ad19a">SCB_Type</a>
|
||||
</li>
|
||||
<li>CLAIMCLR
|
||||
: <a class="el" href="struct_t_p_i___type.html#a0e10e292cb019a832b03ddd055b2f6ac">TPI_Type</a>
|
||||
</li>
|
||||
<li>CLAIMSET
|
||||
: <a class="el" href="struct_t_p_i___type.html#af8b7d15fa5252b733dd4b11fa1b5730a">TPI_Type</a>
|
||||
</li>
|
||||
<li>COMP0
|
||||
: <a class="el" href="struct_d_w_t___type.html#a61c2965af5bc0643f9af65620b0e67c9">DWT_Type</a>
|
||||
</li>
|
||||
<li>COMP1
|
||||
: <a class="el" href="struct_d_w_t___type.html#a38714af6b7fa7c64d68f5e1efbe7a931">DWT_Type</a>
|
||||
</li>
|
||||
<li>COMP2
|
||||
: <a class="el" href="struct_d_w_t___type.html#a5ae6dde39989f27bae90afc2347deb46">DWT_Type</a>
|
||||
</li>
|
||||
<li>COMP3
|
||||
: <a class="el" href="struct_d_w_t___type.html#a85eb73d1848ac3f82d39d6c3e8910847">DWT_Type</a>
|
||||
</li>
|
||||
<li>CPACR
|
||||
: <a class="el" href="struct_s_c_b___type.html#ac6a860c1b8d8154a1f00d99d23b67764">SCB_Type</a>
|
||||
</li>
|
||||
<li>CPICNT
|
||||
: <a class="el" href="struct_d_w_t___type.html#a2c08096c82abe245c0fa97badc458154">DWT_Type</a>
|
||||
</li>
|
||||
<li>CPUID
|
||||
: <a class="el" href="struct_s_c_b___type.html#a21e08d546d8b641bee298a459ea73e46">SCB_Type</a>
|
||||
</li>
|
||||
<li>CSPSR
|
||||
: <a class="el" href="struct_t_p_i___type.html#a8826aa84e5806053395a742d38d59d0f">TPI_Type</a>
|
||||
</li>
|
||||
<li>CTRL
|
||||
: <a class="el" href="struct_d_w_t___type.html#add790c53410023b3b581919bb681fe2a">DWT_Type</a>
|
||||
, <a class="el" href="struct_m_p_u___type.html#a4d81d6aa73a9287bafba2bcc5ffc6d18">MPU_Type</a>
|
||||
, <a class="el" href="struct_sys_tick___type.html#a875e7afa5c4fd43997fb544a4ac6e37e">SysTick_Type</a>
|
||||
</li>
|
||||
<li>CYCCNT
|
||||
: <a class="el" href="struct_d_w_t___type.html#a102eaa529d9098242851cb57c52b42d9">DWT_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_d"></a>- d -</h3><ul>
|
||||
<li>DCRDR
|
||||
: <a class="el" href="struct_core_debug___type.html#aab3cc92ef07bc1f04b3a3aa6db2c2d55">CoreDebug_Type</a>
|
||||
</li>
|
||||
<li>DCRSR
|
||||
: <a class="el" href="struct_core_debug___type.html#af907cf64577eaf927dac6787df6dd98b">CoreDebug_Type</a>
|
||||
</li>
|
||||
<li>DEMCR
|
||||
: <a class="el" href="struct_core_debug___type.html#aeb3126abc4c258a858f21f356c0df6ee">CoreDebug_Type</a>
|
||||
</li>
|
||||
<li>DEVID
|
||||
: <a class="el" href="struct_t_p_i___type.html#abc0ecda8a5446bc754080276bad77514">TPI_Type</a>
|
||||
</li>
|
||||
<li>DEVTYPE
|
||||
: <a class="el" href="struct_t_p_i___type.html#ad98855854a719bbea33061e71529a472">TPI_Type</a>
|
||||
</li>
|
||||
<li>DFR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a85dd6fe77aab17e7ea89a52c59da6004">SCB_Type</a>
|
||||
</li>
|
||||
<li>DFSR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a191579bde0d21ff51d30a714fd887033">SCB_Type</a>
|
||||
</li>
|
||||
<li>DHCSR
|
||||
: <a class="el" href="struct_core_debug___type.html#ad63554e4650da91a8e79929cbb63db66">CoreDebug_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_e"></a>- e -</h3><ul>
|
||||
<li>EXCCNT
|
||||
: <a class="el" href="struct_d_w_t___type.html#a9fe20c16c5167ca61486caf6832686d1">DWT_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_f"></a>- f -</h3><ul>
|
||||
<li>FFCR
|
||||
: <a class="el" href="struct_t_p_i___type.html#a3f68b6e73561b4849ebf953a894df8d2">TPI_Type</a>
|
||||
</li>
|
||||
<li>FFSR
|
||||
: <a class="el" href="struct_t_p_i___type.html#a6c47a0b4c7ffc66093ef993d36bb441c">TPI_Type</a>
|
||||
</li>
|
||||
<li>FIFO0
|
||||
: <a class="el" href="struct_t_p_i___type.html#aa4d7b5cf39dff9f53bf7f69bc287a814">TPI_Type</a>
|
||||
</li>
|
||||
<li>FIFO1
|
||||
: <a class="el" href="struct_t_p_i___type.html#a061372fcd72f1eea871e2d9c1be849bc">TPI_Type</a>
|
||||
</li>
|
||||
<li>FOLDCNT
|
||||
: <a class="el" href="struct_d_w_t___type.html#a1cfc48384ebd8fd8fb7e5d955aae6c97">DWT_Type</a>
|
||||
</li>
|
||||
<li>FPCA
|
||||
: <a class="el" href="union_c_o_n_t_r_o_l___type.html#ac62cfff08e6f055e0101785bad7094cd">CONTROL_Type</a>
|
||||
</li>
|
||||
<li>FPCAR
|
||||
: <a class="el" href="struct_f_p_u___type.html#a55263b468d0f8e11ac77aec9ff87c820">FPU_Type</a>
|
||||
</li>
|
||||
<li>FPCCR
|
||||
: <a class="el" href="struct_f_p_u___type.html#af1b708c5e413739150df3d16ca3b7061">FPU_Type</a>
|
||||
</li>
|
||||
<li>FPDSCR
|
||||
: <a class="el" href="struct_f_p_u___type.html#a58d1989664a06db6ec2e122eefa9f04a">FPU_Type</a>
|
||||
</li>
|
||||
<li>FSCR
|
||||
: <a class="el" href="struct_t_p_i___type.html#ad6901bfd8a0089ca7e8a20475cf494a8">TPI_Type</a>
|
||||
</li>
|
||||
<li>FUNCTION0
|
||||
: <a class="el" href="struct_d_w_t___type.html#a579ae082f58a0317b7ef029b20f52889">DWT_Type</a>
|
||||
</li>
|
||||
<li>FUNCTION1
|
||||
: <a class="el" href="struct_d_w_t___type.html#a8dfcf25675f9606aa305c46e85182e4e">DWT_Type</a>
|
||||
</li>
|
||||
<li>FUNCTION2
|
||||
: <a class="el" href="struct_d_w_t___type.html#ab1b60d6600c38abae515bab8e86a188f">DWT_Type</a>
|
||||
</li>
|
||||
<li>FUNCTION3
|
||||
: <a class="el" href="struct_d_w_t___type.html#a52d4ff278fae6f9216c63b74ce328841">DWT_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_h"></a>- h -</h3><ul>
|
||||
<li>HFSR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a14ad254659362b9752c69afe3fd80934">SCB_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_i"></a>- i -</h3><ul>
|
||||
<li>IABR
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a4bca5452748ba84d64536fb6a5d795af">NVIC_Type</a>
|
||||
</li>
|
||||
<li>ICER
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a245df8bac1da05c39eadabede9323203">NVIC_Type</a>
|
||||
</li>
|
||||
<li>ICPR
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a8d8f45d9c5c67bba3c153c55574bac95">NVIC_Type</a>
|
||||
</li>
|
||||
<li>ICSR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a0ca18ef984d132c6bf4d9b61cd00f05a">SCB_Type</a>
|
||||
</li>
|
||||
<li>ICTR
|
||||
: <a class="el" href="struct_s_cn_s_c_b___type.html#a34ec1d771245eb9bd0e3ec9336949762">SCnSCB_Type</a>
|
||||
</li>
|
||||
<li>IP
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a7ff7364a4260df67a2784811e8da4efd">NVIC_Type</a>
|
||||
</li>
|
||||
<li>ISAR
|
||||
: <a class="el" href="struct_s_c_b___type.html#ae0136a2d2d3c45f016b2c449e92b2066">SCB_Type</a>
|
||||
</li>
|
||||
<li>ISER
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a9fccef5a60a0d5e81fcd7869a6274f47">NVIC_Type</a>
|
||||
</li>
|
||||
<li>ISPR
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a8f731a9f428efc86e8d311b52ce823d0">NVIC_Type</a>
|
||||
</li>
|
||||
<li>ISR
|
||||
: <a class="el" href="union_i_p_s_r___type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5">IPSR_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#a3e9120dcf1a829fc8d2302b4d0673970">xPSR_Type</a>
|
||||
</li>
|
||||
<li>IT
|
||||
: <a class="el" href="unionx_p_s_r___type.html#a3200966922a194d84425e2807a7f1328">xPSR_Type</a>
|
||||
</li>
|
||||
<li>ITATBCTR0
|
||||
: <a class="el" href="struct_t_p_i___type.html#aaa573b2e073e76e93c51ecec79c616d0">TPI_Type</a>
|
||||
</li>
|
||||
<li>ITATBCTR2
|
||||
: <a class="el" href="struct_t_p_i___type.html#ab358319b969d3fed0f89bbe33e9f1652">TPI_Type</a>
|
||||
</li>
|
||||
<li>ITCTRL
|
||||
: <a class="el" href="struct_t_p_i___type.html#aaa4c823c10f115f7517c82ef86a5a68d">TPI_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_l"></a>- l -</h3><ul>
|
||||
<li>LOAD
|
||||
: <a class="el" href="struct_sys_tick___type.html#a4780a489256bb9f54d0ba8ed4de191cd">SysTick_Type</a>
|
||||
</li>
|
||||
<li>LSUCNT
|
||||
: <a class="el" href="struct_d_w_t___type.html#acc05d89bdb1b4fe2fa499920ec02d0b1">DWT_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_m"></a>- m -</h3><ul>
|
||||
<li>MASK0
|
||||
: <a class="el" href="struct_d_w_t___type.html#a821eb5e71f340ec077efc064cfc567db">DWT_Type</a>
|
||||
</li>
|
||||
<li>MASK1
|
||||
: <a class="el" href="struct_d_w_t___type.html#aabf94936c9340e62fed836dcfb152405">DWT_Type</a>
|
||||
</li>
|
||||
<li>MASK2
|
||||
: <a class="el" href="struct_d_w_t___type.html#a00ac4d830dfe0070a656cda9baed170f">DWT_Type</a>
|
||||
</li>
|
||||
<li>MASK3
|
||||
: <a class="el" href="struct_d_w_t___type.html#a2a509d8505c37a3b64f6b24993df5f3f">DWT_Type</a>
|
||||
</li>
|
||||
<li>MMFAR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a2d03d0b7cec2254f39eb1c46c7445e80">SCB_Type</a>
|
||||
</li>
|
||||
<li>MMFR
|
||||
: <a class="el" href="struct_s_c_b___type.html#aa11887804412bda283cc85a83fdafa7c">SCB_Type</a>
|
||||
</li>
|
||||
<li>MVFR0
|
||||
: <a class="el" href="struct_f_p_u___type.html#a4f19014defe6033d070b80af19ef627c">FPU_Type</a>
|
||||
</li>
|
||||
<li>MVFR1
|
||||
: <a class="el" href="struct_f_p_u___type.html#a66f8cfa49a423b480001a4e101bf842d">FPU_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_n"></a>- n -</h3><ul>
|
||||
<li>N
|
||||
: <a class="el" href="union_a_p_s_r___type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0">APSR_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#a2db9a52f6d42809627d1a7a607c5dbc5">xPSR_Type</a>
|
||||
</li>
|
||||
<li>nPRIV
|
||||
: <a class="el" href="union_c_o_n_t_r_o_l___type.html#a35c1732cf153b7b5c4bd321cf1de9605">CONTROL_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_p"></a>- p -</h3><ul>
|
||||
<li>PCSR
|
||||
: <a class="el" href="struct_d_w_t___type.html#a6353ca1d1ad9bc1be05d3b5632960113">DWT_Type</a>
|
||||
</li>
|
||||
<li>PFR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a681c9d9e518b217976bef38c2423d83d">SCB_Type</a>
|
||||
</li>
|
||||
<li>PORT
|
||||
: <a class="el" href="struct_i_t_m___type.html#af4c205be465780a20098387120bdb482">ITM_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_q"></a>- q -</h3><ul>
|
||||
<li>Q
|
||||
: <a class="el" href="union_a_p_s_r___type.html#a22d10913489d24ab08bd83457daa88de">APSR_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#add7cbd2b0abd8954d62cd7831796ac7c">xPSR_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_r"></a>- r -</h3><ul>
|
||||
<li>RASR
|
||||
: <a class="el" href="struct_m_p_u___type.html#a9236c629b7cf86f8bd2459c610fdf715">MPU_Type</a>
|
||||
</li>
|
||||
<li>RASR_A1
|
||||
: <a class="el" href="struct_m_p_u___type.html#ab5a224ccd12ac55ddfe11d9eca42de48">MPU_Type</a>
|
||||
</li>
|
||||
<li>RASR_A2
|
||||
: <a class="el" href="struct_m_p_u___type.html#ac60e0919871b66446a039838bcaaec3b">MPU_Type</a>
|
||||
</li>
|
||||
<li>RASR_A3
|
||||
: <a class="el" href="struct_m_p_u___type.html#a9c0b2d3e3e16bb4e7dfa069652d5a155">MPU_Type</a>
|
||||
</li>
|
||||
<li>RBAR
|
||||
: <a class="el" href="struct_m_p_u___type.html#ac953770d38a7d322b971d93eb8a5b062">MPU_Type</a>
|
||||
</li>
|
||||
<li>RBAR_A1
|
||||
: <a class="el" href="struct_m_p_u___type.html#a13d69b9bea12861383f3a62764b02f63">MPU_Type</a>
|
||||
</li>
|
||||
<li>RBAR_A2
|
||||
: <a class="el" href="struct_m_p_u___type.html#a57dc551614932150e684fcc60590c2c4">MPU_Type</a>
|
||||
</li>
|
||||
<li>RBAR_A3
|
||||
: <a class="el" href="struct_m_p_u___type.html#a345911aabecd1f7d93a1bff7738b0d86">MPU_Type</a>
|
||||
</li>
|
||||
<li>RESERVED0
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a2de17698945ea49abd58a2d45bdc9c80">NVIC_Type</a>
|
||||
, <a class="el" href="struct_s_c_b___type.html#ac89a5d9901e3748d22a7090bfca2bee6">SCB_Type</a>
|
||||
, <a class="el" href="struct_s_cn_s_c_b___type.html#afe1d5fd2966d5062716613b05c8d0ae1">SCnSCB_Type</a>
|
||||
, <a class="el" href="struct_i_t_m___type.html#a2c5ae30385b5f370d023468ea9914c0e">ITM_Type</a>
|
||||
, <a class="el" href="struct_f_p_u___type.html#a7b2967b069046c8544adbbc1db143a36">FPU_Type</a>
|
||||
, <a class="el" href="struct_d_w_t___type.html#addd893d655ed90d40705b20170daac59">DWT_Type</a>
|
||||
, <a class="el" href="struct_t_p_i___type.html#af143c5e8fc9a3b2be2878e9c1f331aa9">TPI_Type</a>
|
||||
</li>
|
||||
<li>RESERVED1
|
||||
: <a class="el" href="struct_i_t_m___type.html#afffce5b93bbfedbaee85357d0b07ebce">ITM_Type</a>
|
||||
, <a class="el" href="struct_d_w_t___type.html#a069871233a8c1df03521e6d7094f1de4">DWT_Type</a>
|
||||
, <a class="el" href="struct_t_p_i___type.html#ac3956fe93987b725d89d3be32738da12">TPI_Type</a>
|
||||
</li>
|
||||
<li>RESERVED2
|
||||
: <a class="el" href="struct_i_t_m___type.html#af56b2f07bc6b42cd3e4d17e1b27cff7b">ITM_Type</a>
|
||||
, <a class="el" href="struct_d_w_t___type.html#a8556ca1c32590517602d92fe0cd55738">DWT_Type</a>
|
||||
, <a class="el" href="struct_t_p_i___type.html#ac7bbb92e6231b9b38ac483f7d161a096">TPI_Type</a>
|
||||
, <a class="el" href="struct_n_v_i_c___type.html#a0953af43af8ec7fd5869a1d826ce5b72">NVIC_Type</a>
|
||||
</li>
|
||||
<li>RESERVED3
|
||||
: <a class="el" href="struct_t_p_i___type.html#a31700c8cdd26e4c094db72af33d9f24c">TPI_Type</a>
|
||||
, <a class="el" href="struct_n_v_i_c___type.html#a9dd330835dbf21471e7b5be8692d77ab">NVIC_Type</a>
|
||||
</li>
|
||||
<li>RESERVED4
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790">NVIC_Type</a>
|
||||
, <a class="el" href="struct_t_p_i___type.html#a684071216fafee4e80be6aaa932cec46">TPI_Type</a>
|
||||
</li>
|
||||
<li>RESERVED5
|
||||
: <a class="el" href="struct_t_p_i___type.html#a3f80dd93f6bab6524603a7aa58de9a30">TPI_Type</a>
|
||||
, <a class="el" href="struct_n_v_i_c___type.html#a4f753b4f824270175af045ac99bc12e8">NVIC_Type</a>
|
||||
</li>
|
||||
<li>RESERVED7
|
||||
: <a class="el" href="struct_t_p_i___type.html#a476ca23fbc9480f1697fbec871130550">TPI_Type</a>
|
||||
</li>
|
||||
<li>RNR
|
||||
: <a class="el" href="struct_m_p_u___type.html#aa800d44f4d3520cc891d7b8d711320c1">MPU_Type</a>
|
||||
</li>
|
||||
<li>RSERVED1
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe">NVIC_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_s"></a>- s -</h3><ul>
|
||||
<li>SCR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a3a4840c6fa4d1ee75544f4032c88ec34">SCB_Type</a>
|
||||
</li>
|
||||
<li>SHCSR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a7b5ae9741a99808043394c4743b635c4">SCB_Type</a>
|
||||
</li>
|
||||
<li>SHP
|
||||
: <a class="el" href="struct_s_c_b___type.html#a85768f4b3dbbc41fd760041ee1202162">SCB_Type</a>
|
||||
</li>
|
||||
<li>SLEEPCNT
|
||||
: <a class="el" href="struct_d_w_t___type.html#a416a54e2084ce66e5ca74f152a5ecc70">DWT_Type</a>
|
||||
</li>
|
||||
<li>SPPR
|
||||
: <a class="el" href="struct_t_p_i___type.html#a12f79d4e3ddc69893ba8bff890d04cc5">TPI_Type</a>
|
||||
</li>
|
||||
<li>SPSEL
|
||||
: <a class="el" href="union_c_o_n_t_r_o_l___type.html#a8cc085fea1c50a8bd9adea63931ee8e2">CONTROL_Type</a>
|
||||
</li>
|
||||
<li>SSPSR
|
||||
: <a class="el" href="struct_t_p_i___type.html#a7b72598e20066133e505bb781690dc22">TPI_Type</a>
|
||||
</li>
|
||||
<li>STIR
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a37de89637466e007171c6b135299bc75">NVIC_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_t"></a>- t -</h3><ul>
|
||||
<li>T
|
||||
: <a class="el" href="unionx_p_s_r___type.html#a7eed9fe24ae8d354cd76ae1c1110a658">xPSR_Type</a>
|
||||
</li>
|
||||
<li>TCR
|
||||
: <a class="el" href="struct_i_t_m___type.html#a04b9fbc83759cb818dfa161d39628426">ITM_Type</a>
|
||||
</li>
|
||||
<li>TER
|
||||
: <a class="el" href="struct_i_t_m___type.html#acd03c6858f7b678dab6a6121462e7807">ITM_Type</a>
|
||||
</li>
|
||||
<li>TPR
|
||||
: <a class="el" href="struct_i_t_m___type.html#ae907229ba50538bf370fbdfd54c099a2">ITM_Type</a>
|
||||
</li>
|
||||
<li>TRIGGER
|
||||
: <a class="el" href="struct_t_p_i___type.html#a4d4cd2357f72333a82a1313228287bbd">TPI_Type</a>
|
||||
</li>
|
||||
<li>TYPE
|
||||
: <a class="el" href="struct_m_p_u___type.html#a0433efc1383674bc8e86cc0e830b462d">MPU_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_u"></a>- u -</h3><ul>
|
||||
<li>u16
|
||||
: <a class="el" href="struct_i_t_m___type.html#a962a970dfd286cad7f8a8577e87d4ad3">ITM_Type</a>
|
||||
</li>
|
||||
<li>u32
|
||||
: <a class="el" href="struct_i_t_m___type.html#a5834885903a557674f078f3b71fa8bc8">ITM_Type</a>
|
||||
</li>
|
||||
<li>u8
|
||||
: <a class="el" href="struct_i_t_m___type.html#ae773bf9f9dac64e6c28b14aa39f74275">ITM_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_v"></a>- v -</h3><ul>
|
||||
<li>V
|
||||
: <a class="el" href="union_a_p_s_r___type.html#a8004d224aacb78ca37774c35f9156e7e">APSR_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#af14df16ea0690070c45b95f2116b7a0a">xPSR_Type</a>
|
||||
</li>
|
||||
<li>VAL
|
||||
: <a class="el" href="struct_sys_tick___type.html#a9b5420d17e8e43104ddd4ae5a610af93">SysTick_Type</a>
|
||||
</li>
|
||||
<li>VTOR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a187a4578e920544ed967f98020fb8170">SCB_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_w"></a>- w -</h3><ul>
|
||||
<li>w
|
||||
: <a class="el" href="union_a_p_s_r___type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94">APSR_Type</a>
|
||||
, <a class="el" href="union_c_o_n_t_r_o_l___type.html#a6b642cca3d96da660b1198c133ca2a1f">CONTROL_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#a1a47176768f45f79076c4f5b1b534bc2">xPSR_Type</a>
|
||||
, <a class="el" href="union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879">IPSR_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_z"></a>- z -</h3><ul>
|
||||
<li>Z
|
||||
: <a class="el" href="union_a_p_s_r___type.html#a3b04d58738b66a28ff13f23d8b0ba7e5">APSR_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#a1e5d9801013d5146f2e02d9b7b3da562">xPSR_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- contents -->
|
||||
</div><!-- doc-content -->
|
||||
<!-- start footer part -->
|
||||
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
|
||||
<ul>
|
||||
<li class="footer">Generated on Tue Oct 27 2015 14:35:22 for CMSIS-CORE by ARM Ltd. All rights reserved.
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<!--
|
||||
<a href="http://www.doxygen.org/index.html">
|
||||
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.2
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-->
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</li>
|
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</ul>
|
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</div>
|
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</body>
|
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</html>
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@@ -0,0 +1,627 @@
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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$(document).ready(function() { searchBox.OnSelectItem(0); });
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|
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<td style="padding-left: 0.5em;">
|
||||
<div id="projectname">CMSIS-CORE
|
||||
 <span id="projectnumber">Version 4.30</span>
|
||||
</div>
|
||||
<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
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</table>
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<!-- end header part -->
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writeComponentTabs.call(this);
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//-->
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<script type="text/javascript">
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var searchBox = new SearchBox("searchBox", "search",false,'Search');
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<ul class="tablist">
|
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<li><a href="index.html"><span>Main Page</span></a></li>
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<li><a href="pages.html"><span>Usage and Description</span></a></li>
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<div id="MSearchBox" class="MSearchBoxInactive">
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<span class="left">
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<img id="MSearchSelect" src="search/mag_sel.png"
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onmouseover="return searchBox.OnSearchSelectShow()"
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onmouseout="return searchBox.OnSearchSelectHide()"
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alt=""/>
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<input type="text" id="MSearchField" value="Search" accesskey="S"
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onfocus="searchBox.OnSearchFieldFocus(true)"
|
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onblur="searchBox.OnSearchFieldFocus(false)"
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onkeyup="searchBox.OnSearchFieldChange(event)"/>
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</span><span class="right">
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<a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
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</li>
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</ul>
|
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</div>
|
||||
<div id="navrow2" class="tabs2">
|
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<ul class="tablist">
|
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<li><a href="annotated.html"><span>Data Structures</span></a></li>
|
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<li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
|
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</ul>
|
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</div>
|
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<div id="navrow3" class="tabs2">
|
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<ul class="tablist">
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<li><a href="functions.html"><span>All</span></a></li>
|
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<li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
|
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</ul>
|
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</div>
|
||||
<div id="navrow4" class="tabs3">
|
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<ul class="tablist">
|
||||
<li><a href="#index__"><span>_</span></a></li>
|
||||
<li><a href="#index_a"><span>a</span></a></li>
|
||||
<li><a href="#index_b"><span>b</span></a></li>
|
||||
<li><a href="#index_c"><span>c</span></a></li>
|
||||
<li><a href="#index_d"><span>d</span></a></li>
|
||||
<li><a href="#index_e"><span>e</span></a></li>
|
||||
<li><a href="#index_f"><span>f</span></a></li>
|
||||
<li><a href="#index_h"><span>h</span></a></li>
|
||||
<li><a href="#index_i"><span>i</span></a></li>
|
||||
<li><a href="#index_l"><span>l</span></a></li>
|
||||
<li><a href="#index_m"><span>m</span></a></li>
|
||||
<li><a href="#index_n"><span>n</span></a></li>
|
||||
<li><a href="#index_p"><span>p</span></a></li>
|
||||
<li><a href="#index_q"><span>q</span></a></li>
|
||||
<li><a href="#index_r"><span>r</span></a></li>
|
||||
<li><a href="#index_s"><span>s</span></a></li>
|
||||
<li><a href="#index_t"><span>t</span></a></li>
|
||||
<li><a href="#index_u"><span>u</span></a></li>
|
||||
<li><a href="#index_v"><span>v</span></a></li>
|
||||
<li><a href="#index_w"><span>w</span></a></li>
|
||||
<li><a href="#index_z"><span>z</span></a></li>
|
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</ul>
|
||||
</div>
|
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</div><!-- top -->
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<div id="side-nav" class="ui-resizable side-nav-resizable">
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</div>
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</div>
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<div id="splitbar" style="-moz-user-select:none;"
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class="ui-resizable-handle">
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</div>
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</div>
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<script type="text/javascript">
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$(document).ready(function(){initNavTree('functions_vars.html','');});
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<div id="doc-content">
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<!-- window showing the filter options -->
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<div id="MSearchSelectWindow"
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onmouseover="return searchBox.OnSearchSelectShow()"
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onmouseout="return searchBox.OnSearchSelectHide()"
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onkeydown="return searchBox.OnSearchSelectKey(event)">
|
||||
<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div>
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<div id="MSearchResultsWindow">
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<iframe src="javascript:void(0)" frameborder="0"
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name="MSearchResults" id="MSearchResults">
|
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</iframe>
|
||||
</div>
|
||||
|
||||
<div class="contents">
|
||||
 
|
||||
|
||||
<h3><a class="anchor" id="index__"></a>- _ -</h3><ul>
|
||||
<li>_reserved0
|
||||
: <a class="el" href="union_a_p_s_r___type.html#afbce95646fd514c10aa85ec0a33db728">APSR_Type</a>
|
||||
, <a class="el" href="union_c_o_n_t_r_o_l___type.html#af8c314273a1e4970a5671bd7f8184f50">CONTROL_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#af438e0f407357e914a70b5bd4d6a97c5">xPSR_Type</a>
|
||||
, <a class="el" href="union_i_p_s_r___type.html#ad2eb0a06de4f03f58874a727716aa9aa">IPSR_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_a"></a>- a -</h3><ul>
|
||||
<li>ACPR
|
||||
: <a class="el" href="struct_t_p_i___type.html#a9e5e4421ef9c3d5b7ff8b24abd4e99b3">TPI_Type</a>
|
||||
</li>
|
||||
<li>ACTLR
|
||||
: <a class="el" href="struct_s_cn_s_c_b___type.html#a13af9b718dde7481f1c0344f00593c23">SCnSCB_Type</a>
|
||||
</li>
|
||||
<li>ADR
|
||||
: <a class="el" href="struct_s_c_b___type.html#af084e1b2dad004a88668efea1dfe7fa1">SCB_Type</a>
|
||||
</li>
|
||||
<li>AFSR
|
||||
: <a class="el" href="struct_s_c_b___type.html#ab65372404ce64b0f0b35e2709429404e">SCB_Type</a>
|
||||
</li>
|
||||
<li>AIRCR
|
||||
: <a class="el" href="struct_s_c_b___type.html#ad3e5b8934c647eb1b7383c1894f01380">SCB_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_b"></a>- b -</h3><ul>
|
||||
<li>b
|
||||
: <a class="el" href="union_a_p_s_r___type.html#a7dbc79a057ded4b11ca5323fc2d5ab14">APSR_Type</a>
|
||||
, <a class="el" href="union_i_p_s_r___type.html#add0d6497bd50c25569ea22b48a03ec50">IPSR_Type</a>
|
||||
, <a class="el" href="union_c_o_n_t_r_o_l___type.html#adc6a38ab2980d0e9577b5a871da14eb9">CONTROL_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#a3b1063bb5cdad67e037cba993b693b70">xPSR_Type</a>
|
||||
</li>
|
||||
<li>BFAR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a3f8e7e58be4e41c88dfa78f54589271c">SCB_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_c"></a>- c -</h3><ul>
|
||||
<li>C
|
||||
: <a class="el" href="union_a_p_s_r___type.html#a86e2c5b891ecef1ab55b1edac0da79a6">APSR_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#a40213a6b5620410cac83b0d89564609d">xPSR_Type</a>
|
||||
</li>
|
||||
<li>CALIB
|
||||
: <a class="el" href="struct_sys_tick___type.html#afcadb0c6d35b21cdc0018658a13942de">SysTick_Type</a>
|
||||
</li>
|
||||
<li>CCR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a2d6653b0b70faac936046a02809b577f">SCB_Type</a>
|
||||
</li>
|
||||
<li>CFSR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a0cda9e061b42373383418663092ad19a">SCB_Type</a>
|
||||
</li>
|
||||
<li>CLAIMCLR
|
||||
: <a class="el" href="struct_t_p_i___type.html#a0e10e292cb019a832b03ddd055b2f6ac">TPI_Type</a>
|
||||
</li>
|
||||
<li>CLAIMSET
|
||||
: <a class="el" href="struct_t_p_i___type.html#af8b7d15fa5252b733dd4b11fa1b5730a">TPI_Type</a>
|
||||
</li>
|
||||
<li>COMP0
|
||||
: <a class="el" href="struct_d_w_t___type.html#a61c2965af5bc0643f9af65620b0e67c9">DWT_Type</a>
|
||||
</li>
|
||||
<li>COMP1
|
||||
: <a class="el" href="struct_d_w_t___type.html#a38714af6b7fa7c64d68f5e1efbe7a931">DWT_Type</a>
|
||||
</li>
|
||||
<li>COMP2
|
||||
: <a class="el" href="struct_d_w_t___type.html#a5ae6dde39989f27bae90afc2347deb46">DWT_Type</a>
|
||||
</li>
|
||||
<li>COMP3
|
||||
: <a class="el" href="struct_d_w_t___type.html#a85eb73d1848ac3f82d39d6c3e8910847">DWT_Type</a>
|
||||
</li>
|
||||
<li>CPACR
|
||||
: <a class="el" href="struct_s_c_b___type.html#ac6a860c1b8d8154a1f00d99d23b67764">SCB_Type</a>
|
||||
</li>
|
||||
<li>CPICNT
|
||||
: <a class="el" href="struct_d_w_t___type.html#a2c08096c82abe245c0fa97badc458154">DWT_Type</a>
|
||||
</li>
|
||||
<li>CPUID
|
||||
: <a class="el" href="struct_s_c_b___type.html#a21e08d546d8b641bee298a459ea73e46">SCB_Type</a>
|
||||
</li>
|
||||
<li>CSPSR
|
||||
: <a class="el" href="struct_t_p_i___type.html#a8826aa84e5806053395a742d38d59d0f">TPI_Type</a>
|
||||
</li>
|
||||
<li>CTRL
|
||||
: <a class="el" href="struct_d_w_t___type.html#add790c53410023b3b581919bb681fe2a">DWT_Type</a>
|
||||
, <a class="el" href="struct_m_p_u___type.html#a4d81d6aa73a9287bafba2bcc5ffc6d18">MPU_Type</a>
|
||||
, <a class="el" href="struct_sys_tick___type.html#a875e7afa5c4fd43997fb544a4ac6e37e">SysTick_Type</a>
|
||||
</li>
|
||||
<li>CYCCNT
|
||||
: <a class="el" href="struct_d_w_t___type.html#a102eaa529d9098242851cb57c52b42d9">DWT_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_d"></a>- d -</h3><ul>
|
||||
<li>DCRDR
|
||||
: <a class="el" href="struct_core_debug___type.html#aab3cc92ef07bc1f04b3a3aa6db2c2d55">CoreDebug_Type</a>
|
||||
</li>
|
||||
<li>DCRSR
|
||||
: <a class="el" href="struct_core_debug___type.html#af907cf64577eaf927dac6787df6dd98b">CoreDebug_Type</a>
|
||||
</li>
|
||||
<li>DEMCR
|
||||
: <a class="el" href="struct_core_debug___type.html#aeb3126abc4c258a858f21f356c0df6ee">CoreDebug_Type</a>
|
||||
</li>
|
||||
<li>DEVID
|
||||
: <a class="el" href="struct_t_p_i___type.html#abc0ecda8a5446bc754080276bad77514">TPI_Type</a>
|
||||
</li>
|
||||
<li>DEVTYPE
|
||||
: <a class="el" href="struct_t_p_i___type.html#ad98855854a719bbea33061e71529a472">TPI_Type</a>
|
||||
</li>
|
||||
<li>DFR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a85dd6fe77aab17e7ea89a52c59da6004">SCB_Type</a>
|
||||
</li>
|
||||
<li>DFSR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a191579bde0d21ff51d30a714fd887033">SCB_Type</a>
|
||||
</li>
|
||||
<li>DHCSR
|
||||
: <a class="el" href="struct_core_debug___type.html#ad63554e4650da91a8e79929cbb63db66">CoreDebug_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_e"></a>- e -</h3><ul>
|
||||
<li>EXCCNT
|
||||
: <a class="el" href="struct_d_w_t___type.html#a9fe20c16c5167ca61486caf6832686d1">DWT_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_f"></a>- f -</h3><ul>
|
||||
<li>FFCR
|
||||
: <a class="el" href="struct_t_p_i___type.html#a3f68b6e73561b4849ebf953a894df8d2">TPI_Type</a>
|
||||
</li>
|
||||
<li>FFSR
|
||||
: <a class="el" href="struct_t_p_i___type.html#a6c47a0b4c7ffc66093ef993d36bb441c">TPI_Type</a>
|
||||
</li>
|
||||
<li>FIFO0
|
||||
: <a class="el" href="struct_t_p_i___type.html#aa4d7b5cf39dff9f53bf7f69bc287a814">TPI_Type</a>
|
||||
</li>
|
||||
<li>FIFO1
|
||||
: <a class="el" href="struct_t_p_i___type.html#a061372fcd72f1eea871e2d9c1be849bc">TPI_Type</a>
|
||||
</li>
|
||||
<li>FOLDCNT
|
||||
: <a class="el" href="struct_d_w_t___type.html#a1cfc48384ebd8fd8fb7e5d955aae6c97">DWT_Type</a>
|
||||
</li>
|
||||
<li>FPCA
|
||||
: <a class="el" href="union_c_o_n_t_r_o_l___type.html#ac62cfff08e6f055e0101785bad7094cd">CONTROL_Type</a>
|
||||
</li>
|
||||
<li>FPCAR
|
||||
: <a class="el" href="struct_f_p_u___type.html#a55263b468d0f8e11ac77aec9ff87c820">FPU_Type</a>
|
||||
</li>
|
||||
<li>FPCCR
|
||||
: <a class="el" href="struct_f_p_u___type.html#af1b708c5e413739150df3d16ca3b7061">FPU_Type</a>
|
||||
</li>
|
||||
<li>FPDSCR
|
||||
: <a class="el" href="struct_f_p_u___type.html#a58d1989664a06db6ec2e122eefa9f04a">FPU_Type</a>
|
||||
</li>
|
||||
<li>FSCR
|
||||
: <a class="el" href="struct_t_p_i___type.html#ad6901bfd8a0089ca7e8a20475cf494a8">TPI_Type</a>
|
||||
</li>
|
||||
<li>FUNCTION0
|
||||
: <a class="el" href="struct_d_w_t___type.html#a579ae082f58a0317b7ef029b20f52889">DWT_Type</a>
|
||||
</li>
|
||||
<li>FUNCTION1
|
||||
: <a class="el" href="struct_d_w_t___type.html#a8dfcf25675f9606aa305c46e85182e4e">DWT_Type</a>
|
||||
</li>
|
||||
<li>FUNCTION2
|
||||
: <a class="el" href="struct_d_w_t___type.html#ab1b60d6600c38abae515bab8e86a188f">DWT_Type</a>
|
||||
</li>
|
||||
<li>FUNCTION3
|
||||
: <a class="el" href="struct_d_w_t___type.html#a52d4ff278fae6f9216c63b74ce328841">DWT_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_h"></a>- h -</h3><ul>
|
||||
<li>HFSR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a14ad254659362b9752c69afe3fd80934">SCB_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_i"></a>- i -</h3><ul>
|
||||
<li>IABR
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a4bca5452748ba84d64536fb6a5d795af">NVIC_Type</a>
|
||||
</li>
|
||||
<li>ICER
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a245df8bac1da05c39eadabede9323203">NVIC_Type</a>
|
||||
</li>
|
||||
<li>ICPR
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a8d8f45d9c5c67bba3c153c55574bac95">NVIC_Type</a>
|
||||
</li>
|
||||
<li>ICSR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a0ca18ef984d132c6bf4d9b61cd00f05a">SCB_Type</a>
|
||||
</li>
|
||||
<li>ICTR
|
||||
: <a class="el" href="struct_s_cn_s_c_b___type.html#a34ec1d771245eb9bd0e3ec9336949762">SCnSCB_Type</a>
|
||||
</li>
|
||||
<li>IP
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a7ff7364a4260df67a2784811e8da4efd">NVIC_Type</a>
|
||||
</li>
|
||||
<li>ISAR
|
||||
: <a class="el" href="struct_s_c_b___type.html#ae0136a2d2d3c45f016b2c449e92b2066">SCB_Type</a>
|
||||
</li>
|
||||
<li>ISER
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a9fccef5a60a0d5e81fcd7869a6274f47">NVIC_Type</a>
|
||||
</li>
|
||||
<li>ISPR
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a8f731a9f428efc86e8d311b52ce823d0">NVIC_Type</a>
|
||||
</li>
|
||||
<li>ISR
|
||||
: <a class="el" href="union_i_p_s_r___type.html#ab46e5f1b2f4d17cfb9aca4fffcbb2fa5">IPSR_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#a3e9120dcf1a829fc8d2302b4d0673970">xPSR_Type</a>
|
||||
</li>
|
||||
<li>IT
|
||||
: <a class="el" href="unionx_p_s_r___type.html#a3200966922a194d84425e2807a7f1328">xPSR_Type</a>
|
||||
</li>
|
||||
<li>ITATBCTR0
|
||||
: <a class="el" href="struct_t_p_i___type.html#aaa573b2e073e76e93c51ecec79c616d0">TPI_Type</a>
|
||||
</li>
|
||||
<li>ITATBCTR2
|
||||
: <a class="el" href="struct_t_p_i___type.html#ab358319b969d3fed0f89bbe33e9f1652">TPI_Type</a>
|
||||
</li>
|
||||
<li>ITCTRL
|
||||
: <a class="el" href="struct_t_p_i___type.html#aaa4c823c10f115f7517c82ef86a5a68d">TPI_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_l"></a>- l -</h3><ul>
|
||||
<li>LOAD
|
||||
: <a class="el" href="struct_sys_tick___type.html#a4780a489256bb9f54d0ba8ed4de191cd">SysTick_Type</a>
|
||||
</li>
|
||||
<li>LSUCNT
|
||||
: <a class="el" href="struct_d_w_t___type.html#acc05d89bdb1b4fe2fa499920ec02d0b1">DWT_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_m"></a>- m -</h3><ul>
|
||||
<li>MASK0
|
||||
: <a class="el" href="struct_d_w_t___type.html#a821eb5e71f340ec077efc064cfc567db">DWT_Type</a>
|
||||
</li>
|
||||
<li>MASK1
|
||||
: <a class="el" href="struct_d_w_t___type.html#aabf94936c9340e62fed836dcfb152405">DWT_Type</a>
|
||||
</li>
|
||||
<li>MASK2
|
||||
: <a class="el" href="struct_d_w_t___type.html#a00ac4d830dfe0070a656cda9baed170f">DWT_Type</a>
|
||||
</li>
|
||||
<li>MASK3
|
||||
: <a class="el" href="struct_d_w_t___type.html#a2a509d8505c37a3b64f6b24993df5f3f">DWT_Type</a>
|
||||
</li>
|
||||
<li>MMFAR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a2d03d0b7cec2254f39eb1c46c7445e80">SCB_Type</a>
|
||||
</li>
|
||||
<li>MMFR
|
||||
: <a class="el" href="struct_s_c_b___type.html#aa11887804412bda283cc85a83fdafa7c">SCB_Type</a>
|
||||
</li>
|
||||
<li>MVFR0
|
||||
: <a class="el" href="struct_f_p_u___type.html#a4f19014defe6033d070b80af19ef627c">FPU_Type</a>
|
||||
</li>
|
||||
<li>MVFR1
|
||||
: <a class="el" href="struct_f_p_u___type.html#a66f8cfa49a423b480001a4e101bf842d">FPU_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_n"></a>- n -</h3><ul>
|
||||
<li>N
|
||||
: <a class="el" href="union_a_p_s_r___type.html#a7e7bbba9b00b0bb3283dc07f1abe37e0">APSR_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#a2db9a52f6d42809627d1a7a607c5dbc5">xPSR_Type</a>
|
||||
</li>
|
||||
<li>nPRIV
|
||||
: <a class="el" href="union_c_o_n_t_r_o_l___type.html#a35c1732cf153b7b5c4bd321cf1de9605">CONTROL_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_p"></a>- p -</h3><ul>
|
||||
<li>PCSR
|
||||
: <a class="el" href="struct_d_w_t___type.html#a6353ca1d1ad9bc1be05d3b5632960113">DWT_Type</a>
|
||||
</li>
|
||||
<li>PFR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a681c9d9e518b217976bef38c2423d83d">SCB_Type</a>
|
||||
</li>
|
||||
<li>PORT
|
||||
: <a class="el" href="struct_i_t_m___type.html#af4c205be465780a20098387120bdb482">ITM_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_q"></a>- q -</h3><ul>
|
||||
<li>Q
|
||||
: <a class="el" href="union_a_p_s_r___type.html#a22d10913489d24ab08bd83457daa88de">APSR_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#add7cbd2b0abd8954d62cd7831796ac7c">xPSR_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_r"></a>- r -</h3><ul>
|
||||
<li>RASR
|
||||
: <a class="el" href="struct_m_p_u___type.html#a9236c629b7cf86f8bd2459c610fdf715">MPU_Type</a>
|
||||
</li>
|
||||
<li>RASR_A1
|
||||
: <a class="el" href="struct_m_p_u___type.html#ab5a224ccd12ac55ddfe11d9eca42de48">MPU_Type</a>
|
||||
</li>
|
||||
<li>RASR_A2
|
||||
: <a class="el" href="struct_m_p_u___type.html#ac60e0919871b66446a039838bcaaec3b">MPU_Type</a>
|
||||
</li>
|
||||
<li>RASR_A3
|
||||
: <a class="el" href="struct_m_p_u___type.html#a9c0b2d3e3e16bb4e7dfa069652d5a155">MPU_Type</a>
|
||||
</li>
|
||||
<li>RBAR
|
||||
: <a class="el" href="struct_m_p_u___type.html#ac953770d38a7d322b971d93eb8a5b062">MPU_Type</a>
|
||||
</li>
|
||||
<li>RBAR_A1
|
||||
: <a class="el" href="struct_m_p_u___type.html#a13d69b9bea12861383f3a62764b02f63">MPU_Type</a>
|
||||
</li>
|
||||
<li>RBAR_A2
|
||||
: <a class="el" href="struct_m_p_u___type.html#a57dc551614932150e684fcc60590c2c4">MPU_Type</a>
|
||||
</li>
|
||||
<li>RBAR_A3
|
||||
: <a class="el" href="struct_m_p_u___type.html#a345911aabecd1f7d93a1bff7738b0d86">MPU_Type</a>
|
||||
</li>
|
||||
<li>RESERVED0
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a2de17698945ea49abd58a2d45bdc9c80">NVIC_Type</a>
|
||||
, <a class="el" href="struct_s_c_b___type.html#ac89a5d9901e3748d22a7090bfca2bee6">SCB_Type</a>
|
||||
, <a class="el" href="struct_s_cn_s_c_b___type.html#afe1d5fd2966d5062716613b05c8d0ae1">SCnSCB_Type</a>
|
||||
, <a class="el" href="struct_i_t_m___type.html#a2c5ae30385b5f370d023468ea9914c0e">ITM_Type</a>
|
||||
, <a class="el" href="struct_f_p_u___type.html#a7b2967b069046c8544adbbc1db143a36">FPU_Type</a>
|
||||
, <a class="el" href="struct_d_w_t___type.html#addd893d655ed90d40705b20170daac59">DWT_Type</a>
|
||||
, <a class="el" href="struct_t_p_i___type.html#af143c5e8fc9a3b2be2878e9c1f331aa9">TPI_Type</a>
|
||||
</li>
|
||||
<li>RESERVED1
|
||||
: <a class="el" href="struct_i_t_m___type.html#afffce5b93bbfedbaee85357d0b07ebce">ITM_Type</a>
|
||||
, <a class="el" href="struct_d_w_t___type.html#a069871233a8c1df03521e6d7094f1de4">DWT_Type</a>
|
||||
, <a class="el" href="struct_t_p_i___type.html#ac3956fe93987b725d89d3be32738da12">TPI_Type</a>
|
||||
</li>
|
||||
<li>RESERVED2
|
||||
: <a class="el" href="struct_i_t_m___type.html#af56b2f07bc6b42cd3e4d17e1b27cff7b">ITM_Type</a>
|
||||
, <a class="el" href="struct_d_w_t___type.html#a8556ca1c32590517602d92fe0cd55738">DWT_Type</a>
|
||||
, <a class="el" href="struct_t_p_i___type.html#ac7bbb92e6231b9b38ac483f7d161a096">TPI_Type</a>
|
||||
, <a class="el" href="struct_n_v_i_c___type.html#a0953af43af8ec7fd5869a1d826ce5b72">NVIC_Type</a>
|
||||
</li>
|
||||
<li>RESERVED3
|
||||
: <a class="el" href="struct_t_p_i___type.html#a31700c8cdd26e4c094db72af33d9f24c">TPI_Type</a>
|
||||
, <a class="el" href="struct_n_v_i_c___type.html#a9dd330835dbf21471e7b5be8692d77ab">NVIC_Type</a>
|
||||
</li>
|
||||
<li>RESERVED4
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a5c0e5d507ac3c1bd5cdaaf9bbd177790">NVIC_Type</a>
|
||||
, <a class="el" href="struct_t_p_i___type.html#a684071216fafee4e80be6aaa932cec46">TPI_Type</a>
|
||||
</li>
|
||||
<li>RESERVED5
|
||||
: <a class="el" href="struct_t_p_i___type.html#a3f80dd93f6bab6524603a7aa58de9a30">TPI_Type</a>
|
||||
, <a class="el" href="struct_n_v_i_c___type.html#a4f753b4f824270175af045ac99bc12e8">NVIC_Type</a>
|
||||
</li>
|
||||
<li>RESERVED7
|
||||
: <a class="el" href="struct_t_p_i___type.html#a476ca23fbc9480f1697fbec871130550">TPI_Type</a>
|
||||
</li>
|
||||
<li>RNR
|
||||
: <a class="el" href="struct_m_p_u___type.html#aa800d44f4d3520cc891d7b8d711320c1">MPU_Type</a>
|
||||
</li>
|
||||
<li>RSERVED1
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a6d1daf7ab6f2ba83f57ff67ae6f571fe">NVIC_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_s"></a>- s -</h3><ul>
|
||||
<li>SCR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a3a4840c6fa4d1ee75544f4032c88ec34">SCB_Type</a>
|
||||
</li>
|
||||
<li>SHCSR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a7b5ae9741a99808043394c4743b635c4">SCB_Type</a>
|
||||
</li>
|
||||
<li>SHP
|
||||
: <a class="el" href="struct_s_c_b___type.html#a85768f4b3dbbc41fd760041ee1202162">SCB_Type</a>
|
||||
</li>
|
||||
<li>SLEEPCNT
|
||||
: <a class="el" href="struct_d_w_t___type.html#a416a54e2084ce66e5ca74f152a5ecc70">DWT_Type</a>
|
||||
</li>
|
||||
<li>SPPR
|
||||
: <a class="el" href="struct_t_p_i___type.html#a12f79d4e3ddc69893ba8bff890d04cc5">TPI_Type</a>
|
||||
</li>
|
||||
<li>SPSEL
|
||||
: <a class="el" href="union_c_o_n_t_r_o_l___type.html#a8cc085fea1c50a8bd9adea63931ee8e2">CONTROL_Type</a>
|
||||
</li>
|
||||
<li>SSPSR
|
||||
: <a class="el" href="struct_t_p_i___type.html#a7b72598e20066133e505bb781690dc22">TPI_Type</a>
|
||||
</li>
|
||||
<li>STIR
|
||||
: <a class="el" href="struct_n_v_i_c___type.html#a37de89637466e007171c6b135299bc75">NVIC_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_t"></a>- t -</h3><ul>
|
||||
<li>T
|
||||
: <a class="el" href="unionx_p_s_r___type.html#a7eed9fe24ae8d354cd76ae1c1110a658">xPSR_Type</a>
|
||||
</li>
|
||||
<li>TCR
|
||||
: <a class="el" href="struct_i_t_m___type.html#a04b9fbc83759cb818dfa161d39628426">ITM_Type</a>
|
||||
</li>
|
||||
<li>TER
|
||||
: <a class="el" href="struct_i_t_m___type.html#acd03c6858f7b678dab6a6121462e7807">ITM_Type</a>
|
||||
</li>
|
||||
<li>TPR
|
||||
: <a class="el" href="struct_i_t_m___type.html#ae907229ba50538bf370fbdfd54c099a2">ITM_Type</a>
|
||||
</li>
|
||||
<li>TRIGGER
|
||||
: <a class="el" href="struct_t_p_i___type.html#a4d4cd2357f72333a82a1313228287bbd">TPI_Type</a>
|
||||
</li>
|
||||
<li>TYPE
|
||||
: <a class="el" href="struct_m_p_u___type.html#a0433efc1383674bc8e86cc0e830b462d">MPU_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_u"></a>- u -</h3><ul>
|
||||
<li>u16
|
||||
: <a class="el" href="struct_i_t_m___type.html#a962a970dfd286cad7f8a8577e87d4ad3">ITM_Type</a>
|
||||
</li>
|
||||
<li>u32
|
||||
: <a class="el" href="struct_i_t_m___type.html#a5834885903a557674f078f3b71fa8bc8">ITM_Type</a>
|
||||
</li>
|
||||
<li>u8
|
||||
: <a class="el" href="struct_i_t_m___type.html#ae773bf9f9dac64e6c28b14aa39f74275">ITM_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_v"></a>- v -</h3><ul>
|
||||
<li>V
|
||||
: <a class="el" href="union_a_p_s_r___type.html#a8004d224aacb78ca37774c35f9156e7e">APSR_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#af14df16ea0690070c45b95f2116b7a0a">xPSR_Type</a>
|
||||
</li>
|
||||
<li>VAL
|
||||
: <a class="el" href="struct_sys_tick___type.html#a9b5420d17e8e43104ddd4ae5a610af93">SysTick_Type</a>
|
||||
</li>
|
||||
<li>VTOR
|
||||
: <a class="el" href="struct_s_c_b___type.html#a187a4578e920544ed967f98020fb8170">SCB_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_w"></a>- w -</h3><ul>
|
||||
<li>w
|
||||
: <a class="el" href="union_a_p_s_r___type.html#ae4c2ef8c9430d7b7bef5cbfbbaed3a94">APSR_Type</a>
|
||||
, <a class="el" href="union_c_o_n_t_r_o_l___type.html#a6b642cca3d96da660b1198c133ca2a1f">CONTROL_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#a1a47176768f45f79076c4f5b1b534bc2">xPSR_Type</a>
|
||||
, <a class="el" href="union_i_p_s_r___type.html#a4adca999d3a0bc1ae682d73ea7cfa879">IPSR_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_z"></a>- z -</h3><ul>
|
||||
<li>Z
|
||||
: <a class="el" href="union_a_p_s_r___type.html#a3b04d58738b66a28ff13f23d8b0ba7e5">APSR_Type</a>
|
||||
, <a class="el" href="unionx_p_s_r___type.html#a1e5d9801013d5146f2e02d9b7b3da562">xPSR_Type</a>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- contents -->
|
||||
</div><!-- doc-content -->
|
||||
<!-- start footer part -->
|
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<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
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<ul>
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<li class="footer">Generated on Tue Oct 27 2015 14:35:22 for CMSIS-CORE by ARM Ltd. All rights reserved.
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<a href="http://www.doxygen.org/index.html">
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.2
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</html>
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<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
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<div id="top"><!-- do not remove this div, it is closed by doxygen! -->
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<tbody>
|
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<tr style="height: 46px;">
|
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<td id="projectlogo"><img alt="Logo" src="CMSIS_Logo_Final.png"/></td>
|
||||
<td style="padding-left: 0.5em;">
|
||||
<div id="projectname">CMSIS-CORE
|
||||
 <span id="projectnumber">Version 4.30</span>
|
||||
</div>
|
||||
<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
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</div>
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//-->
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var searchBox = new SearchBox("searchBox", "search",false,'Search');
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<li><a href="pages.html"><span>Usage and Description</span></a></li>
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onmouseover="return searchBox.OnSearchSelectShow()"
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onmouseout="return searchBox.OnSearchSelectHide()"
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alt=""/>
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<input type="text" id="MSearchField" value="Search" accesskey="S"
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onfocus="searchBox.OnSearchFieldFocus(true)"
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onblur="searchBox.OnSearchFieldFocus(false)"
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</span><span class="right">
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<a id="MSearchClose" href="javascript:searchBox.CloseResultsWindow()"><img id="MSearchCloseImg" border="0" src="search/close.png" alt=""/></a>
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</ul>
|
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</div>
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<div id="navrow3" class="tabs2">
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<ul class="tablist">
|
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<li class="current"><a href="globals.html"><span>All</span></a></li>
|
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<li><a href="globals_func.html"><span>Functions</span></a></li>
|
||||
<li><a href="globals_vars.html"><span>Variables</span></a></li>
|
||||
<li><a href="globals_enum.html"><span>Enumerations</span></a></li>
|
||||
<li><a href="globals_eval.html"><span>Enumerator</span></a></li>
|
||||
<li><a href="globals_defs.html"><span>Macros</span></a></li>
|
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</ul>
|
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</div>
|
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<div id="navrow4" class="tabs3">
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<ul class="tablist">
|
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<li><a href="#index__"><span>_</span></a></li>
|
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<li><a href="#index_b"><span>b</span></a></li>
|
||||
<li><a href="#index_d"><span>d</span></a></li>
|
||||
<li><a href="#index_h"><span>h</span></a></li>
|
||||
<li><a href="#index_i"><span>i</span></a></li>
|
||||
<li><a href="#index_m"><span>m</span></a></li>
|
||||
<li><a href="#index_n"><span>n</span></a></li>
|
||||
<li><a href="#index_p"><span>p</span></a></li>
|
||||
<li><a href="#index_s"><span>s</span></a></li>
|
||||
<li><a href="#index_u"><span>u</span></a></li>
|
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<li><a href="#index_w"><span>w</span></a></li>
|
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</ul>
|
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</div>
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</div><!-- top -->
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<div id="side-nav" class="ui-resizable side-nav-resizable">
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<div id="nav-tree-contents">
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<div id="nav-sync" class="sync"></div>
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</div>
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class="ui-resizable-handle">
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<script type="text/javascript">
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$(document).ready(function(){initNavTree('globals.html','');});
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</script>
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<div id="doc-content">
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<!-- window showing the filter options -->
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<div id="MSearchSelectWindow"
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onmouseover="return searchBox.OnSearchSelectShow()"
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onmouseout="return searchBox.OnSearchSelectHide()"
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onkeydown="return searchBox.OnSearchSelectKey(event)">
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<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div>
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name="MSearchResults" id="MSearchResults">
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</iframe>
|
||||
</div>
|
||||
|
||||
<div class="contents">
|
||||
<div class="textblock">Here is a list of all functions, variables, defines, enums, and typedefs with links to the files they belong to:</div>
|
||||
|
||||
<h3><a class="anchor" id="index__"></a>- _ -</h3><ul>
|
||||
<li>__BKPT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga92f5621626711931da71eaa8bf301af7">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__CLREX()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__CLZ()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga90884c591ac5d73d6069334eba9d6c02">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__disable_fault_irq()
|
||||
: <a class="el" href="group___core___register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__disable_irq()
|
||||
: <a class="el" href="group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__DMB()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__DSB()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__enable_fault_irq()
|
||||
: <a class="el" href="group___core___register__gr.html#ga6575d37863cec5d334864f93b5b783bf">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__enable_irq()
|
||||
: <a class="el" href="group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_APSR()
|
||||
: <a class="el" href="group___core___register__gr.html#ga811c0012221ee918a75111ca84c4d5e7">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_BASEPRI()
|
||||
: <a class="el" href="group___core___register__gr.html#ga32da759f46e52c95bcfbde5012260667">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_CONTROL()
|
||||
: <a class="el" href="group___core___register__gr.html#ga963cf236b73219ce78e965deb01b81a7">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_FAULTMASK()
|
||||
: <a class="el" href="group___core___register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_FPSCR()
|
||||
: <a class="el" href="group___core___register__gr.html#gad6d7eca9ddd1d9072dd7b020cfe64905">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_IPSR()
|
||||
: <a class="el" href="group___core___register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_MSP()
|
||||
: <a class="el" href="group___core___register__gr.html#gab898559392ba027814e5bbb5a98b38d2">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_PRIMASK()
|
||||
: <a class="el" href="group___core___register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_PSP()
|
||||
: <a class="el" href="group___core___register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_xPSR()
|
||||
: <a class="el" href="group___core___register__gr.html#ga732e08184154f44a617963cc65ff95bd">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__ISB()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga93c09b4709394d81977300d5f84950e5">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__LDRBT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9464d75db32846aa8295c3c3adfacb41">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__LDREXB()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__LDREXH()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__LDREXW()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__LDRHT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaa762b8bc5634ce38cb14d62a6b2aee32">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__LDRT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga616504f5da979ba8a073d428d6e8d5c7">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__NOP()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__PKHBT()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaefb8ebf3a54e197464da1ff69a44f4b5">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__PKHTB()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafd8fe4a6d87e947caa81a69ec36c1666">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QADD()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga17b873f246c9f5e9355760ffef3dad4a">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QADD16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae83a53ec04b496304bed6d9fe8f7461b">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QADD8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf2f5a9132dcfc6d01d34cd971c425713">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QASX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga87618799672e1511e33964bc71467eb3">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QSAX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab41eb2b17512ab01d476fc9d5bd19520">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QSUB()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga3ba259f8f05a36f7b88b469a71ffc096">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QSUB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad089605c16df9823a2c8aaa37777aae5">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QSUB8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga753493a65493880c28baa82c151a0d61">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__RBIT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gad6f9f297f6b91a995ee199fbc796b863">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__REV()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga4717abc17af5ba29b1e4c055e0a0d9b8">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__REV16()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__REVSH()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga1ec006e6d79063363cb0c2a2e0b3adbe">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__ROR()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__RRX()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gac09134f1bf9c49db07282001afcc9380">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__SADD16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad0bf46373a1c05aabf64517e84be5984">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SADD8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac20aa0f741d0a1494d58c531e38d5785">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SASX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5845084fd99c872e98cf5553d554de2a">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SEL()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf5448e591fe49161b6759b48aecb08fe">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__set_BASEPRI()
|
||||
: <a class="el" href="group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__set_BASEPRI_MAX()
|
||||
: <a class="el" href="group___core___register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__set_CONTROL()
|
||||
: <a class="el" href="group___core___register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__set_FAULTMASK()
|
||||
: <a class="el" href="group___core___register__gr.html#gaa5587cc09031053a40a35c14ec36078a">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__set_FPSCR()
|
||||
: <a class="el" href="group___core___register__gr.html#ga6f26bd75ca7e3247f27b272acc10536b">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__set_MSP()
|
||||
: <a class="el" href="group___core___register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__set_PRIMASK()
|
||||
: <a class="el" href="group___core___register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__set_PSP()
|
||||
: <a class="el" href="group___core___register__gr.html#ga48e5853f417e17a8a65080f6a605b743">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__SEV()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__SHADD16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga15d8899a173effb8ad8c7268da32b60e">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SHADD8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga524575b442ea01aec10c762bf4d85fea">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SHASX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae0a649035f67627464fd80e7218c89d5">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SHSAX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafadbd89c36b5addcf1ca10dd392db3e9">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SHSUB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga31328467f0f91b8ff9ae9a01682ad3bf">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SHSUB8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac3ec7215b354d925a239f3b31df2b77b">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLAD()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae0c86f3298532183f3a29f5bb454d354">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLADX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9c286d330f4fb29b256335add91eec9f">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLALD()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad80e9b20c1736fd798f897362273a146">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLALDX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad1adad1b3f2667328cc0db6c6b4f41cf">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLSD()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf4350af7f2030c36f43b2c104a9d16cd">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLSDX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5290ce5564770ad124910d2583dc0a9e">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLSLD()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5611f7314e0c8f53da377918dfbf42ee">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLSLDX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga83e69ef81057d3cbd06863d729385187">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMMLA()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaea60757232f740ec6b09980eebb614ff">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMUAD()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae326e368a1624d2dfb4b97c626939257">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMUADX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaee6390f86965cb662500f690b0012092">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMUSD()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga039142a5368840683cf329cb55b73f84">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMUSDX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gabb5bcba694bf17b141c32e6a8474f60e">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SSAT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga7d9dddda18805abbf51ac21c639845e1">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__SSAT16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga95e666b82216066bf6064d1244e6883c">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SSAX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9d3bc5c539f9bd50f7d59ffa37ac6a65">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SSUB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga4262f73be75efbac6b46ab7c71aa6cbc">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SSUB8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaba63bb52e1e93fb527e26f3d474da12e">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__STRBT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gad41aa59c92c0a165b7f98428d3320cd5">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__STREXB()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__STREXH()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__STREXW()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__STRHT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga2b5d93b8e461755b1072a03df3f1722e">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__STRT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga625bc4ac0b1d50de9bcd13d9f050030e">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__SXTAB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac540b4fc41d30778ba102d2a65db5589">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SXTB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga38dce3dd13ba212e80ec3cff4abeb11a">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UADD16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaa1160f0cf76d6aa292fbad54a1aa6b74">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UADD8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab3d7fd00d113b20fb3741a17394da762">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UASX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga980353d2c72ebb879282e49f592fddc0">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UHADD16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gabd0b0e2da2e6364e176d051687702b86">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UHADD8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga3a14e5485e59bf0f23595b7c2a94eb0b">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UHASX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga028f0732b961fb6e5209326fb3855261">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UHSAX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga09e129e6613329aab87c89f1108b7ed7">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UHSUB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga1f7545b8dc33bb97982731cb9d427a69">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UHSUB8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga48a55df1c3e73923b73819d7c19b392d">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UQADD16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9e2cc5117e79578a08b25f1e89022966">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UQADD8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafa9af218db3934a692fb06fa728d8031">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UQASX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5eff3ae5eabcd73f3049996ca391becb">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UQSAX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gadecfdfabc328d8939d49d996f2fd4482">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UQSUB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5ec4e2e231d15e5c692233feb3806187">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UQSUB8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9736fe816aec74fe886e7fb949734eab">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__USAD8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac8855c07044239ea775c8128013204f0">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__USADA8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad032bd21f013c5d29f5fcb6b0f02bc3f">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__USAT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga76bbe4374a5912362866cdc1ded4064a">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__USAT16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga967f516afff5900cf30f1a81907cdd89">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__USAX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga578a082747436772c482c96d7a58e45e">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__USUB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9f2b77e11fc4a77b26c36c423ed45b4e">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__USUB8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gacb7257dc3b8e9acbd0ef0e31ff87d4b8">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UXTAB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad25ce96db0f17096bbd815f4817faf09">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UXTB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab41d713653b16f8d9fef44d14e397228">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__WFE()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gad3efec76c3bfa2b8528ded530386c563">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__WFI()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>_FLD2VAL
|
||||
: <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">Ref_Peripheral.txt</a>
|
||||
</li>
|
||||
<li>_VAL2FLD
|
||||
: <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">Ref_Peripheral.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_b"></a>- b -</h3><ul>
|
||||
<li>BusFault_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_d"></a>- d -</h3><ul>
|
||||
<li>DebugMonitor_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_h"></a>- h -</h3><ul>
|
||||
<li>HardFault_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_i"></a>- i -</h3><ul>
|
||||
<li>IRQn_Type
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>ITM_CheckChar()
|
||||
: <a class="el" href="group___i_t_m___debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535">Ref_Debug.txt</a>
|
||||
</li>
|
||||
<li>ITM_ReceiveChar()
|
||||
: <a class="el" href="group___i_t_m___debug__gr.html#ga37b8f41cae703b5ff6947e271065558c">Ref_Debug.txt</a>
|
||||
</li>
|
||||
<li>ITM_RxBuffer
|
||||
: <a class="el" href="group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">Ref_Debug.txt</a>
|
||||
</li>
|
||||
<li>ITM_SendChar()
|
||||
: <a class="el" href="group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">Ref_Debug.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_m"></a>- m -</h3><ul>
|
||||
<li>MemoryManagement_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_n"></a>- n -</h3><ul>
|
||||
<li>NonMaskableInt_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_ClearPendingIRQ()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_DecodePriority()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gad3cbca1be7a4726afa9448a9acd89377">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_DisableIRQ()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_EnableIRQ()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_EncodePriority()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga0688c59605b119c53c71b2505ab23eb5">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_GetActive()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gadf4252e600661fd762cfc0d1a9f5b892">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_GetPendingIRQ()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga95a8329a680b051ecf3ee8f516acc662">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_GetPriority()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_GetPriorityGrouping()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gaa81b19849367d3cdb95ac108c500fa78">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_SetPendingIRQ()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga3b885147ef9965ecede49614de8df9d2">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_SetPriority()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_SetPriorityGrouping()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gad78f447e891789b4d8f2e5b21eeda354">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_SystemReset()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_p"></a>- p -</h3><ul>
|
||||
<li>PendSV_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>PVD_STM_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_s"></a>- s -</h3><ul>
|
||||
<li>SCB_CleanDCache()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#ga55583e3065c6eabca204b8b89b121c4c">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_CleanDCache_by_Addr()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#ga696fadbf7b9cc71dad42fab61873a40d">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_CleanInvalidateDCache()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#ga1b741def9e3b2ca97dc9ea49b8ce505c">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_CleanInvalidateDCache_by_Addr()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#ga630131b2572eaa16b569ed364dfc895e">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_DisableDCache()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#ga6468170f90d270caab8116e7a4f0b5fe">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_DisableICache()
|
||||
: <a class="el" href="group___icache__functions__m7.html#gaba757390852f95b3ac2d8638c717d8d8">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_EnableDCache()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#ga63aa640d9006021a796a5dcf9c7180b6">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_EnableICache()
|
||||
: <a class="el" href="group___icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_GetFPUType()
|
||||
: <a class="el" href="group__fpu__functions__m7.html#ga6bcad99ce80a0e7e4ddc6f2379081756">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_InvalidateDCache()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_InvalidateDCache_by_Addr()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_InvalidateICache()
|
||||
: <a class="el" href="group___icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SVCall_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>SystemCoreClock
|
||||
: <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">Ref_SystemAndClock.txt</a>
|
||||
</li>
|
||||
<li>SystemCoreClockUpdate()
|
||||
: <a class="el" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">Ref_SystemAndClock.txt</a>
|
||||
</li>
|
||||
<li>SystemInit()
|
||||
: <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">Ref_SystemAndClock.txt</a>
|
||||
</li>
|
||||
<li>SysTick_Config()
|
||||
: <a class="el" href="group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427">Ref_Systick.txt</a>
|
||||
</li>
|
||||
<li>SysTick_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_u"></a>- u -</h3><ul>
|
||||
<li>UsageFault_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_w"></a>- w -</h3><ul>
|
||||
<li>WWDG_STM_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- contents -->
|
||||
</div><!-- doc-content -->
|
||||
<!-- start footer part -->
|
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<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
|
||||
<ul>
|
||||
<li class="footer">Generated on Tue Oct 27 2015 14:35:22 for CMSIS-CORE by ARM Ltd. All rights reserved.
|
||||
<!--
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<a href="http://www.doxygen.org/index.html">
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<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.2
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|
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|
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|
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|
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</html>
|
||||
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|
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<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
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|
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|
||||
<div id="projectname">CMSIS-CORE
|
||||
 <span id="projectnumber">Version 4.30</span>
|
||||
</div>
|
||||
<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
|
||||
</td>
|
||||
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|
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<div class="contents">
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||||
 <ul>
|
||||
<li>_FLD2VAL
|
||||
: <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">Ref_Peripheral.txt</a>
|
||||
</li>
|
||||
<li>_VAL2FLD
|
||||
: <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">Ref_Peripheral.txt</a>
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|
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||||
</div>
|
||||
|
||||
<div class="contents">
|
||||
 <ul>
|
||||
<li>BusFault_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8693500eff174f16119e96234fee73af">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>DebugMonitor_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a8e033fcef7aed98a31c60a7de206722c">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>HardFault_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ab1a222a34a32f0ef5ac65e714efc1f85">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>MemoryManagement_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a33ff1cf7098de65d61b6354fee6cd5aa">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NonMaskableInt_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8ade177d9c70c89e084093024b932a4e30">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>PendSV_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a03c3cc89984928816d81793fc7bce4a2">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>PVD_STM_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a853e0f318108110e0527f29733d11f86">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>SVCall_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a4ce820b3cc6cf3a796b41aadc0cf1237">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>SysTick_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6dbff8f8543325f3474cbae2446776e7">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>UsageFault_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8a6895237c9443601ac832efa635dd8bbf">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>WWDG_STM_IRQn
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gga7e1129cd8a196f4284d41db3e82ad5c8aa62e040960b4beb6cba107e4703c12d2">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
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<!-- start footer part -->
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|
||||
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|
||||
 <span id="projectnumber">Version 4.30</span>
|
||||
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|
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<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
|
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<li><a href="globals_enum.html"><span>Enumerations</span></a></li>
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<div class="contents">
|
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|
||||
|
||||
<h3><a class="anchor" id="index__"></a>- _ -</h3><ul>
|
||||
<li>__BKPT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga92f5621626711931da71eaa8bf301af7">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__CLREX()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga354c5ac8870cc3dfb823367af9c4b412">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__CLZ()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga90884c591ac5d73d6069334eba9d6c02">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__disable_fault_irq()
|
||||
: <a class="el" href="group___core___register__gr.html#ga9d174f979b2f76fdb3228a9b338fd939">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__disable_irq()
|
||||
: <a class="el" href="group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__DMB()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gab1c9b393641dc2d397b3408fdbe72b96">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__DSB()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gacb2a8ca6eae1ba4b31161578b720c199">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__enable_fault_irq()
|
||||
: <a class="el" href="group___core___register__gr.html#ga6575d37863cec5d334864f93b5b783bf">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__enable_irq()
|
||||
: <a class="el" href="group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_APSR()
|
||||
: <a class="el" href="group___core___register__gr.html#ga811c0012221ee918a75111ca84c4d5e7">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_BASEPRI()
|
||||
: <a class="el" href="group___core___register__gr.html#ga32da759f46e52c95bcfbde5012260667">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_CONTROL()
|
||||
: <a class="el" href="group___core___register__gr.html#ga963cf236b73219ce78e965deb01b81a7">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_FAULTMASK()
|
||||
: <a class="el" href="group___core___register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_FPSCR()
|
||||
: <a class="el" href="group___core___register__gr.html#gad6d7eca9ddd1d9072dd7b020cfe64905">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_IPSR()
|
||||
: <a class="el" href="group___core___register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_MSP()
|
||||
: <a class="el" href="group___core___register__gr.html#gab898559392ba027814e5bbb5a98b38d2">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_PRIMASK()
|
||||
: <a class="el" href="group___core___register__gr.html#ga799b5d9a2ae75e459264c8512c7c0e02">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_PSP()
|
||||
: <a class="el" href="group___core___register__gr.html#ga914dfa8eff7ca53380dd54cf1d8bebd9">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__get_xPSR()
|
||||
: <a class="el" href="group___core___register__gr.html#ga732e08184154f44a617963cc65ff95bd">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__ISB()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga93c09b4709394d81977300d5f84950e5">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__LDRBT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9464d75db32846aa8295c3c3adfacb41">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__LDREXB()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9e3ac13d8dcf4331176b624cf6234a7e">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__LDREXH()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga9feffc093d6f68b120d592a7a0d45a15">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__LDREXW()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gabd78840a0f2464905b7cec791ebc6a4c">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__LDRHT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaa762b8bc5634ce38cb14d62a6b2aee32">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__LDRT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga616504f5da979ba8a073d428d6e8d5c7">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__NOP()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gac71fad9f0a91980fecafcb450ee0a63e">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__PKHBT()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaefb8ebf3a54e197464da1ff69a44f4b5">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__PKHTB()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafd8fe4a6d87e947caa81a69ec36c1666">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QADD()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga17b873f246c9f5e9355760ffef3dad4a">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QADD16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae83a53ec04b496304bed6d9fe8f7461b">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QADD8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf2f5a9132dcfc6d01d34cd971c425713">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QASX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga87618799672e1511e33964bc71467eb3">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QSAX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab41eb2b17512ab01d476fc9d5bd19520">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QSUB()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga3ba259f8f05a36f7b88b469a71ffc096">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QSUB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad089605c16df9823a2c8aaa37777aae5">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__QSUB8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga753493a65493880c28baa82c151a0d61">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__RBIT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gad6f9f297f6b91a995ee199fbc796b863">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__REV()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga4717abc17af5ba29b1e4c055e0a0d9b8">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__REV16()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaeef6f853b6df3a365c838ee5b49a7a26">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__REVSH()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga1ec006e6d79063363cb0c2a2e0b3adbe">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__ROR()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaf66beb577bb9d90424c3d1d7f684c024">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__RRX()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gac09134f1bf9c49db07282001afcc9380">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__SADD16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad0bf46373a1c05aabf64517e84be5984">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SADD8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac20aa0f741d0a1494d58c531e38d5785">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SASX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5845084fd99c872e98cf5553d554de2a">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SEL()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf5448e591fe49161b6759b48aecb08fe">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__set_BASEPRI()
|
||||
: <a class="el" href="group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__set_BASEPRI_MAX()
|
||||
: <a class="el" href="group___core___register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__set_CONTROL()
|
||||
: <a class="el" href="group___core___register__gr.html#gac64d37e7ff9de06437f9fb94bbab8b6c">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__set_FAULTMASK()
|
||||
: <a class="el" href="group___core___register__gr.html#gaa5587cc09031053a40a35c14ec36078a">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__set_FPSCR()
|
||||
: <a class="el" href="group___core___register__gr.html#ga6f26bd75ca7e3247f27b272acc10536b">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__set_MSP()
|
||||
: <a class="el" href="group___core___register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__set_PRIMASK()
|
||||
: <a class="el" href="group___core___register__gr.html#ga70b4e1a6c1c86eb913fb9d6e8400156f">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__set_PSP()
|
||||
: <a class="el" href="group___core___register__gr.html#ga48e5853f417e17a8a65080f6a605b743">Ref_CoreReg.txt</a>
|
||||
</li>
|
||||
<li>__SEV()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga3c34da7eb16496ae2668a5b95fa441e7">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__SHADD16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga15d8899a173effb8ad8c7268da32b60e">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SHADD8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga524575b442ea01aec10c762bf4d85fea">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SHASX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae0a649035f67627464fd80e7218c89d5">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SHSAX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafadbd89c36b5addcf1ca10dd392db3e9">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SHSUB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga31328467f0f91b8ff9ae9a01682ad3bf">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SHSUB8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac3ec7215b354d925a239f3b31df2b77b">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLAD()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae0c86f3298532183f3a29f5bb454d354">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLADX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9c286d330f4fb29b256335add91eec9f">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLALD()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad80e9b20c1736fd798f897362273a146">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLALDX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad1adad1b3f2667328cc0db6c6b4f41cf">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLSD()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaf4350af7f2030c36f43b2c104a9d16cd">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLSDX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5290ce5564770ad124910d2583dc0a9e">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLSLD()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5611f7314e0c8f53da377918dfbf42ee">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMLSLDX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga83e69ef81057d3cbd06863d729385187">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMMLA()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaea60757232f740ec6b09980eebb614ff">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMUAD()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gae326e368a1624d2dfb4b97c626939257">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMUADX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaee6390f86965cb662500f690b0012092">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMUSD()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga039142a5368840683cf329cb55b73f84">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SMUSDX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gabb5bcba694bf17b141c32e6a8474f60e">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SSAT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga7d9dddda18805abbf51ac21c639845e1">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__SSAT16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga95e666b82216066bf6064d1244e6883c">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SSAX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9d3bc5c539f9bd50f7d59ffa37ac6a65">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SSUB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga4262f73be75efbac6b46ab7c71aa6cbc">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SSUB8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaba63bb52e1e93fb527e26f3d474da12e">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__STRBT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gad41aa59c92c0a165b7f98428d3320cd5">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__STREXB()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaab6482d1f59f59e2b6b7efc1af391c99">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__STREXH()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga0a354bdf71caa52f081a4a54e84c8d2a">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__STREXW()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga335deaaa7991490e1450cb7d1e4c5197">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__STRHT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga2b5d93b8e461755b1072a03df3f1722e">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__STRT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga625bc4ac0b1d50de9bcd13d9f050030e">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__SXTAB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac540b4fc41d30778ba102d2a65db5589">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__SXTB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga38dce3dd13ba212e80ec3cff4abeb11a">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UADD16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gaa1160f0cf76d6aa292fbad54a1aa6b74">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UADD8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab3d7fd00d113b20fb3741a17394da762">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UASX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga980353d2c72ebb879282e49f592fddc0">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UHADD16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gabd0b0e2da2e6364e176d051687702b86">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UHADD8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga3a14e5485e59bf0f23595b7c2a94eb0b">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UHASX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga028f0732b961fb6e5209326fb3855261">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UHSAX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga09e129e6613329aab87c89f1108b7ed7">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UHSUB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga1f7545b8dc33bb97982731cb9d427a69">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UHSUB8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga48a55df1c3e73923b73819d7c19b392d">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UQADD16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9e2cc5117e79578a08b25f1e89022966">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UQADD8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gafa9af218db3934a692fb06fa728d8031">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UQASX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5eff3ae5eabcd73f3049996ca391becb">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UQSAX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gadecfdfabc328d8939d49d996f2fd4482">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UQSUB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga5ec4e2e231d15e5c692233feb3806187">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UQSUB8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9736fe816aec74fe886e7fb949734eab">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__USAD8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gac8855c07044239ea775c8128013204f0">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__USADA8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad032bd21f013c5d29f5fcb6b0f02bc3f">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__USAT()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#ga76bbe4374a5912362866cdc1ded4064a">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__USAT16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga967f516afff5900cf30f1a81907cdd89">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__USAX()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga578a082747436772c482c96d7a58e45e">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__USUB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#ga9f2b77e11fc4a77b26c36c423ed45b4e">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__USUB8()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gacb7257dc3b8e9acbd0ef0e31ff87d4b8">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UXTAB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gad25ce96db0f17096bbd815f4817faf09">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__UXTB16()
|
||||
: <a class="el" href="group__intrinsic___s_i_m_d__gr.html#gab41d713653b16f8d9fef44d14e397228">Ref_cm4_simd.txt</a>
|
||||
</li>
|
||||
<li>__WFE()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gad3efec76c3bfa2b8528ded530386c563">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
<li>__WFI()
|
||||
: <a class="el" href="group__intrinsic___c_p_u__gr.html#gaed91dfbf3d7d7b7fba8d912fcbeaad88">Ref_cmInstr.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_i"></a>- i -</h3><ul>
|
||||
<li>ITM_CheckChar()
|
||||
: <a class="el" href="group___i_t_m___debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535">Ref_Debug.txt</a>
|
||||
</li>
|
||||
<li>ITM_ReceiveChar()
|
||||
: <a class="el" href="group___i_t_m___debug__gr.html#ga37b8f41cae703b5ff6947e271065558c">Ref_Debug.txt</a>
|
||||
</li>
|
||||
<li>ITM_SendChar()
|
||||
: <a class="el" href="group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">Ref_Debug.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_n"></a>- n -</h3><ul>
|
||||
<li>NVIC_ClearPendingIRQ()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga382ad6bedd6eecfdabd1b94dd128a01a">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_DecodePriority()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gad3cbca1be7a4726afa9448a9acd89377">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_DisableIRQ()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga736ba13a76eb37ef6e2c253be8b0331c">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_EnableIRQ()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga530ad9fda2ed1c8b70e439ecfe80591f">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_EncodePriority()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga0688c59605b119c53c71b2505ab23eb5">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_GetActive()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gadf4252e600661fd762cfc0d1a9f5b892">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_GetPendingIRQ()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga95a8329a680b051ecf3ee8f516acc662">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_GetPriority()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gab18fb9f6c5f4c70fdd73047f0f7c8395">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_GetPriorityGrouping()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gaa81b19849367d3cdb95ac108c500fa78">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_SetPendingIRQ()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga3b885147ef9965ecede49614de8df9d2">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_SetPriority()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga5bb7f43ad92937c039dee3d36c3c2798">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_SetPriorityGrouping()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#gad78f447e891789b4d8f2e5b21eeda354">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
<li>NVIC_SystemReset()
|
||||
: <a class="el" href="group___n_v_i_c__gr.html#ga1b47d17e90b6a03e7bd1ec6a0d549b46">Ref_NVIC.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
|
||||
|
||||
<h3><a class="anchor" id="index_s"></a>- s -</h3><ul>
|
||||
<li>SCB_CleanDCache()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#ga55583e3065c6eabca204b8b89b121c4c">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_CleanDCache_by_Addr()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#ga696fadbf7b9cc71dad42fab61873a40d">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_CleanInvalidateDCache()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#ga1b741def9e3b2ca97dc9ea49b8ce505c">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_CleanInvalidateDCache_by_Addr()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#ga630131b2572eaa16b569ed364dfc895e">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_DisableDCache()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#ga6468170f90d270caab8116e7a4f0b5fe">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_DisableICache()
|
||||
: <a class="el" href="group___icache__functions__m7.html#gaba757390852f95b3ac2d8638c717d8d8">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_EnableDCache()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#ga63aa640d9006021a796a5dcf9c7180b6">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_EnableICache()
|
||||
: <a class="el" href="group___icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_GetFPUType()
|
||||
: <a class="el" href="group__fpu__functions__m7.html#ga6bcad99ce80a0e7e4ddc6f2379081756">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_InvalidateDCache()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_InvalidateDCache_by_Addr()
|
||||
: <a class="el" href="group___dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SCB_InvalidateICache()
|
||||
: <a class="el" href="group___icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3">core_cm7.txt</a>
|
||||
</li>
|
||||
<li>SystemCoreClockUpdate()
|
||||
: <a class="el" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">Ref_SystemAndClock.txt</a>
|
||||
</li>
|
||||
<li>SystemInit()
|
||||
: <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">Ref_SystemAndClock.txt</a>
|
||||
</li>
|
||||
<li>SysTick_Config()
|
||||
: <a class="el" href="group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427">Ref_Systick.txt</a>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- contents -->
|
||||
</div><!-- doc-content -->
|
||||
<!-- start footer part -->
|
||||
<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
|
||||
<ul>
|
||||
<li class="footer">Generated on Tue Oct 27 2015 14:35:22 for CMSIS-CORE by ARM Ltd. All rights reserved.
|
||||
<!--
|
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<a href="http://www.doxygen.org/index.html">
|
||||
<img class="footer" src="doxygen.png" alt="doxygen"/></a> 1.8.2
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||||
-->
|
||||
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|
||||
</ul>
|
||||
</div>
|
||||
</body>
|
||||
</html>
|
||||
@@ -0,0 +1,142 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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||||
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|
||||
<head>
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||||
<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
|
||||
<meta http-equiv="X-UA-Compatible" content="IE=9"/>
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<title>Globals</title>
|
||||
<title>CMSIS-CORE: Globals</title>
|
||||
<link href="tabs.css" rel="stylesheet" type="text/css"/>
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<link href="cmsis.css" rel="stylesheet" type="text/css" />
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Functions</h2></td></tr>
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<tr class="memitem:ga63aa640d9006021a796a5dcf9c7180b6"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___dcache__functions__m7.html#ga63aa640d9006021a796a5dcf9c7180b6">SCB_EnableDCache</a> (void)</td></tr>
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<tr class="memitem:ga1b741def9e3b2ca97dc9ea49b8ce505c"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___dcache__functions__m7.html#ga1b741def9e3b2ca97dc9ea49b8ce505c">SCB_CleanInvalidateDCache</a> (void)</td></tr>
|
||||
<tr class="memdesc:ga1b741def9e3b2ca97dc9ea49b8ce505c"><td class="mdescLeft"> </td><td class="mdescRight">Clean & Invalidate D-Cache. <a href="#ga1b741def9e3b2ca97dc9ea49b8ce505c"></a><br/></td></tr>
|
||||
<tr class="separator:ga1b741def9e3b2ca97dc9ea49b8ce505c"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
<tr class="memitem:ga503ef7ef58c0773defd15a82f6336c09"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09">SCB_InvalidateDCache_by_Addr</a> (uint32_t *addr, int32_t dsize)</td></tr>
|
||||
<tr class="memdesc:ga503ef7ef58c0773defd15a82f6336c09"><td class="mdescLeft"> </td><td class="mdescRight">D-Cache Invalidate by address. <a href="#ga503ef7ef58c0773defd15a82f6336c09"></a><br/></td></tr>
|
||||
<tr class="separator:ga503ef7ef58c0773defd15a82f6336c09"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
<tr class="memitem:ga696fadbf7b9cc71dad42fab61873a40d"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___dcache__functions__m7.html#ga696fadbf7b9cc71dad42fab61873a40d">SCB_CleanDCache_by_Addr</a> (uint32_t *addr, int32_t dsize)</td></tr>
|
||||
<tr class="memdesc:ga696fadbf7b9cc71dad42fab61873a40d"><td class="mdescLeft"> </td><td class="mdescRight">D-Cache Clean by address. <a href="#ga696fadbf7b9cc71dad42fab61873a40d"></a><br/></td></tr>
|
||||
<tr class="separator:ga696fadbf7b9cc71dad42fab61873a40d"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
<tr class="memitem:ga630131b2572eaa16b569ed364dfc895e"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___dcache__functions__m7.html#ga630131b2572eaa16b569ed364dfc895e">SCB_CleanInvalidateDCache_by_Addr</a> (uint32_t *addr, int32_t dsize)</td></tr>
|
||||
<tr class="memdesc:ga630131b2572eaa16b569ed364dfc895e"><td class="mdescLeft"> </td><td class="mdescRight">D-Cache Clean and Invalidate by address. <a href="#ga630131b2572eaa16b569ed364dfc895e"></a><br/></td></tr>
|
||||
<tr class="separator:ga630131b2572eaa16b569ed364dfc895e"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
</table>
|
||||
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
|
||||
<p>// close ICache functions </p>
|
||||
<h2 class="groupheader">Function Documentation</h2>
|
||||
<a class="anchor" id="ga55583e3065c6eabca204b8b89b121c4c"></a>
|
||||
<div class="memitem">
|
||||
<div class="memproto">
|
||||
<table class="memname">
|
||||
<tr>
|
||||
<td class="memname">__STATIC_INLINE void SCB_CleanDCache </td>
|
||||
<td>(</td>
|
||||
<td class="paramtype">void </td>
|
||||
<td class="paramname"></td><td>)</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><div class="memdoc">
|
||||
<p>The function cleans the entire data cache. </p>
|
||||
|
||||
</div>
|
||||
</div>
|
||||
<a class="anchor" id="ga696fadbf7b9cc71dad42fab61873a40d"></a>
|
||||
<div class="memitem">
|
||||
<div class="memproto">
|
||||
<table class="memname">
|
||||
<tr>
|
||||
<td class="memname">__STATIC_INLINE void SCB_CleanDCache_by_Addr </td>
|
||||
<td>(</td>
|
||||
<td class="paramtype">uint32_t * </td>
|
||||
<td class="paramname"><em>addr</em>, </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="paramkey"></td>
|
||||
<td></td>
|
||||
<td class="paramtype">int32_t </td>
|
||||
<td class="paramname"><em>dsize</em> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>)</td>
|
||||
<td></td><td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><div class="memdoc">
|
||||
<dl class="params"><dt>Parameters</dt><dd>
|
||||
<table class="params">
|
||||
<tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>address (aligned to 32-byte boundary) </td></tr>
|
||||
<tr><td class="paramdir">[in]</td><td class="paramname">dsize</td><td>size of memory block (in number of bytes)</td></tr>
|
||||
</table>
|
||||
</dd>
|
||||
</dl>
|
||||
<p>The function cleans a memory block of size <em>dsize</em> [bytes] starting at address <em>address</em>. The address is aligned to 32-byte boundry. </p>
|
||||
|
||||
</div>
|
||||
</div>
|
||||
<a class="anchor" id="ga1b741def9e3b2ca97dc9ea49b8ce505c"></a>
|
||||
<div class="memitem">
|
||||
<div class="memproto">
|
||||
<table class="memname">
|
||||
<tr>
|
||||
<td class="memname">__STATIC_INLINE void SCB_CleanInvalidateDCache </td>
|
||||
<td>(</td>
|
||||
<td class="paramtype">void </td>
|
||||
<td class="paramname"></td><td>)</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><div class="memdoc">
|
||||
<p>The function cleans and invalidates the entire data cache. </p>
|
||||
|
||||
</div>
|
||||
</div>
|
||||
<a class="anchor" id="ga630131b2572eaa16b569ed364dfc895e"></a>
|
||||
<div class="memitem">
|
||||
<div class="memproto">
|
||||
<table class="memname">
|
||||
<tr>
|
||||
<td class="memname">__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr </td>
|
||||
<td>(</td>
|
||||
<td class="paramtype">uint32_t * </td>
|
||||
<td class="paramname"><em>addr</em>, </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="paramkey"></td>
|
||||
<td></td>
|
||||
<td class="paramtype">int32_t </td>
|
||||
<td class="paramname"><em>dsize</em> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>)</td>
|
||||
<td></td><td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><div class="memdoc">
|
||||
<dl class="params"><dt>Parameters</dt><dd>
|
||||
<table class="params">
|
||||
<tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>address (aligned to 32-byte boundary) </td></tr>
|
||||
<tr><td class="paramdir">[in]</td><td class="paramname">dsize</td><td>size of memory block (in number of bytes)</td></tr>
|
||||
</table>
|
||||
</dd>
|
||||
</dl>
|
||||
<p>The function invalidates and cleans a memory block of size <em>dsize</em> [bytes] starting at address <em>address</em>. The address is aligned to 32-byte boundry. </p>
|
||||
|
||||
</div>
|
||||
</div>
|
||||
<a class="anchor" id="ga6468170f90d270caab8116e7a4f0b5fe"></a>
|
||||
<div class="memitem">
|
||||
<div class="memproto">
|
||||
<table class="memname">
|
||||
<tr>
|
||||
<td class="memname">__STATIC_INLINE void SCB_DisableDCache </td>
|
||||
<td>(</td>
|
||||
<td class="paramtype">void </td>
|
||||
<td class="paramname"></td><td>)</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><div class="memdoc">
|
||||
<p>The function turns off the entire data cache.</p>
|
||||
<dl class="section note"><dt>Note</dt><dd>When disabling the data cache, you must clean (<a class="el" href="group___dcache__functions__m7.html#ga55583e3065c6eabca204b8b89b121c4c">SCB_CleanDCache</a>) the entire cache to ensure that any dirty data is flushed to external memory. </dd></dl>
|
||||
|
||||
</div>
|
||||
</div>
|
||||
<a class="anchor" id="ga63aa640d9006021a796a5dcf9c7180b6"></a>
|
||||
<div class="memitem">
|
||||
<div class="memproto">
|
||||
<table class="memname">
|
||||
<tr>
|
||||
<td class="memname">__STATIC_INLINE void SCB_EnableDCache </td>
|
||||
<td>(</td>
|
||||
<td class="paramtype">void </td>
|
||||
<td class="paramname"></td><td>)</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><div class="memdoc">
|
||||
<p>The function turns on the entire data cache. </p>
|
||||
<dl class="section note"><dt>Note</dt><dd>Before enabling the data cache, you must invalidate the entire data cache (<a class="el" href="group___dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6">SCB_InvalidateDCache</a>), because external memory might have changed from when the cache was disabled.</dd>
|
||||
<dd>
|
||||
After reset, you must invalidate (<a class="el" href="group___dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6">SCB_InvalidateDCache</a>) each cache before enabling it. </dd></dl>
|
||||
|
||||
</div>
|
||||
</div>
|
||||
<a class="anchor" id="gace2d30db08887d0bdb818b8a785a5ce6"></a>
|
||||
<div class="memitem">
|
||||
<div class="memproto">
|
||||
<table class="memname">
|
||||
<tr>
|
||||
<td class="memname">__STATIC_INLINE void SCB_InvalidateDCache </td>
|
||||
<td>(</td>
|
||||
<td class="paramtype">void </td>
|
||||
<td class="paramname"></td><td>)</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><div class="memdoc">
|
||||
<p>The function invalidates the entire data cache.</p>
|
||||
<dl class="section note"><dt>Note</dt><dd>After reset, you must invalidate each cache before enabling (<a class="el" href="group___dcache__functions__m7.html#ga63aa640d9006021a796a5dcf9c7180b6">SCB_EnableDCache</a>) it. </dd></dl>
|
||||
|
||||
</div>
|
||||
</div>
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<a class="anchor" id="ga503ef7ef58c0773defd15a82f6336c09"></a>
|
||||
<div class="memitem">
|
||||
<div class="memproto">
|
||||
<table class="memname">
|
||||
<tr>
|
||||
<td class="memname">__STATIC_INLINE void SCB_InvalidateDCache_by_Addr </td>
|
||||
<td>(</td>
|
||||
<td class="paramtype">uint32_t * </td>
|
||||
<td class="paramname"><em>addr</em>, </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="paramkey"></td>
|
||||
<td></td>
|
||||
<td class="paramtype">int32_t </td>
|
||||
<td class="paramname"><em>dsize</em> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>)</td>
|
||||
<td></td><td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><div class="memdoc">
|
||||
<dl class="params"><dt>Parameters</dt><dd>
|
||||
<table class="params">
|
||||
<tr><td class="paramdir">[in]</td><td class="paramname">addr</td><td>address (aligned to 32-byte boundary) </td></tr>
|
||||
<tr><td class="paramdir">[in]</td><td class="paramname">dsize</td><td>size of memory block (in number of bytes)</td></tr>
|
||||
</table>
|
||||
</dd>
|
||||
</dl>
|
||||
<p>The function invalidates a memory block of size <em>dsize</em> [bytes] starting at address <em>address</em>. The address is aligned to 32-byte boundry. </p>
|
||||
|
||||
</div>
|
||||
</div>
|
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</div><!-- contents -->
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</div><!-- doc-content -->
|
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<!-- start footer part -->
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<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
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<li class="footer">Generated on Tue Oct 27 2015 14:35:21 for CMSIS-CORE by ARM Ltd. All rights reserved.
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+11
@@ -0,0 +1,11 @@
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var group___dcache__functions__m7 =
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[
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[ "SCB_CleanDCache", "group___dcache__functions__m7.html#ga55583e3065c6eabca204b8b89b121c4c", null ],
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[ "SCB_CleanDCache_by_Addr", "group___dcache__functions__m7.html#ga696fadbf7b9cc71dad42fab61873a40d", null ],
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||||
[ "SCB_CleanInvalidateDCache", "group___dcache__functions__m7.html#ga1b741def9e3b2ca97dc9ea49b8ce505c", null ],
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[ "SCB_DisableDCache", "group___dcache__functions__m7.html#ga6468170f90d270caab8116e7a4f0b5fe", null ],
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||||
[ "SCB_EnableDCache", "group___dcache__functions__m7.html#ga63aa640d9006021a796a5dcf9c7180b6", null ],
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||||
[ "SCB_InvalidateDCache", "group___dcache__functions__m7.html#gace2d30db08887d0bdb818b8a785a5ce6", null ],
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[ "SCB_InvalidateDCache_by_Addr", "group___dcache__functions__m7.html#ga503ef7ef58c0773defd15a82f6336c09", null ]
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<div id="projectname">CMSIS-CORE
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 <span id="projectnumber">Version 4.30</span>
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<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
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<li><a href="pages.html"><span>Usage and Description</span></a></li>
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<div class="contents">
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||||
<p>Debug Access to the Instrumented Trace Macrocell (ITM)
|
||||
<a href="#details">More...</a></p>
|
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
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Functions</h2></td></tr>
|
||||
<tr class="memitem:gaaa7c716331f74d644bf6bf25cd3392d1"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a> (uint32_t ch)</td></tr>
|
||||
<tr class="memdesc:gaaa7c716331f74d644bf6bf25cd3392d1"><td class="mdescLeft"> </td><td class="mdescRight">Transmits a character via channel 0. <a href="#gaaa7c716331f74d644bf6bf25cd3392d1"></a><br/></td></tr>
|
||||
<tr class="separator:gaaa7c716331f74d644bf6bf25cd3392d1"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
<tr class="memitem:ga37b8f41cae703b5ff6947e271065558c"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___i_t_m___debug__gr.html#ga37b8f41cae703b5ff6947e271065558c">ITM_ReceiveChar</a> (void)</td></tr>
|
||||
<tr class="memdesc:ga37b8f41cae703b5ff6947e271065558c"><td class="mdescLeft"> </td><td class="mdescRight">ITM Receive Character. <a href="#ga37b8f41cae703b5ff6947e271065558c"></a><br/></td></tr>
|
||||
<tr class="separator:ga37b8f41cae703b5ff6947e271065558c"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
<tr class="memitem:ga7f9bbabd9756d1a7eafb2d9bf27e0535"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___i_t_m___debug__gr.html#ga7f9bbabd9756d1a7eafb2d9bf27e0535">ITM_CheckChar</a> (void)</td></tr>
|
||||
<tr class="memdesc:ga7f9bbabd9756d1a7eafb2d9bf27e0535"><td class="mdescLeft"> </td><td class="mdescRight">ITM Check Character. <a href="#ga7f9bbabd9756d1a7eafb2d9bf27e0535"></a><br/></td></tr>
|
||||
<tr class="separator:ga7f9bbabd9756d1a7eafb2d9bf27e0535"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="var-members"></a>
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Variables</h2></td></tr>
|
||||
<tr class="memitem:ga12e68e55a7badc271b948d6c7230b2a8"><td class="memItemLeft" align="right" valign="top">volatile int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a></td></tr>
|
||||
<tr class="memdesc:ga12e68e55a7badc271b948d6c7230b2a8"><td class="mdescLeft"> </td><td class="mdescRight">external variable to receive characters <a href="#ga12e68e55a7badc271b948d6c7230b2a8"></a><br/></td></tr>
|
||||
<tr class="separator:ga12e68e55a7badc271b948d6c7230b2a8"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
</table>
|
||||
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
|
||||
<p>CMSIS provides additional debug functions to enlarge the Debug Access. Data can be transmitted via a certain global buffer variable towards the target system.</p>
|
||||
<p>The Cortex-M3 / Cortex-M4 / Cortex-M7 incorporates the <b>Instrumented Trace Macrocell (ITM)</b> that provides together with the <b>Serial Viewer Output (SVO)</b> trace capabilities for the microcontroller system. The ITM has 32 communication channels; two ITM communication channels are used by CMSIS to output the following information:</p>
|
||||
<ul>
|
||||
<li><b>ITM Channel 0</b>: implements the <a class="el" href="group___i_t_m___debug__gr.html#gaaa7c716331f74d644bf6bf25cd3392d1">ITM_SendChar</a> function which can be used for printf-style output via the debug interface.</li>
|
||||
</ul>
|
||||
<ul>
|
||||
<li><b>ITM Channel 31</b>: is reserved for the RTOS kernel and can be used for kernel awareness debugging.</li>
|
||||
</ul>
|
||||
<dl class="section remark"><dt>Remarks</dt><dd><ul>
|
||||
<li>ITM channels have 4 groups with 8 channels each, whereby each group can be configured for access rights in the Unprivileged level.</li>
|
||||
<li>The ITM channel 0 can be enabled for the user task.</li>
|
||||
<li>ITM channel 31 can be accessed only in Privileged mode from the RTOS kernel itself. The ITM channel 31 has been selected for the RTOS kernel because some kernels may use the Privileged level for program execution.</li>
|
||||
</ul>
|
||||
</dd></dl>
|
||||
<hr/>
|
||||
<h1><a class="anchor" id="ITM_debug_uv"></a>
|
||||
ITM Debugger Support</h1>
|
||||
<p>A debugger may support a <b>Debug (printf) Viewer</b> window to display data.</p>
|
||||
<p><b>Direction: Microcontroller –> Debugger:</b></p>
|
||||
<ul>
|
||||
<li>Characters received via ITM communication channel 0 are written in a printf-style to the <b>Debug (printf) Viewer</b> window.</li>
|
||||
</ul>
|
||||
<p><b>Direction: Debugger –> Microcontroller:</b></p>
|
||||
<ul>
|
||||
<li>Check if <a class="el" href="group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a> variable is available (only performed once).</li>
|
||||
<li>Read the character from the <b>Debug (printf) Viewer</b> window.</li>
|
||||
<li>If <a class="el" href="group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a> is empty, write character to <a class="el" href="group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a>.</li>
|
||||
</ul>
|
||||
<dl class="section note"><dt>Note</dt><dd>The current solution does not use a buffer mechanism for transmitting the characters.</dd></dl>
|
||||
<hr/>
|
||||
<h1><a class="anchor" id="itm_debug_ex"></a>
|
||||
Example:</h1>
|
||||
<p>Example for the usage of the ITM Channel 31 for RTOS Kernels:</p>
|
||||
<div class="fragment"><div class="line"><span class="comment">// check if debugger connected and ITM channel enabled for tracing</span></div>
|
||||
<div class="line"><span class="keywordflow">if</span> ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&</div>
|
||||
<div class="line"> (ITM->TCR & ITM_TCR_ITMENA) &&</div>
|
||||
<div class="line"> (ITM->TER & (1UL >> 31))) {</div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"> <span class="comment">// transmit trace data</span></div>
|
||||
<div class="line"> <span class="keywordflow">while</span> (ITM->PORT31_U32 == 0);</div>
|
||||
<div class="line"> ITM->PORT[31].u8 = task_id; <span class="comment">// id of next task</span></div>
|
||||
<div class="line"> <span class="keywordflow">while</span> (ITM->PORT[31].u32 == 0);</div>
|
||||
<div class="line"> ITM->PORT[31].u32 = task_status; <span class="comment">// status information</span></div>
|
||||
<div class="line">}</div>
|
||||
</div><!-- fragment --> <h2 class="groupheader">Function Documentation</h2>
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<a class="anchor" id="ga7f9bbabd9756d1a7eafb2d9bf27e0535"></a>
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<div class="memitem">
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||||
<div class="memproto">
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||||
<table class="memname">
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||||
<tr>
|
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<td class="memname">int32_t ITM_CheckChar </td>
|
||||
<td>(</td>
|
||||
<td class="paramtype">void </td>
|
||||
<td class="paramname"></td><td>)</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><div class="memdoc">
|
||||
<p>This function reads the external variable <a class="el" href="group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a> and checks whether a character is available or not.</p>
|
||||
<dl class="section return"><dt>Returns</dt><dd><ul>
|
||||
<li>=0 - No character available</li>
|
||||
<li>=1 - Character available </li>
|
||||
</ul>
|
||||
</dd></dl>
|
||||
|
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<td class="memname">int32_t ITM_ReceiveChar </td>
|
||||
<td>(</td>
|
||||
<td class="paramtype">void </td>
|
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<td class="paramname"></td><td>)</td>
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<td></td>
|
||||
</tr>
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||||
</table>
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||||
</div><div class="memdoc">
|
||||
<p>This function inputs a character via the external variable <a class="el" href="group___i_t_m___debug__gr.html#ga12e68e55a7badc271b948d6c7230b2a8">ITM_RxBuffer</a>. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.</p>
|
||||
<dl class="section return"><dt>Returns</dt><dd><ul>
|
||||
<li>Received character</li>
|
||||
<li>=1 - No character received </li>
|
||||
</ul>
|
||||
</dd></dl>
|
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|
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<td class="memname">uint32_t ITM_SendChar </td>
|
||||
<td>(</td>
|
||||
<td class="paramtype">uint32_t </td>
|
||||
<td class="paramname"><em>ch</em></td><td>)</td>
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|
||||
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|
||||
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|
||||
</div><div class="memdoc">
|
||||
<p>This function transmits a character via the ITM channel 0. It returns when no debugger is connected that has booked the output. It is blocking when a debugger is connected, but the previously sent character has not been transmitted.</p>
|
||||
<dl class="params"><dt>Parameters</dt><dd>
|
||||
<table class="params">
|
||||
<tr><td class="paramdir">[in]</td><td class="paramname">ch</td><td>Character to transmit</td></tr>
|
||||
</table>
|
||||
</dd>
|
||||
</dl>
|
||||
<dl class="section return"><dt>Returns</dt><dd>Character to transmit </dd></dl>
|
||||
|
||||
</div>
|
||||
</div>
|
||||
<h2 class="groupheader">Variable Documentation</h2>
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<tr>
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<td class="memname">volatile int32_t ITM_RxBuffer</td>
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<tr class="memitem:ga50d373a785edd782c5de5a3b55e30ff3"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3">SCB_InvalidateICache</a> (void)</td></tr>
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<p>The function turns off the instruction cache. </p>
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<p>The function turns on the instruction cache. </p>
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<p>The function invalidates the instruction cache. The instruction cache is never dirty so cache RAM errors are always recoverable by invalidating the cache and retrying the instruction. </p>
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<dl class="section note"><dt>Note</dt><dd>After reset, you must invalidate each cache before enabling (<a class="el" href="group___icache__functions__m7.html#gaf9e7c6c8e16ada1f95e5bf5a03505b68">SCB_EnableICache</a>) it. </dd></dl>
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<tr class="memdesc:gabe47de40e9b0ad465b752297a9d9f427"><td class="mdescLeft"> </td><td class="mdescRight">System Tick Timer Configuration. <a href="#gabe47de40e9b0ad465b752297a9d9f427"></a><br/></td></tr>
|
||||
<tr class="separator:gabe47de40e9b0ad465b752297a9d9f427"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
</table>
|
||||
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
|
||||
<pre class="fragment">The System Tick Time (SysTick) generates interrupt requests on a regular basis.
|
||||
This allows an OS to carry out context switching to support multiple tasking. For applications
|
||||
that do not require an OS, the SysTick can be used for time keeping, time measurement, or as an
|
||||
interrupt source for tasks that need to be executed regularly.
|
||||
</pre><h1><a class="anchor" id="SysTick_code_ex_sec"></a>
|
||||
Code Example</h1>
|
||||
<p>The code below shows the usage of the function <a class="el" href="group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427" title="System Tick Timer Configuration.">SysTick_Config()</a> with an LPC1700.</p>
|
||||
<div class="fragment"><div class="line"><span class="preprocessor">#include "LPC17xx.h"</span></div>
|
||||
<div class="line"></div>
|
||||
<div class="line">uint32_t msTicks = 0; <span class="comment">/* Variable to store millisecond ticks */</span></div>
|
||||
<div class="line"></div>
|
||||
<div class="line"> </div>
|
||||
<div class="line"><span class="keywordtype">void</span> SysTick_Handler(<span class="keywordtype">void</span>) { <span class="comment">/* SysTick interrupt Handler.</span></div>
|
||||
<div class="line"><span class="comment"> msTicks++; See startup file startup_LPC17xx.s for SysTick vector */</span> </div>
|
||||
<div class="line">}</div>
|
||||
<div class="line"></div>
|
||||
<div class="line"></div>
|
||||
<div class="line"><span class="keywordtype">int</span> main (<span class="keywordtype">void</span>) {</div>
|
||||
<div class="line"> uint32_t returnCode;</div>
|
||||
<div class="line"></div>
|
||||
<div class="line"> returnCode = <a class="code" href="group___sys_tick__gr.html#gabe47de40e9b0ad465b752297a9d9f427" title="System Tick Timer Configuration.">SysTick_Config</a>(<a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6" title="Variable to hold the system core clock value.">SystemCoreClock</a> / 1000); <span class="comment">/* Configure SysTick to generate an interrupt every millisecond */</span></div>
|
||||
<div class="line"></div>
|
||||
<div class="line"> <span class="keywordflow">if</span> (returnCode != 0) { <span class="comment">/* Check return code for errors */</span></div>
|
||||
<div class="line"> <span class="comment">// Error Handling </span></div>
|
||||
<div class="line"> }</div>
|
||||
<div class="line"></div>
|
||||
<div class="line"> <span class="keywordflow">while</span>(1);</div>
|
||||
<div class="line">}</div>
|
||||
</div><!-- fragment --> <h2 class="groupheader">Function Documentation</h2>
|
||||
<a class="anchor" id="gabe47de40e9b0ad465b752297a9d9f427"></a>
|
||||
<div class="memitem">
|
||||
<div class="memproto">
|
||||
<table class="memname">
|
||||
<tr>
|
||||
<td class="memname">uint32_t SysTick_Config </td>
|
||||
<td>(</td>
|
||||
<td class="paramtype">uint32_t </td>
|
||||
<td class="paramname"><em>ticks</em></td><td>)</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><div class="memdoc">
|
||||
<p>Initialises and starts the System Tick Timer and its interrupt. After this call, the SysTick timer creates interrupts with the specified time interval. Counter is in free running mode to generate periodical interrupts.</p>
|
||||
<dl class="params"><dt>Parameters</dt><dd>
|
||||
<table class="params">
|
||||
<tr><td class="paramdir">[in]</td><td class="paramname">ticks</td><td>Number of ticks between two interrupts</td></tr>
|
||||
</table>
|
||||
</dd>
|
||||
</dl>
|
||||
<dl class="section return"><dt>Returns</dt><dd>0 - success </dd>
|
||||
<dd>
|
||||
1 - failure</dd></dl>
|
||||
<dl class="section note"><dt>Note</dt><dd>When <b>#define __Vendor_SysTickConfig</b> is set to 1, the standard function <b>SysTick_Config</b> is excluded. In this case, the file <b><em>device</em>.h</b> must contain a vendor specific implementation of this function. </dd></dl>
|
||||
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||||
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|
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 <span id="projectnumber">Version 4.30</span>
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<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
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|
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<div class="contents">
|
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|
||||
<p>Functions for Instruction and Data Cache.
|
||||
<a href="#details">More...</a></p>
|
||||
<table class="memberdecls">
|
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="groups"></a>
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Content</h2></td></tr>
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<tr class="memitem:group___icache__functions__m7"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___icache__functions__m7.html">I-Cache Functions</a></td></tr>
|
||||
<tr class="memdesc:group___icache__functions__m7"><td class="mdescLeft"> </td><td class="mdescRight">Functions for the instruction cache. <br/></td></tr>
|
||||
<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
<tr class="memitem:group___dcache__functions__m7"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___dcache__functions__m7.html">D-Cache Functions</a></td></tr>
|
||||
<tr class="memdesc:group___dcache__functions__m7"><td class="mdescLeft"> </td><td class="mdescRight">Functions for the data cache. <br/></td></tr>
|
||||
<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
</table>
|
||||
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
|
||||
<p>Cortex-M7 processors include a memory system, which includes an optional MPU and Harvard data and instruction cache with ECC. The optional CPU cache has an instruction and data cache with sizes of <span class="XML-Token">[0;4;8;16;32;64]KB</span>. Both instruction and data cache RAM can be configured at implementation time to have Error Correcting Code (ECC) to protect the data stored in the memory from errors.</p>
|
||||
<p>All cache maintenance operations are executed by writing to registers in the memory mapped System Control Space (SCS) region of the internal PPB memory space.</p>
|
||||
<dl class="section note"><dt>Note</dt><dd>After reset, you must invalidate each cache before enabling it.</dd></dl>
|
||||
<p>The functions are grouped for:</p>
|
||||
<ul>
|
||||
<li><a class="el" href="group___icache__functions__m7.html">I-Cache Functions</a></li>
|
||||
<li><a class="el" href="group___dcache__functions__m7.html">D-Cache Functions</a> </li>
|
||||
</ul>
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<!-- start footer part -->
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Functions</h2></td></tr>
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<tr class="memitem:ga6bcad99ce80a0e7e4ddc6f2379081756"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__fpu__functions__m7.html#ga6bcad99ce80a0e7e4ddc6f2379081756">SCB_GetFPUType</a> (void)</td></tr>
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<p>The Cortex-M7 processor includes optional floating-point arithmetic functionality, with support for single and double-precision arithmetic. The Cortex-M7 processor with FPU is an implementation of the single-precision and double-precision variant of the ARMv7-M Architecture with Floating-Point Extension (FPv5). </p>
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<div id="projectname">CMSIS-CORE
|
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 <span id="projectnumber">Version 4.30</span>
|
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|
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<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
|
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<a href="#define-members">Macros</a> </div>
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<div class="headertitle">
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<div class="title">Peripheral Access</div> </div>
|
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</div><!--header-->
|
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<div class="contents">
|
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|
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<p>Describes naming conventions, requirements, and optional features for accessing peripherals.
|
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<a href="#details">More...</a></p>
|
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<table class="memberdecls">
|
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
|
||||
<tr class="memitem:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a>(field, value)</td></tr>
|
||||
<tr class="memdesc:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="mdescLeft"> </td><td class="mdescRight">Mask and shift a bit field value for assigning to result to a peripheral register. <a href="#ga286e3b913dbd236c7f48ea70c8821f4e"></a><br/></td></tr>
|
||||
<tr class="separator:ga286e3b913dbd236c7f48ea70c8821f4e"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
<tr class="memitem:ga139b6e261c981f014f386927ca4a8444"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a>(field, value)</td></tr>
|
||||
<tr class="memdesc:ga139b6e261c981f014f386927ca4a8444"><td class="mdescLeft"> </td><td class="mdescRight">Extract from a peripheral register value the a bit field value. <a href="#ga139b6e261c981f014f386927ca4a8444"></a><br/></td></tr>
|
||||
<tr class="separator:ga139b6e261c981f014f386927ca4a8444"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
</table>
|
||||
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
|
||||
<p>The section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals. Most of the rules also apply to the core peripherals. The <a class="el" href="device_h_pg.html">Device Header File <device.h></a> contains typically these definition and also includes the core specific header files.</p>
|
||||
<p>Most of the definitions can be generated using the <a href="../../SVD/html/index.html"><b>CMSIS-SVD</b></a> System View Description for Peripherals. Refer to <a href="../../SVD/html/svd__s_v_d_conv_pg.html"><b>SVDConv.exe</b></a> for more information.</p>
|
||||
<p>Each peripheral provides a data type definition with a name that is composed of:</p>
|
||||
<ul>
|
||||
<li>prefix <b><<em>device abbreviation></em>_</b></li>
|
||||
<li><b><<em>peripheral name</em>></b></li>
|
||||
<li>postfix <b>_Type</b> or <b>_TypeDef</b> to identify a type definition.</li>
|
||||
</ul>
|
||||
<p>Example: <b>LPC_UART_TypeDef</b> for the device <b>LPC</b> and the peripheral <b>UART</b>.</p>
|
||||
<p>The data type definition uses standard C data types defined by the ANSI C header file <stdint.h>.</p>
|
||||
<ul>
|
||||
<li>IO Type Qualifiers are used to specify the access to peripheral variables. <table class="doxtable">
|
||||
<tr>
|
||||
<th align="left">IO Type Qualifier </th><th align="left">Type </th><th align="left">Description</th></tr>
|
||||
<tr>
|
||||
<td align="left"><b>__IM</b> </td><td align="left">Struct member </td><td align="left">Defines 'read only' permissions </td></tr>
|
||||
<tr>
|
||||
<td align="left"><b>__OM</b> </td><td align="left">Struct member </td><td align="left">Defines 'write only' permissions </td></tr>
|
||||
<tr>
|
||||
<td align="left"><b>__IOM</b> </td><td align="left">Struct member </td><td align="left">Defines 'read / write' permissions </td></tr>
|
||||
<tr>
|
||||
<td align="left"><b>__I</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'read only' permissions </td></tr>
|
||||
<tr>
|
||||
<td align="left"><b>__O</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'write only' permissions </td></tr>
|
||||
<tr>
|
||||
<td align="left"><b>__IO</b> </td><td align="left">Scalar variable </td><td align="left">Defines 'read / write' permissions </td></tr>
|
||||
</table>
|
||||
</li>
|
||||
</ul>
|
||||
<dl class="section note"><dt>Note</dt><dd><b>__IM</b>, <b>__OM</b>, <b>__IOM</b> are added in CMSIS-Core V4.20 to enhance support for C++. Prior version used <b>__I</b>, <b>__O</b>, <b>__IO</b> also for struct member definitions.</dd></dl>
|
||||
<p>The typedef <b><<em>device abbreviation</em>>_UART_TypeDef</b> shown below defines the generic register layout for all UART channels in a device.</p>
|
||||
<div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||||
<div class="line">{</div>
|
||||
<div class="line"> <span class="keyword">union </span>{</div>
|
||||
<div class="line"> __IM uint8_t RBR; <span class="comment">/* Offset: 0x000 (R/ ) Receiver Buffer Register */</span></div>
|
||||
<div class="line"> __OM uint8_t THR; <span class="comment">/* Offset: 0x000 ( /W) Transmit Holding Register */</span></div>
|
||||
<div class="line"> __IOM uint8_t DLL; <span class="comment">/* Offset: 0x000 (R/W) Divisor Latch LSB */</span></div>
|
||||
<div class="line"> uint32_t RESERVED0;</div>
|
||||
<div class="line"> };</div>
|
||||
<div class="line"> <span class="keyword">union </span>{</div>
|
||||
<div class="line"> __IOM uint8_t DLM; <span class="comment">/* Offset: 0x004 (R/W) Divisor Latch MSB */</span></div>
|
||||
<div class="line"> __IOM uint32_t IER; <span class="comment">/* Offset: 0x004 (R/W) Interrupt Enable Register */</span></div>
|
||||
<div class="line"> };</div>
|
||||
<div class="line"> <span class="keyword">union </span>{</div>
|
||||
<div class="line"> __IM uint32_t IIR; <span class="comment">/* Offset: 0x008 (R/ ) Interrupt ID Register */</span></div>
|
||||
<div class="line"> __OM uint8_t FCR; <span class="comment">/* Offset: 0x008 ( /W) FIFO Control Register */</span></div>
|
||||
<div class="line"> };</div>
|
||||
<div class="line"> __IOM uint8_t LCR; <span class="comment">/* Offset: 0x00C (R/W) Line Control Register */</span></div>
|
||||
<div class="line"> uint8_t RESERVED1[7];</div>
|
||||
<div class="line"> __IM uint8_t LSR; <span class="comment">/* Offset: 0x014 (R/ ) Line Status Register */</span></div>
|
||||
<div class="line"> uint8_t RESERVED2[7];</div>
|
||||
<div class="line"> __IOM uint8_t SCR; <span class="comment">/* Offset: 0x01C (R/W) Scratch Pad Register */</span></div>
|
||||
<div class="line"> uint8_t RESERVED3[3];</div>
|
||||
<div class="line"> __IOM uint32_t ACR; <span class="comment">/* Offset: 0x020 (R/W) Autobaud Control Register */</span></div>
|
||||
<div class="line"> __IOM uint8_t ICR; <span class="comment">/* Offset: 0x024 (R/W) IrDA Control Register */</span></div>
|
||||
<div class="line"> uint8_t RESERVED4[3];</div>
|
||||
<div class="line"> __IOM uint8_t FDR; <span class="comment">/* Offset: 0x028 (R/W) Fractional Divider Register */</span></div>
|
||||
<div class="line"> uint8_t RESERVED5[7];</div>
|
||||
<div class="line"> __IOM uint8_t TER; <span class="comment">/* Offset: 0x030 (R/W) Transmit Enable Register */</span></div>
|
||||
<div class="line"> uint8_t RESERVED6[39];</div>
|
||||
<div class="line"> __IM uint8_t FIFOLVL; <span class="comment">/* Offset: 0x058 (R/ ) FIFO Level Register */</span></div>
|
||||
<div class="line">} LPC_UART_TypeDef;</div>
|
||||
</div><!-- fragment --><p>To access the registers of the UART defined above, pointers to this register structure are defined. If more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.</p>
|
||||
<p><b>Example:</b> In this example <b>LPC_UART2</b> and <b>LPC_UART3</b> are two pointers to UARTs defined with above register structure. <br/>
|
||||
</p>
|
||||
<div class="fragment"><div class="line"><span class="preprocessor">#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )</span></div>
|
||||
<div class="line"><span class="preprocessor">#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )</span></div>
|
||||
</div><!-- fragment --><p>The registers in the various UARTs can now be referred in the user code as shown below:<br/>
|
||||
</p>
|
||||
<div class="fragment"><div class="line">val = LPC_UART2->DR <span class="comment">// is the data register of UART1.</span></div>
|
||||
</div><!-- fragment --><hr/>
|
||||
<h1><a class="anchor" id="core_cmsis_pal_min_reqs"></a>
|
||||
Minimal Requirements</h1>
|
||||
<p>To access the peripheral registers and related function in a device, the files <b><em>device.h</em></b> and <b>core_cm<em>#</em>.h</b> define as a minimum: <br/>
|
||||
<br/>
|
||||
</p>
|
||||
<ul>
|
||||
<li>The <b>Register Layout Typedef</b> for each peripheral that defines all register names. RESERVED is used to introduce space into the structure for adjusting the addresses of the peripheral registers. <br/>
|
||||
<br/>
|
||||
<b>Example:</b> <div class="fragment"><div class="line"><span class="keyword">typedef</span> <span class="keyword">struct</span></div>
|
||||
<div class="line">{</div>
|
||||
<div class="line"> __IOM uint32_t CTRL; <span class="comment">/* Offset: 0x000 (R/W) SysTick Control and Status Register */</span></div>
|
||||
<div class="line"> __IOM uint32_t LOAD; <span class="comment">/* Offset: 0x004 (R/W) SysTick Reload Value Register */</span></div>
|
||||
<div class="line"> __IOM uint32_t VAL; <span class="comment">/* Offset: 0x008 (R/W) SysTick Current Value Register */</span></div>
|
||||
<div class="line"> __IM uint32_t CALIB; <span class="comment">/* Offset: 0x00C (R/ ) SysTick Calibration Register */</span></div>
|
||||
<div class="line">} <a class="code" href="struct_sys_tick___type.html" title="Structure type to access the System Timer (SysTick).">SysTick_Type</a>;</div>
|
||||
</div><!-- fragment --></li>
|
||||
</ul>
|
||||
<ul>
|
||||
<li><b>Base Address</b> for each peripheral (in case of multiple peripherals that use the same <b>register layout typedef</b> multiple base addresses are defined). <br/>
|
||||
<br/>
|
||||
<b>Example:</b> <div class="fragment"><div class="line"><span class="preprocessor">#define SysTick_BASE (SCS_BASE + 0x0010) </span><span class="comment">/* SysTick Base Address */</span><span class="preprocessor"></span></div>
|
||||
</div><!-- fragment --></li>
|
||||
</ul>
|
||||
<ul>
|
||||
<li><b>Access Definitions</b> for each peripheral. In case of multiple peripherals that are using the same <b>register layout typdef</b>, multiple access definitions exist (LPC_UART0, LPC_UART2). <br/>
|
||||
<br/>
|
||||
<b>Example:</b> <div class="fragment"><div class="line"><span class="preprocessor">#define SysTick ((SysTick_Type *) Systick_BASE) </span><span class="comment">/* SysTick access definition */</span><span class="preprocessor"></span></div>
|
||||
</div><!-- fragment --></li>
|
||||
</ul>
|
||||
<p>These definitions allow accessing peripheral registers with simple assignments.</p>
|
||||
<ul>
|
||||
<li><b>Example:</b> <br/>
|
||||
<div class="fragment"><div class="line">SysTick->CTRL = 0;</div>
|
||||
</div><!-- fragment --></li>
|
||||
</ul>
|
||||
<hr/>
|
||||
<h1><a class="anchor" id="core_cmsis_pal_opts"></a>
|
||||
Optional Features</h1>
|
||||
<p>Optionally, the file <b><em>device</em>.h</b> may define:</p>
|
||||
<ul>
|
||||
<li><a class="el" href="group__peripheral__gr.html#core_cmsis_pal_bitfields">Register Bit Fields</a> and #define constants that simplify access to peripheral registers. These constants may define bit-positions or other specific patterns that are required for programming peripheral registers. The identifiers should start with <b><<em>device abbreviation</em>>_</b> and <b><<em>peripheral name</em>>_</b>. It is recommended to use CAPITAL letters for #define constants.</li>
|
||||
</ul>
|
||||
<ul>
|
||||
<li>More complex functions (i.e. status query before a sending register is accessed). Again, these functions start with <b><<em>device abbreviation</em>>_</b> and <b><<em>peripheral name</em>>_</b>.</li>
|
||||
</ul>
|
||||
<hr/>
|
||||
<h1><a class="anchor" id="core_cmsis_pal_bitfields"></a>
|
||||
Register Bit Fields</h1>
|
||||
<p>For Core Register, macros define the position and the mask value for a bit field. It is recommended to create such definitions also for other peripheral registers.</p>
|
||||
<p><b>Example:</b></p>
|
||||
<p>Bit field definitions for register CPUID in SCB (System Control Block).</p>
|
||||
<div class="fragment"><div class="line"><span class="comment">/* SCB CPUID Register Definitions */</span></div>
|
||||
<div class="line"><span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Pos 24U </span></div>
|
||||
<div class="line"><span class="preprocessor">#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) </span></div>
|
||||
<div class="line"><span class="preprocessor">#define SCB_CPUID_VARIANT_Pos 20U </span></div>
|
||||
<div class="line"><span class="preprocessor">#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) </span></div>
|
||||
<div class="line"><span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Pos 16U </span></div>
|
||||
<div class="line"><span class="preprocessor">#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) </span></div>
|
||||
<div class="line"><span class="preprocessor">#define SCB_CPUID_PARTNO_Pos 4U </span></div>
|
||||
<div class="line"><span class="preprocessor">#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) </span></div>
|
||||
<div class="line"><span class="preprocessor">#define SCB_CPUID_REVISION_Pos 0U </span></div>
|
||||
<div class="line"><span class="preprocessor">#define SCB_CPUID_REVISION_Msk (0xFUL </span><span class="comment">/*<< SCB_CPUID_REVISION_Pos*/</span><span class="preprocessor">) </span></div>
|
||||
</div><!-- fragment --><p>The macros <b><a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e" title="Mask and shift a bit field value for assigning to result to a peripheral register.">_VAL2FLD(field, value)</a></b> and <b><a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444" title="Extract from a peripheral register value the a bit field value.">_FLD2VAL(field, value)</a></b> enable access to bit fields. </p>
|
||||
<h2 class="groupheader">Macro Definition Documentation</h2>
|
||||
<a class="anchor" id="ga139b6e261c981f014f386927ca4a8444"></a>
|
||||
<div class="memitem">
|
||||
<div class="memproto">
|
||||
<table class="memname">
|
||||
<tr>
|
||||
<td class="memname">#define _FLD2VAL</td>
|
||||
<td>(</td>
|
||||
<td class="paramtype"> </td>
|
||||
<td class="paramname">field, </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="paramkey"></td>
|
||||
<td></td>
|
||||
<td class="paramtype"> </td>
|
||||
<td class="paramname">value </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td></td>
|
||||
<td>)</td>
|
||||
<td></td><td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><div class="memdoc">
|
||||
<dl class="params"><dt>Parameters</dt><dd>
|
||||
<table class="params">
|
||||
<tr><td class="paramname">field</td><td>name of bit field. </td></tr>
|
||||
<tr><td class="paramname">value</td><td>value of the register</td></tr>
|
||||
</table>
|
||||
</dd>
|
||||
</dl>
|
||||
<p>The macro <a class="el" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444">_FLD2VAL</a> uses the #define's <em>_Pos</em> and <em>_Msk</em> of the related bit field to extract the value of a bit field from a register.</p>
|
||||
<p><b>Example:</b> </p>
|
||||
<div class="fragment"><div class="line"><span class="keywordtype">id</span> = = <a class="code" href="group__peripheral__gr.html#ga139b6e261c981f014f386927ca4a8444" title="Extract from a peripheral register value the a bit field value.">_FLD2VAL</a>(SCB_CPUID_REVISION, SCB->CPUID);</div>
|
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||||
<table class="memname">
|
||||
<tr>
|
||||
<td class="memname">#define _VAL2FLD</td>
|
||||
<td>(</td>
|
||||
<td class="paramtype"> </td>
|
||||
<td class="paramname">field, </td>
|
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|
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<tr>
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<td class="paramkey"></td>
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<dl class="params"><dt>Parameters</dt><dd>
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<table class="params">
|
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<tr><td class="paramname">field</td><td>name of bit field. </td></tr>
|
||||
<tr><td class="paramname">value</td><td>value for the bit field.</td></tr>
|
||||
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|
||||
</dd>
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|
||||
<p>The macro <a class="el" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e">_VAL2FLD</a> uses the #define's <em>_Pos</em> and <em>_Msk</em> of the related bit field to shift bit-field values for assigning to a register.</p>
|
||||
<p><b>Example:</b> </p>
|
||||
<div class="fragment"><div class="line">SCB->CPUID = <a class="code" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e" title="Mask and shift a bit field value for assigning to result to a peripheral register.">_VAL2FLD</a>(SCB_CPUID_REVISION, 0x3) | <a class="code" href="group__peripheral__gr.html#ga286e3b913dbd236c7f48ea70c8821f4e" title="Mask and shift a bit field value for assigning to result to a peripheral register.">_VAL2FLD</a>(SCB_CPUID_VARIANT, 0x3);</div>
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<div id="projectname">CMSIS-CORE
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 <span id="projectnumber">Version 4.30</span>
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<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
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<a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(0)"><span class="SelectionMark"> </span>All</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(1)"><span class="SelectionMark"> </span>Data Structures</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(2)"><span class="SelectionMark"> </span>Files</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(3)"><span class="SelectionMark"> </span>Functions</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(4)"><span class="SelectionMark"> </span>Variables</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(5)"><span class="SelectionMark"> </span>Enumerations</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(6)"><span class="SelectionMark"> </span>Enumerator</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(7)"><span class="SelectionMark"> </span>Groups</a><a class="SelectItem" href="javascript:void(0)" onclick="searchBox.OnSelectItem(8)"><span class="SelectionMark"> </span>Pages</a></div>
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<a href="#func-members">Functions</a> |
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<a href="#var-members">Variables</a> </div>
|
||||
<div class="headertitle">
|
||||
<div class="title">System and Clock Configuration</div> </div>
|
||||
</div><!--header-->
|
||||
<div class="contents">
|
||||
|
||||
<p>Describes system_<em>device</em>.c file that contains functions for system and clock setup.
|
||||
<a href="#details">More...</a></p>
|
||||
<table class="memberdecls">
|
||||
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
|
||||
Functions</h2></td></tr>
|
||||
<tr class="memitem:ga93f514700ccf00d08dbdcff7f1224eb2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit</a> (void)</td></tr>
|
||||
<tr class="memdesc:ga93f514700ccf00d08dbdcff7f1224eb2"><td class="mdescLeft"> </td><td class="mdescRight">Function to Initialize the system. <a href="#ga93f514700ccf00d08dbdcff7f1224eb2"></a><br/></td></tr>
|
||||
<tr class="separator:ga93f514700ccf00d08dbdcff7f1224eb2"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
<tr class="memitem:gae0c36a9591fe6e9c45ecb21a794f0f0f"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f">SystemCoreClockUpdate</a> (void)</td></tr>
|
||||
<tr class="memdesc:gae0c36a9591fe6e9c45ecb21a794f0f0f"><td class="mdescLeft"> </td><td class="mdescRight">Function to update the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>. <a href="#gae0c36a9591fe6e9c45ecb21a794f0f0f"></a><br/></td></tr>
|
||||
<tr class="separator:gae0c36a9591fe6e9c45ecb21a794f0f0f"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
</table><table class="memberdecls">
|
||||
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="var-members"></a>
|
||||
Variables</h2></td></tr>
|
||||
<tr class="memitem:gaa3cd3e43291e81e795d642b79b6088e6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a></td></tr>
|
||||
<tr class="memdesc:gaa3cd3e43291e81e795d642b79b6088e6"><td class="mdescLeft"> </td><td class="mdescRight">Variable to hold the system core clock value. <a href="#gaa3cd3e43291e81e795d642b79b6088e6"></a><br/></td></tr>
|
||||
<tr class="separator:gaa3cd3e43291e81e795d642b79b6088e6"><td class="memSeparator" colspan="2"> </td></tr>
|
||||
</table>
|
||||
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
|
||||
<p>ARM provides a template file <b>system_<em>device</em>.c</b> that must be adapted by the silicon vendor to match their actual device. As a <b>minimum requirement</b>, this file must provide:</p>
|
||||
<ul>
|
||||
<li>A device-specific system configuration function, <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2">SystemInit()</a>.</li>
|
||||
<li>A global variable that contains the system frequency, <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>.</li>
|
||||
</ul>
|
||||
<p>The file configures the device and, typically, initializes the oscillator (PLL) that is part of the microcontroller device. This file might export other functions or variables that provide a more flexible configuration of the microcontroller system.</p>
|
||||
<h1><a class="anchor" id="system_init_code_ex_sec"></a>
|
||||
Code Example</h1>
|
||||
<p>The code below shows the usage of the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> and the functions <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system.">SystemInit()</a> and <a class="el" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f" title="Function to update the variable SystemCoreClock.">SystemCoreClockUpdate()</a> with an LPC1700.</p>
|
||||
<div class="fragment"><div class="line"><span class="preprocessor">#include "LPC17xx.h"</span></div>
|
||||
<div class="line"></div>
|
||||
<div class="line">uint32_t coreClock_1 = 0; <span class="comment">/* Variables to store core clock values */</span></div>
|
||||
<div class="line">uint32_t coreClock_2 = 0;</div>
|
||||
<div class="line"></div>
|
||||
<div class="line"></div>
|
||||
<div class="line"><span class="keywordtype">int</span> main (<span class="keywordtype">void</span>) {</div>
|
||||
<div class="line"></div>
|
||||
<div class="line"> coreClock_1 = <a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6" title="Variable to hold the system core clock value.">SystemCoreClock</a>; <span class="comment">/* Store value of predefined SystemCoreClock */</span></div>
|
||||
<div class="line"></div>
|
||||
<div class="line"> <a class="code" href="group__system__init__gr.html#gae0c36a9591fe6e9c45ecb21a794f0f0f" title="Function to update the variable SystemCoreClock.">SystemCoreClockUpdate</a>(); <span class="comment">/* Update SystemCoreClock according to register settings */</span></div>
|
||||
<div class="line"></div>
|
||||
<div class="line"> coreClock_2 = <a class="code" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6" title="Variable to hold the system core clock value.">SystemCoreClock</a>; <span class="comment">/* Store value of calculated SystemCoreClock */</span></div>
|
||||
<div class="line"></div>
|
||||
<div class="line"> <span class="keywordflow">if</span> (coreClock_2 != coreClock_1) { <span class="comment">/* Without changing the clock setting both core clock values should be the same */</span> </div>
|
||||
<div class="line"> <span class="comment">// Error Handling</span></div>
|
||||
<div class="line"> }</div>
|
||||
<div class="line"></div>
|
||||
<div class="line"> <span class="keywordflow">while</span>(1);</div>
|
||||
<div class="line">}</div>
|
||||
</div><!-- fragment --> <h2 class="groupheader">Function Documentation</h2>
|
||||
<a class="anchor" id="gae0c36a9591fe6e9c45ecb21a794f0f0f"></a>
|
||||
<div class="memitem">
|
||||
<div class="memproto">
|
||||
<table class="memname">
|
||||
<tr>
|
||||
<td class="memname">void SystemCoreClockUpdate </td>
|
||||
<td>(</td>
|
||||
<td class="paramtype">void </td>
|
||||
<td class="paramname"></td><td>)</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><div class="memdoc">
|
||||
<p>Updates the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a> and must be called whenever the core clock is changed during program execution. The function evaluates the clock register settings and calculates the current core clock. </p>
|
||||
|
||||
</div>
|
||||
</div>
|
||||
<a class="anchor" id="ga93f514700ccf00d08dbdcff7f1224eb2"></a>
|
||||
<div class="memitem">
|
||||
<div class="memproto">
|
||||
<table class="memname">
|
||||
<tr>
|
||||
<td class="memname">void SystemInit </td>
|
||||
<td>(</td>
|
||||
<td class="paramtype">void </td>
|
||||
<td class="paramname"></td><td>)</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><div class="memdoc">
|
||||
<p>Initializes the microcontroller system. Typically, this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with a variable clock speed, it updates the variable <a class="el" href="group__system__init__gr.html#gaa3cd3e43291e81e795d642b79b6088e6">SystemCoreClock</a>. SystemInit is called from the file <b>startup<em>_device</em></b>. </p>
|
||||
|
||||
</div>
|
||||
</div>
|
||||
<h2 class="groupheader">Variable Documentation</h2>
|
||||
<a class="anchor" id="gaa3cd3e43291e81e795d642b79b6088e6"></a>
|
||||
<div class="memitem">
|
||||
<div class="memproto">
|
||||
<table class="memname">
|
||||
<tr>
|
||||
<td class="memname">uint32_t SystemCoreClock</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><div class="memdoc">
|
||||
<p>Holds the system core clock, which is the system clock frequency supplied to the SysTick timer and the processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure the trace clock speed.</p>
|
||||
<dl class="section attention"><dt>Attention</dt><dd>Compilers must be configured to avoid removing this variable in case the application program is not using it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure the debugger. </dd></dl>
|
||||
|
||||
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|
||||
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|
||||
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||||
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<!-- start footer part -->
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<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
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<li class="footer">Generated on Tue Oct 27 2015 14:35:21 for CMSIS-CORE by ARM Ltd. All rights reserved.
|
||||
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+6
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|
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 <span id="projectnumber">Version 4.30</span>
|
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|
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<div id="projectbrief">CMSIS-CORE support for Cortex-M processor-based devices</div>
|
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|
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|
||||
</div><!--header-->
|
||||
<div class="contents">
|
||||
<div class="textblock"><p>CMSIS-CORE implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:</p>
|
||||
<ul>
|
||||
<li><b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.</li>
|
||||
<li><b>System exception names</b> to interface to system exceptions without having compatibility issues.</li>
|
||||
<li><b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.</li>
|
||||
<li><b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized <a class="el" href="group__system__init__gr.html#ga93f514700ccf00d08dbdcff7f1224eb2" title="Function to Initialize the system.">SystemInit()</a> function is essential for configuring the clock system of the device.</li>
|
||||
<li><b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.</li>
|
||||
<li>A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.</li>
|
||||
</ul>
|
||||
<p>The following sections provide details about the CMSIS-CORE:</p>
|
||||
<ul>
|
||||
<li><a class="el" href="_using_pg.html">Using CMSIS in Embedded Applications</a> describes the project setup and shows a simple program example.</li>
|
||||
<li><a class="el" href="_templates_pg.html">Template Files</a> describes the files of the CMSIS-CORE in detail and explains how to adapt template files provided by ARM to silicon vendor devices.</li>
|
||||
<li><a class="el" href="_c_o_r_e__m_i_s_r_a__exceptions_pg.html">MISRA-C:2004 Compliance Exceptions</a> describes the violations to the MISRA standard.</li>
|
||||
<li><a href="Modules.html"><b>Reference</b> </a> describe the features and functions of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</li>
|
||||
<li><a href="Annotated.html"><b>Data</b> <b>Structures</b> </a> describe the data structures of the <a class="el" href="device_h_pg.html">Device Header File <device.h></a> in detail.</li>
|
||||
</ul>
|
||||
<hr/>
|
||||
<h2>CMSIS-CORE in ARM::CMSIS Pack</h2>
|
||||
<p>Files relevant to CMSIS-CORE are present in the following <b>ARM::CMSIS</b> directories: </p>
|
||||
<table class="doxtable">
|
||||
<tr>
|
||||
<th>File/Folder </th><th>Content </th></tr>
|
||||
<tr>
|
||||
<td><b>CMSIS\Documentation\Core</b> </td><td>This documentation </td></tr>
|
||||
<tr>
|
||||
<td><b>CMSIS\Include</b> </td><td>CMSIS-CORE header files (for example core_cm3.h, core_cmInstr.h, etc.) </td></tr>
|
||||
<tr>
|
||||
<td><b>Device</b> </td><td><a class="el" href="_using__a_r_m_pg.html">ARM reference implementations</a> of Cortex-M devices </td></tr>
|
||||
<tr>
|
||||
<td><b>Device\_Template_Vendor</b> </td><td><a class="el" href="_templates_pg.html">Template Files</a> for extension by silicon vendors </td></tr>
|
||||
</table>
|
||||
<hr/>
|
||||
<h1><a class="anchor" id="ref_man_sec"></a>
|
||||
Cortex-M Reference Manuals</h1>
|
||||
<p>The Cortex-M Reference Manuals are generic user guides for devices that implement the various ARM Cortex-M processors. These manuals contain the programmers model and detailed information about the core peripherals.</p>
|
||||
<ul>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0_generic_ug.pdf" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a></li>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0662b/DUI0662B_cortex_m0p_r0p1_dgug.pdf" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a></li>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0552a/DUI0552A_cortex_m3_dgug.pdf" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a></li>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a></li>
|
||||
<li><a href="http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/DUI0646A_cortex_m7_dgug.pdf" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a></li>
|
||||
</ul>
|
||||
<hr/>
|
||||
<h1><a class="anchor" id="tested_tools_sec"></a>
|
||||
Tested and Verified Toolchains</h1>
|
||||
<p>The CMSIS-CORE <a class="el" href="_templates_pg.html">Template Files</a> supplied by ARM have been tested and verified with the following toolchains:</p>
|
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<ul>
|
||||
<li>ARM: MDK-ARM Version 5.16</li>
|
||||
<li>GNU: GNU Tools ARM Embedded 4.9 2015.q2</li>
|
||||
<li>IAR: IAR Embedded Workbench Kickstart Edition V6.10</li>
|
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</ul>
|
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|
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<tr id="row_0_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__peripheral__gr.html" target="_self">Peripheral Access</a></td><td class="desc">Describes naming conventions, requirements, and optional features for accessing peripherals</td></tr>
|
||||
<tr id="row_1_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group__system__init__gr.html" target="_self">System and Clock Configuration</a></td><td class="desc">Describes system_<em>device</em>.c file that contains functions for system and clock setup</td></tr>
|
||||
<tr id="row_2_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group___n_v_i_c__gr.html" target="_self">Interrupts and Exceptions (NVIC)</a></td><td class="desc">Explains how to use interrupts and exceptions and access functions for the Nested Vector Interrupt Controller (NVIC)</td></tr>
|
||||
<tr id="row_3_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group___core___register__gr.html" target="_self">Core Register Access</a></td><td class="desc">Functions to access the Cortex-M core registers</td></tr>
|
||||
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||||
if (typeof(node.childrenData)==='string') {
|
||||
var varName = node.childrenData;
|
||||
getScript(node.relpath+varName,function(){
|
||||
node.childrenData = getData(varName);
|
||||
expandNode(o, node, imm, showRoot);
|
||||
}, showRoot);
|
||||
} else {
|
||||
if (!node.childrenVisited) {
|
||||
getNode(o, node);
|
||||
} if (imm || ($.browser.msie && $.browser.version>8)) {
|
||||
// somehow slideDown jumps to the start of tree for IE9 :-(
|
||||
$(node.getChildrenUL()).show();
|
||||
} else {
|
||||
$(node.getChildrenUL()).slideDown("fast");
|
||||
}
|
||||
if (node.isLast) {
|
||||
node.plus_img.src = node.relpath+"ftv2mlastnode.png";
|
||||
} else {
|
||||
node.plus_img.src = node.relpath+"ftv2mnode.png";
|
||||
}
|
||||
node.expanded = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
function glowEffect(n,duration)
|
||||
{
|
||||
n.addClass('glow').delay(duration).queue(function(next){
|
||||
$(this).removeClass('glow');next();
|
||||
});
|
||||
}
|
||||
|
||||
function highlightAnchor()
|
||||
{
|
||||
var anchor = $($(location).attr('hash'));
|
||||
if (anchor.parent().attr('class')=='memItemLeft'){
|
||||
var rows = $('.memberdecls tr[class$="'+
|
||||
window.location.hash.substring(1)+'"]');
|
||||
glowEffect(rows.children(),300); // member without details
|
||||
} else if (anchor.parents().slice(2).prop('tagName')=='TR') {
|
||||
glowEffect(anchor.parents('div.memitem'),1000); // enum value
|
||||
} else if (anchor.parent().attr('class')=='fieldtype'){
|
||||
glowEffect(anchor.parent().parent(),1000); // struct field
|
||||
} else if (anchor.parent().is(":header")) {
|
||||
glowEffect(anchor.parent(),1000); // section header
|
||||
} else {
|
||||
glowEffect(anchor.next(),1000); // normal member
|
||||
}
|
||||
}
|
||||
|
||||
function selectAndHighlight(hash,n)
|
||||
{
|
||||
var a;
|
||||
if (hash) {
|
||||
var link=stripPath($(location).attr('pathname'))+':'+hash.substring(1);
|
||||
a=$('.item a[class$="'+link+'"]');
|
||||
}
|
||||
if (a && a.length) {
|
||||
a.parent().parent().addClass('selected');
|
||||
a.parent().parent().attr('id','selected');
|
||||
highlightAnchor();
|
||||
} else if (n) {
|
||||
$(n.itemDiv).addClass('selected');
|
||||
$(n.itemDiv).attr('id','selected');
|
||||
}
|
||||
showRoot();
|
||||
}
|
||||
|
||||
function showNode(o, node, index, hash)
|
||||
{
|
||||
if (node && node.childrenData) {
|
||||
if (typeof(node.childrenData)==='string') {
|
||||
var varName = node.childrenData;
|
||||
getScript(node.relpath+varName,function(){
|
||||
node.childrenData = getData(varName);
|
||||
showNode(o,node,index,hash);
|
||||
},true);
|
||||
} else {
|
||||
if (!node.childrenVisited) {
|
||||
getNode(o, node);
|
||||
}
|
||||
$(node.getChildrenUL()).show();
|
||||
if (node.isLast) {
|
||||
node.plus_img.src = node.relpath+"ftv2mlastnode.png";
|
||||
} else {
|
||||
node.plus_img.src = node.relpath+"ftv2mnode.png";
|
||||
}
|
||||
node.expanded = true;
|
||||
var n = node.children[o.breadcrumbs[index]];
|
||||
if (index+1<o.breadcrumbs.length) {
|
||||
showNode(o,n,index+1,hash);
|
||||
} else {
|
||||
if (typeof(n.childrenData)==='string') {
|
||||
var varName = n.childrenData;
|
||||
getScript(n.relpath+varName,function(){
|
||||
n.childrenData = getData(varName);
|
||||
node.expanded=false;
|
||||
showNode(o,node,index,hash); // retry with child node expanded
|
||||
},true);
|
||||
} else {
|
||||
var rootBase = stripPath(o.toroot.replace(/\..+$/, ''));
|
||||
if (rootBase=="index" || rootBase=="pages") {
|
||||
expandNode(o, n, true, true);
|
||||
}
|
||||
selectAndHighlight(hash,n);
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
selectAndHighlight(hash);
|
||||
}
|
||||
}
|
||||
|
||||
function getNode(o, po)
|
||||
{
|
||||
po.childrenVisited = true;
|
||||
var l = po.childrenData.length-1;
|
||||
for (var i in po.childrenData) {
|
||||
var nodeData = po.childrenData[i];
|
||||
po.children[i] = newNode(o, po, nodeData[0], nodeData[1], nodeData[2],
|
||||
i==l);
|
||||
}
|
||||
}
|
||||
|
||||
function gotoNode(o,subIndex,root,hash,relpath)
|
||||
{
|
||||
var nti = navTreeSubIndices[subIndex][root+hash];
|
||||
o.breadcrumbs = $.extend(true, [], nti ? nti : navTreeSubIndices[subIndex][root]);
|
||||
if (!o.breadcrumbs && root!=NAVTREE[0][1]) { // fallback: show index
|
||||
navTo(o,NAVTREE[0][1],"",relpath);
|
||||
$('.item').removeClass('selected');
|
||||
$('.item').removeAttr('id');
|
||||
}
|
||||
if (o.breadcrumbs) {
|
||||
o.breadcrumbs.unshift(0); // add 0 for root node
|
||||
showNode(o, o.node, 0, hash);
|
||||
}
|
||||
}
|
||||
|
||||
function navTo(o,root,hash,relpath)
|
||||
{
|
||||
var link = cachedLink();
|
||||
if (link) {
|
||||
var parts = link.split('#');
|
||||
root = parts[0];
|
||||
if (parts.length>1) hash = '#'+parts[1];
|
||||
else hash='';
|
||||
}
|
||||
if (root==NAVTREE[0][1]) {
|
||||
$('#nav-sync').css('top','30px');
|
||||
} else {
|
||||
$('#nav-sync').css('top','5px');
|
||||
}
|
||||
if (hash.match(/^#l\d+$/)) {
|
||||
var anchor=$('a[name='+hash.substring(1)+']');
|
||||
glowEffect(anchor.parent(),1000); // line number
|
||||
hash=''; // strip line number anchors
|
||||
//root=root.replace(/_source\./,'.'); // source link to doc link
|
||||
}
|
||||
var url=root+hash;
|
||||
var i=-1;
|
||||
while (NAVTREEINDEX[i+1]<=url) i++;
|
||||
if (navTreeSubIndices[i]) {
|
||||
gotoNode(o,i,root,hash,relpath)
|
||||
} else {
|
||||
getScript(relpath+'navtreeindex'+i,function(){
|
||||
navTreeSubIndices[i] = eval('NAVTREEINDEX'+i);
|
||||
if (navTreeSubIndices[i]) {
|
||||
gotoNode(o,i,root,hash,relpath);
|
||||
}
|
||||
},true);
|
||||
}
|
||||
}
|
||||
|
||||
function showSyncOff(n,relpath)
|
||||
{
|
||||
n.html('<img src="'+relpath+'sync_off.png" title="'+SYNCOFFMSG+'"/>');
|
||||
}
|
||||
|
||||
function showSyncOn(n,relpath)
|
||||
{
|
||||
n.html('<img src="'+relpath+'sync_on.png"/ title="'+SYNCONMSG+'">');
|
||||
}
|
||||
|
||||
function toggleSyncButton(relpath)
|
||||
{
|
||||
var navSync = $('#nav-sync');
|
||||
if (navSync.hasClass('sync')) {
|
||||
navSync.removeClass('sync');
|
||||
showSyncOff(navSync,relpath);
|
||||
storeLink(stripPath2($(location).attr('pathname'))+$(location).attr('hash'));
|
||||
} else {
|
||||
navSync.addClass('sync');
|
||||
showSyncOn(navSync,relpath);
|
||||
deleteLink();
|
||||
}
|
||||
}
|
||||
|
||||
function initNavTree(toroot,relpath)
|
||||
{
|
||||
var o = new Object();
|
||||
o.toroot = toroot;
|
||||
o.node = new Object();
|
||||
o.node.li = document.getElementById("nav-tree-contents");
|
||||
o.node.childrenData = NAVTREE;
|
||||
o.node.children = new Array();
|
||||
o.node.childrenUL = document.createElement("ul");
|
||||
o.node.getChildrenUL = function() { return o.node.childrenUL; };
|
||||
o.node.li.appendChild(o.node.childrenUL);
|
||||
o.node.depth = 0;
|
||||
o.node.relpath = relpath;
|
||||
o.node.expanded = false;
|
||||
o.node.isLast = true;
|
||||
o.node.plus_img = document.createElement("img");
|
||||
o.node.plus_img.src = relpath+"ftv2pnode.png";
|
||||
o.node.plus_img.width = 16;
|
||||
o.node.plus_img.height = 22;
|
||||
|
||||
if (localStorageSupported()) {
|
||||
var navSync = $('#nav-sync');
|
||||
if (cachedLink()) {
|
||||
showSyncOff(navSync,relpath);
|
||||
navSync.removeClass('sync');
|
||||
} else {
|
||||
showSyncOn(navSync,relpath);
|
||||
}
|
||||
navSync.click(function(){ toggleSyncButton(relpath); });
|
||||
}
|
||||
|
||||
navTo(o,toroot,window.location.hash,relpath);
|
||||
|
||||
$(window).bind('hashchange', function(){
|
||||
if (window.location.hash && window.location.hash.length>1){
|
||||
var a;
|
||||
if ($(location).attr('hash')){
|
||||
var clslink=stripPath($(location).attr('pathname'))+':'+
|
||||
$(location).attr('hash').substring(1);
|
||||
a=$('.item a[class$="'+clslink+'"]');
|
||||
}
|
||||
if (a==null || !$(a).parent().parent().hasClass('selected')){
|
||||
$('.item').removeClass('selected');
|
||||
$('.item').removeAttr('id');
|
||||
}
|
||||
var link=stripPath2($(location).attr('pathname'));
|
||||
navTo(o,link,$(location).attr('hash'),relpath);
|
||||
}
|
||||
})
|
||||
|
||||
$(window).load(showRoot);
|
||||
}
|
||||
|
||||
@@ -0,0 +1,253 @@
|
||||
var NAVTREEINDEX0 =
|
||||
{
|
||||
"_c_o_r_e__m_i_s_r_a__exceptions_pg.html":[4],
|
||||
"_reg_map_pg.html":[5],
|
||||
"_templates_pg.html":[3],
|
||||
"_templates_pg.html#adapt_template_files_sec":[3,1],
|
||||
"_templates_pg.html#template_files_sec":[3,0],
|
||||
"_using__a_r_m_pg.html":[2,2],
|
||||
"_using__a_r_m_pg.html#Using_ARM_Lib_sec":[2,2,0],
|
||||
"_using__c_m_s_i_s.html":[2,0],
|
||||
"_using__v_t_o_r_pg.html":[2,1],
|
||||
"_using_pg.html":[2],
|
||||
"annotated.html":[7],
|
||||
"core_revision_history.html":[1],
|
||||
"device_h_pg.html":[3,4],
|
||||
"device_h_pg.html#core_config_sect":[3,4,1],
|
||||
"device_h_pg.html#core_version_sect":[3,4,2],
|
||||
"device_h_pg.html#device_access":[3,4,3],
|
||||
"device_h_pg.html#device_h_sec":[3,4,4],
|
||||
"device_h_pg.html#interrupt_number_sec":[3,4,0],
|
||||
"functions.html":[8,0],
|
||||
"functions_vars.html":[8,1],
|
||||
"group___core___register__gr.html":[6,3],
|
||||
"group___core___register__gr.html#ga0bf9564ebc1613a8faba014275dac2a4":[6,3,19],
|
||||
"group___core___register__gr.html#ga0f98dfbd252b89d12564472dbeba9c27":[6,3,3],
|
||||
"group___core___register__gr.html#ga2c32fc5c7f8f07fb3d436c6f6fe4e8c8":[6,3,9],
|
||||
"group___core___register__gr.html#ga32da759f46e52c95bcfbde5012260667":[6,3,5],
|
||||
"group___core___register__gr.html#ga360c73eb7ffb16088556f9278953b882":[6,3,14],
|
||||
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|
||||
"group___core___register__gr.html#ga62fa63d39cf22df348857d5f44ab64d9":[6,3,15],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
"group___core___register__gr.html#gaa78e4e6bf619a65e9f01b4af13fed3a8":[6,3,7],
|
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"group___core___register__gr.html#gab898559392ba027814e5bbb5a98b38d2":[6,3,10],
|
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|
||||
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|
||||
"group___core___register__gr.html#gaeb8e5f7564a8ea23678fe3c987b04013":[6,3,1],
|
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"group___dcache__functions__m7.html":[6,9,1],
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
||||
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|
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|
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|
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<tr id="row_4_" class="even"><td class="entry"><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><a class="el" href="_reg_map_pg.html" target="_self">Register Mapping</a></td><td class="desc"></td></tr>
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