添加PAN159资料
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/**************************************************************************//**
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* @file DAP_vendor.c
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* @brief CMSIS-DAP Vendor Commands
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* @version V1.10
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* @date 20. May 2015
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*
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* @note
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* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#include "DAP_config.h"
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#include "DAP.h"
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//**************************************************************************************************
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/**
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\defgroup DAP_Vendor_Adapt_gr Adapt Vendor Commands
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\ingroup DAP_Vendor_gr
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@{
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The file DAP_vendor.c provides template source code for extension of a Debug Unit with
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Vendor Commands. Copy this file to the project folder of the Debug Unit and add the
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file to the MDK-ARM project under the file group Configuration.
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*/
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/** Process DAP Vendor Command and prepare Response Data
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\param request pointer to request data
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\param response pointer to response data
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\return number of bytes in response (lower 16 bits)
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number of bytes in request (upper 16 bits)
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*/
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uint32_t DAP_ProcessVendorCommand(const uint8_t *request, uint8_t *response) {
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uint32_t num = (1U << 16) | 1U;
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*response++ = *request; // copy Command ID
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switch (*request++) { // first byte in request is Command ID
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case ID_DAP_Vendor0:
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#if 0 // example user command
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num += 1U << 16; // increment request count
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if (*request == 1U) { // when first command data byte is 1
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*response++ = 'X'; // send 'X' as response
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num++; // increment response count
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}
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#endif
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break;
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case ID_DAP_Vendor1: break;
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case ID_DAP_Vendor2: break;
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case ID_DAP_Vendor3: break;
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case ID_DAP_Vendor4: break;
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case ID_DAP_Vendor5: break;
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case ID_DAP_Vendor6: break;
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case ID_DAP_Vendor7: break;
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case ID_DAP_Vendor8: break;
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case ID_DAP_Vendor9: break;
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case ID_DAP_Vendor10: break;
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case ID_DAP_Vendor11: break;
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case ID_DAP_Vendor12: break;
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case ID_DAP_Vendor13: break;
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case ID_DAP_Vendor14: break;
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case ID_DAP_Vendor15: break;
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case ID_DAP_Vendor16: break;
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case ID_DAP_Vendor17: break;
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case ID_DAP_Vendor18: break;
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case ID_DAP_Vendor19: break;
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case ID_DAP_Vendor20: break;
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case ID_DAP_Vendor21: break;
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case ID_DAP_Vendor22: break;
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case ID_DAP_Vendor23: break;
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case ID_DAP_Vendor24: break;
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case ID_DAP_Vendor25: break;
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case ID_DAP_Vendor26: break;
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case ID_DAP_Vendor27: break;
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case ID_DAP_Vendor28: break;
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case ID_DAP_Vendor29: break;
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case ID_DAP_Vendor30: break;
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case ID_DAP_Vendor31: break;
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}
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return (num);
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}
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///@}
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@@ -0,0 +1,358 @@
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/******************************************************************************
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* @file JTAG_DP.c
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* @brief CMSIS-DAP JTAG DP I/O
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* @version V1.10
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* @date 20. May 2015
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*
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* @note
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* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#include "DAP_config.h"
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#include "DAP.h"
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// JTAG Macros
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#define PIN_TCK_SET PIN_SWCLK_TCK_SET
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#define PIN_TCK_CLR PIN_SWCLK_TCK_CLR
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#define PIN_TMS_SET PIN_SWDIO_TMS_SET
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#define PIN_TMS_CLR PIN_SWDIO_TMS_CLR
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#define JTAG_CYCLE_TCK() \
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PIN_TCK_CLR(); \
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PIN_DELAY(); \
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PIN_TCK_SET(); \
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PIN_DELAY()
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#define JTAG_CYCLE_TDI(tdi) \
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PIN_TDI_OUT(tdi); \
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PIN_TCK_CLR(); \
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PIN_DELAY(); \
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PIN_TCK_SET(); \
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PIN_DELAY()
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#define JTAG_CYCLE_TDO(tdo) \
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PIN_TCK_CLR(); \
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PIN_DELAY(); \
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tdo = PIN_TDO_IN(); \
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PIN_TCK_SET(); \
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PIN_DELAY()
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#define JTAG_CYCLE_TDIO(tdi,tdo) \
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PIN_TDI_OUT(tdi); \
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PIN_TCK_CLR(); \
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PIN_DELAY(); \
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tdo = PIN_TDO_IN(); \
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PIN_TCK_SET(); \
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PIN_DELAY()
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#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
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#if (DAP_JTAG != 0)
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// Generate JTAG Sequence
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// info: sequence information
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// tdi: pointer to TDI generated data
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// tdo: pointer to TDO captured data
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// return: none
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void JTAG_Sequence (uint32_t info, const uint8_t *tdi, uint8_t *tdo) {
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uint32_t i_val;
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uint32_t o_val;
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uint32_t bit;
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uint32_t n, k;
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n = info & JTAG_SEQUENCE_TCK;
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if (n == 0U) { n = 64U; }
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if (info & JTAG_SEQUENCE_TMS) {
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PIN_TMS_SET();
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} else {
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PIN_TMS_CLR();
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}
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while (n) {
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i_val = *tdi++;
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o_val = 0U;
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for (k = 8U; k && n; k--, n--) {
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JTAG_CYCLE_TDIO(i_val, bit);
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i_val >>= 1;
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o_val >>= 1;
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o_val |= bit << 7;
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}
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o_val >>= k;
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if (info & JTAG_SEQUENCE_TDO) {
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*tdo++ = (uint8_t)o_val;
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}
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}
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}
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// JTAG Set IR
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// ir: IR value
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// return: none
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#define JTAG_IR_Function(speed) /**/ \
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void JTAG_IR_##speed (uint32_t ir) { \
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uint32_t n; \
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\
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PIN_TMS_SET(); \
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JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \
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JTAG_CYCLE_TCK(); /* Select-IR-Scan */ \
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PIN_TMS_CLR(); \
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JTAG_CYCLE_TCK(); /* Capture-IR */ \
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JTAG_CYCLE_TCK(); /* Shift-IR */ \
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\
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PIN_TDI_OUT(1U); \
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for (n = DAP_Data.jtag_dev.ir_before[DAP_Data.jtag_dev.index]; n; n--) { \
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JTAG_CYCLE_TCK(); /* Bypass before data */ \
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} \
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for (n = DAP_Data.jtag_dev.ir_length[DAP_Data.jtag_dev.index] - 1U; n; n--) { \
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JTAG_CYCLE_TDI(ir); /* Set IR bits (except last) */ \
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ir >>= 1; \
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} \
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n = DAP_Data.jtag_dev.ir_after[DAP_Data.jtag_dev.index]; \
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if (n) { \
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JTAG_CYCLE_TDI(ir); /* Set last IR bit */ \
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PIN_TDI_OUT(1U); \
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for (--n; n; n--) { \
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JTAG_CYCLE_TCK(); /* Bypass after data */ \
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} \
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PIN_TMS_SET(); \
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JTAG_CYCLE_TCK(); /* Bypass & Exit1-IR */ \
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} else { \
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PIN_TMS_SET(); \
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JTAG_CYCLE_TDI(ir); /* Set last IR bit & Exit1-IR */ \
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} \
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\
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JTAG_CYCLE_TCK(); /* Update-IR */ \
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PIN_TMS_CLR(); \
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JTAG_CYCLE_TCK(); /* Idle */ \
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PIN_TDI_OUT(1U); \
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}
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// JTAG Transfer I/O
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// request: A[3:2] RnW APnDP
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// data: DATA[31:0]
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// return: ACK[2:0]
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#define JTAG_TransferFunction(speed) /**/ \
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uint8_t JTAG_Transfer##speed (uint32_t request, uint32_t *data) { \
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uint32_t ack; \
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uint32_t bit; \
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uint32_t val; \
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uint32_t n; \
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\
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PIN_TMS_SET(); \
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JTAG_CYCLE_TCK(); /* Select-DR-Scan */ \
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PIN_TMS_CLR(); \
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JTAG_CYCLE_TCK(); /* Capture-DR */ \
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JTAG_CYCLE_TCK(); /* Shift-DR */ \
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\
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for (n = DAP_Data.jtag_dev.index; n; n--) { \
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JTAG_CYCLE_TCK(); /* Bypass before data */ \
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} \
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\
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JTAG_CYCLE_TDIO(request >> 1, bit); /* Set RnW, Get ACK.0 */ \
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ack = bit << 1; \
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JTAG_CYCLE_TDIO(request >> 2, bit); /* Set A2, Get ACK.1 */ \
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ack |= bit << 0; \
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JTAG_CYCLE_TDIO(request >> 3, bit); /* Set A3, Get ACK.2 */ \
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ack |= bit << 2; \
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\
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if (ack != DAP_TRANSFER_OK) { \
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/* Exit on error */ \
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PIN_TMS_SET(); \
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JTAG_CYCLE_TCK(); /* Exit1-DR */ \
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goto exit; \
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} \
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\
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if (request & DAP_TRANSFER_RnW) { \
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/* Read Transfer */ \
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val = 0U; \
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for (n = 31U; n; n--) { \
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JTAG_CYCLE_TDO(bit); /* Get D0..D30 */ \
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val |= bit << 31; \
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val >>= 1; \
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} \
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n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1U; \
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if (n) { \
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JTAG_CYCLE_TDO(bit); /* Get D31 */ \
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for (--n; n; n--) { \
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JTAG_CYCLE_TCK(); /* Bypass after data */ \
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} \
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PIN_TMS_SET(); \
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JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \
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} else { \
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PIN_TMS_SET(); \
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JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */ \
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} \
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val |= bit << 31; \
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if (data) { *data = val; } \
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} else { \
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/* Write Transfer */ \
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val = *data; \
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for (n = 31U; n; n--) { \
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JTAG_CYCLE_TDI(val); /* Set D0..D30 */ \
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val >>= 1; \
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} \
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n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1u; \
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if (n) { \
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JTAG_CYCLE_TDI(val); /* Set D31 */ \
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for (--n; n; n--) { \
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JTAG_CYCLE_TCK(); /* Bypass after data */ \
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} \
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PIN_TMS_SET(); \
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JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */ \
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} else { \
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PIN_TMS_SET(); \
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JTAG_CYCLE_TDI(val); /* Set D31 & Exit1-DR */ \
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} \
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} \
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\
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exit: \
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JTAG_CYCLE_TCK(); /* Update-DR */ \
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PIN_TMS_CLR(); \
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JTAG_CYCLE_TCK(); /* Idle */ \
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PIN_TDI_OUT(1U); \
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\
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/* Idle cycles */ \
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n = DAP_Data.transfer.idle_cycles; \
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while (n--) { \
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JTAG_CYCLE_TCK(); /* Idle */ \
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} \
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\
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return ((uint8_t)ack); \
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}
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#undef PIN_DELAY
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#define PIN_DELAY() PIN_DELAY_FAST()
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JTAG_IR_Function(Fast);
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JTAG_TransferFunction(Fast);
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#undef PIN_DELAY
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#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
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JTAG_IR_Function(Slow);
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JTAG_TransferFunction(Slow);
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// JTAG Read IDCODE register
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// return: value read
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uint32_t JTAG_ReadIDCode (void) {
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uint32_t bit;
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uint32_t val;
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uint32_t n;
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PIN_TMS_SET();
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JTAG_CYCLE_TCK(); /* Select-DR-Scan */
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PIN_TMS_CLR();
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JTAG_CYCLE_TCK(); /* Capture-DR */
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JTAG_CYCLE_TCK(); /* Shift-DR */
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for (n = DAP_Data.jtag_dev.index; n; n--) {
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JTAG_CYCLE_TCK(); /* Bypass before data */
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}
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val = 0U;
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for (n = 31U; n; n--) {
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JTAG_CYCLE_TDO(bit); /* Get D0..D30 */
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val |= bit << 31;
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val >>= 1;
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}
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PIN_TMS_SET();
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JTAG_CYCLE_TDO(bit); /* Get D31 & Exit1-DR */
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val |= bit << 31;
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JTAG_CYCLE_TCK(); /* Update-DR */
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||||
PIN_TMS_CLR();
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JTAG_CYCLE_TCK(); /* Idle */
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||||
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return (val);
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}
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// JTAG Write ABORT register
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// data: value to write
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// return: none
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void JTAG_WriteAbort (uint32_t data) {
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uint32_t n;
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||||
PIN_TMS_SET();
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||||
JTAG_CYCLE_TCK(); /* Select-DR-Scan */
|
||||
PIN_TMS_CLR();
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||||
JTAG_CYCLE_TCK(); /* Capture-DR */
|
||||
JTAG_CYCLE_TCK(); /* Shift-DR */
|
||||
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||||
for (n = DAP_Data.jtag_dev.index; n; n--) {
|
||||
JTAG_CYCLE_TCK(); /* Bypass before data */
|
||||
}
|
||||
|
||||
PIN_TDI_OUT(0U);
|
||||
JTAG_CYCLE_TCK(); /* Set RnW=0 (Write) */
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||||
JTAG_CYCLE_TCK(); /* Set A2=0 */
|
||||
JTAG_CYCLE_TCK(); /* Set A3=0 */
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||||
for (n = 31U; n; n--) {
|
||||
JTAG_CYCLE_TDI(data); /* Set D0..D30 */
|
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data >>= 1;
|
||||
}
|
||||
n = DAP_Data.jtag_dev.count - DAP_Data.jtag_dev.index - 1u;
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||||
if (n) {
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||||
JTAG_CYCLE_TDI(data); /* Set D31 */
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||||
for (--n; n; n--) {
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JTAG_CYCLE_TCK(); /* Bypass after data */
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||||
}
|
||||
PIN_TMS_SET();
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||||
JTAG_CYCLE_TCK(); /* Bypass & Exit1-DR */
|
||||
} else {
|
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PIN_TMS_SET();
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||||
JTAG_CYCLE_TDI(data); /* Set D31 & Exit1-DR */
|
||||
}
|
||||
|
||||
JTAG_CYCLE_TCK(); /* Update-DR */
|
||||
PIN_TMS_CLR();
|
||||
JTAG_CYCLE_TCK(); /* Idle */
|
||||
PIN_TDI_OUT(1U);
|
||||
}
|
||||
|
||||
|
||||
// JTAG Set IR
|
||||
// ir: IR value
|
||||
// return: none
|
||||
void JTAG_IR (uint32_t ir) {
|
||||
if (DAP_Data.fast_clock) {
|
||||
JTAG_IR_Fast(ir);
|
||||
} else {
|
||||
JTAG_IR_Slow(ir);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// JTAG Transfer I/O
|
||||
// request: A[3:2] RnW APnDP
|
||||
// data: DATA[31:0]
|
||||
// return: ACK[2:0]
|
||||
uint8_t JTAG_Transfer(uint32_t request, uint32_t *data) {
|
||||
if (DAP_Data.fast_clock) {
|
||||
return JTAG_TransferFast(request, data);
|
||||
} else {
|
||||
return JTAG_TransferSlow(request, data);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif /* (DAP_JTAG != 0) */
|
||||
@@ -0,0 +1,603 @@
|
||||
/******************************************************************************
|
||||
* @file SWO.c
|
||||
* @brief CMSIS-DAP SWO I/O
|
||||
* @version V1.00
|
||||
* @date 20. May 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
#if (SWO_UART != 0)
|
||||
#include "Driver_USART.h"
|
||||
#endif
|
||||
|
||||
|
||||
#if (SWO_UART != 0)
|
||||
|
||||
#ifndef USART_PORT
|
||||
#define USART_PORT 0 /* USART Port Number */
|
||||
#endif
|
||||
|
||||
// USART Driver
|
||||
#define _USART_Driver_(n) Driver_USART##n
|
||||
#define USART_Driver_(n) _USART_Driver_(n)
|
||||
extern ARM_DRIVER_USART USART_Driver_(USART_PORT);
|
||||
#define pUSART (&USART_Driver_(USART_PORT))
|
||||
|
||||
static uint8_t USART_Ready;
|
||||
|
||||
#endif /* (SWO_UART != 0) */
|
||||
|
||||
|
||||
#if ((SWO_UART != 0) || (SWO_MANCHESTER != 0))
|
||||
|
||||
|
||||
// Trace State
|
||||
static uint8_t TraceTransport = 0U; /* Trace Transport */
|
||||
static uint8_t TraceMode = 0U; /* Trace Mode */
|
||||
static uint8_t TraceStatus = 0U; /* Trace Status without Errors */
|
||||
static uint8_t TraceError[2] = {0U, 0U}; /* Trace Error flags (banked) */
|
||||
static uint8_t TraceError_n = 0U; /* Active Trace Error bank */
|
||||
|
||||
// Trace Buffer
|
||||
static uint8_t TraceBuf[SWO_BUFFER_SIZE]; /* Trace Buffer (must be 2^n) */
|
||||
static volatile uint32_t TraceIn = 0U; /* Incoming Trace Index */
|
||||
static volatile uint32_t TraceOut = 0U; /* Outgoing Trace Index */
|
||||
static volatile uint32_t TracePending = 0U; /* Pending Trace Count */
|
||||
|
||||
// Trace Helper functions
|
||||
static void ClearTrace (void);
|
||||
static uint32_t GetTraceSpace (void);
|
||||
static uint32_t GetTraceCount (void);
|
||||
static uint8_t GetTraceStatus (void);
|
||||
static void SetTraceError (uint8_t flag);
|
||||
|
||||
|
||||
#if (SWO_UART != 0)
|
||||
|
||||
// USART Driver Callback function
|
||||
// event: event mask
|
||||
static void USART_Callback (uint32_t event) {
|
||||
uint32_t count;
|
||||
|
||||
if (event & ARM_USART_EVENT_RECEIVE_COMPLETE) {
|
||||
TracePending = 0U;
|
||||
TraceIn += pUSART->GetRxCount();
|
||||
count = GetTraceSpace();
|
||||
if (count != 0U) {
|
||||
pUSART->Receive(&TraceBuf[TraceIn & (SWO_BUFFER_SIZE-1U)], count);
|
||||
} else {
|
||||
TraceStatus = DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED;
|
||||
}
|
||||
}
|
||||
if (event & ARM_USART_EVENT_RX_OVERFLOW) {
|
||||
SetTraceError(DAP_SWO_BUFFER_OVERRUN);
|
||||
}
|
||||
if (event & (ARM_USART_EVENT_RX_BREAK |
|
||||
ARM_USART_EVENT_RX_FRAMING_ERROR |
|
||||
ARM_USART_EVENT_RX_PARITY_ERROR)) {
|
||||
SetTraceError(DAP_SWO_STREAM_ERROR);
|
||||
}
|
||||
}
|
||||
|
||||
// Enable or disable UART SWO Mode
|
||||
// enable: enable flag
|
||||
// return: 1 - Success, 0 - Error
|
||||
__weak uint32_t UART_SWO_Mode (uint32_t enable) {
|
||||
int32_t status;
|
||||
|
||||
USART_Ready = 0U;
|
||||
|
||||
if (enable) {
|
||||
status = pUSART->Initialize(USART_Callback);
|
||||
if (status != ARM_DRIVER_OK) { return (0U); }
|
||||
status = pUSART->PowerControl(ARM_POWER_FULL);
|
||||
if (status != ARM_DRIVER_OK) {
|
||||
pUSART->Uninitialize();
|
||||
return (0U);
|
||||
}
|
||||
} else {
|
||||
pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
|
||||
pUSART->PowerControl(ARM_POWER_OFF);
|
||||
pUSART->Uninitialize();
|
||||
}
|
||||
return (1U);
|
||||
}
|
||||
|
||||
// Configure UART SWO Baudrate
|
||||
// baudrate: requested baudrate
|
||||
// return: actual baudrate or 0 when not configured
|
||||
__weak uint32_t UART_SWO_Baudrate (uint32_t baudrate) {
|
||||
int32_t status;
|
||||
uint32_t count;
|
||||
|
||||
if (baudrate > SWO_UART_MAX_BAUDRATE) {
|
||||
baudrate = SWO_UART_MAX_BAUDRATE;
|
||||
}
|
||||
|
||||
if (TraceStatus & DAP_SWO_CAPTURE_ACTIVE) {
|
||||
pUSART->Control(ARM_USART_CONTROL_RX, 0U);
|
||||
if (pUSART->GetStatus().rx_busy) {
|
||||
TracePending = 0U;
|
||||
TraceIn += pUSART->GetRxCount();
|
||||
pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
|
||||
}
|
||||
}
|
||||
|
||||
status = pUSART->Control(ARM_USART_MODE_ASYNCHRONOUS |
|
||||
ARM_USART_DATA_BITS_8 |
|
||||
ARM_USART_PARITY_NONE |
|
||||
ARM_USART_STOP_BITS_1,
|
||||
baudrate);
|
||||
|
||||
if (status == ARM_DRIVER_OK) {
|
||||
USART_Ready = 1U;
|
||||
} else {
|
||||
USART_Ready = 0U;
|
||||
baudrate = 0U;
|
||||
}
|
||||
|
||||
if ((TraceStatus & DAP_SWO_CAPTURE_ACTIVE) && USART_Ready) {
|
||||
pUSART->Control(ARM_USART_CONTROL_RX, 1U);
|
||||
count = GetTraceSpace();
|
||||
if (count != 0U) {
|
||||
pUSART->Receive(&TraceBuf[TraceIn & (SWO_BUFFER_SIZE-1U)], count);
|
||||
} else {
|
||||
TraceStatus = DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED;
|
||||
}
|
||||
}
|
||||
|
||||
return (baudrate);
|
||||
}
|
||||
|
||||
// Control UART SWO Capture
|
||||
// active: active flag
|
||||
// return: 1 - Success, 0 - Error
|
||||
__weak uint32_t UART_SWO_Control (uint32_t active) {
|
||||
int32_t status;
|
||||
|
||||
if (active) {
|
||||
if (!USART_Ready) { return (0U); }
|
||||
status = pUSART->Control(ARM_USART_CONTROL_RX, 1U);
|
||||
if (status != ARM_DRIVER_OK) { return (0U); }
|
||||
status = pUSART->Receive(TraceBuf, SWO_BUFFER_SIZE);
|
||||
if (status != ARM_DRIVER_OK) { return (0U); }
|
||||
} else {
|
||||
pUSART->Control(ARM_USART_CONTROL_RX, 0U);
|
||||
if (pUSART->GetStatus().rx_busy) {
|
||||
TracePending = 0U;
|
||||
TraceIn += pUSART->GetRxCount();
|
||||
pUSART->Control(ARM_USART_ABORT_RECEIVE, 0U);
|
||||
}
|
||||
}
|
||||
return (1U);
|
||||
}
|
||||
|
||||
// Start UART SWO Capture
|
||||
// buf: pointer to buffer for capturing
|
||||
// count: number of bytes to capture
|
||||
__weak void UART_SWO_Capture (uint8_t *buf, uint32_t count) {
|
||||
pUSART->Receive(buf, count);
|
||||
}
|
||||
|
||||
// Update UART SWO Trace Info
|
||||
__weak void UART_SWO_Update (void) {
|
||||
TracePending = pUSART->GetRxCount();
|
||||
}
|
||||
|
||||
#endif /* (SWO_UART != 0) */
|
||||
|
||||
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
|
||||
// Enable or disable Manchester SWO Mode
|
||||
// enable: enable flag
|
||||
// return: 1 - Success, 0 - Error
|
||||
__weak uint32_t Manchester_SWO_Mode (uint32_t enable) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
// Configure Manchester SWO Baudrate
|
||||
// baudrate: requested baudrate
|
||||
// return: actual baudrate or 0 when not configured
|
||||
__weak uint32_t Manchester_SWO_Baudrate (uint32_t baudrate) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
// Control Manchester SWO Capture
|
||||
// active: active flag
|
||||
// return: 1 - Success, 0 - Error
|
||||
__weak uint32_t Manchester_SWO_Control (uint32_t active) {
|
||||
return (0U);
|
||||
}
|
||||
|
||||
// Start Manchester SWO Capture
|
||||
// buf: pointer to buffer for capturing
|
||||
// count: number of bytes to capture
|
||||
__weak void Manchester_SWO_Capture (uint8_t *buf, uint32_t count) {
|
||||
}
|
||||
|
||||
// Update Manchester SWO Trace Info
|
||||
__weak void Manchester_SWO_Update (void) {
|
||||
}
|
||||
|
||||
#endif /* (SWO_MANCHESTER != 0) */
|
||||
|
||||
|
||||
// Clear Trace Errors and Data
|
||||
static void ClearTrace (void) {
|
||||
TraceError[0] = 0U;
|
||||
TraceError[1] = 0U;
|
||||
TraceError_n = 0U;
|
||||
TraceIn = 0U;
|
||||
TraceOut = 0U;
|
||||
TracePending = 0U;
|
||||
}
|
||||
|
||||
// Get Trace Space
|
||||
// return: number of contiguous free bytes in trace buffer
|
||||
static uint32_t GetTraceSpace (void) {
|
||||
uint32_t index;
|
||||
uint32_t limit;
|
||||
uint32_t count;
|
||||
|
||||
index = TraceIn & (SWO_BUFFER_SIZE-1U);
|
||||
limit = SWO_BUFFER_SIZE - index;
|
||||
count = SWO_BUFFER_SIZE - (TraceIn - TraceOut);
|
||||
if (count > limit) {
|
||||
count = limit;
|
||||
}
|
||||
|
||||
return (count);
|
||||
}
|
||||
|
||||
// Get Trace Count
|
||||
// return: number of available data bytes in trace buffer
|
||||
static uint32_t GetTraceCount (void) {
|
||||
uint32_t count;
|
||||
|
||||
if (TraceStatus == DAP_SWO_CAPTURE_ACTIVE) {
|
||||
count = (TraceIn - TraceOut) + TracePending;
|
||||
if (TracePending == 0U) {
|
||||
count = TraceIn - TraceOut;
|
||||
}
|
||||
} else {
|
||||
count = TraceIn - TraceOut;
|
||||
}
|
||||
|
||||
return (count);
|
||||
}
|
||||
|
||||
// Get Trace Status (clear Error flags)
|
||||
// return: Trace Status (Active flag and Error flags)
|
||||
static uint8_t GetTraceStatus (void) {
|
||||
uint8_t status;
|
||||
uint32_t n;
|
||||
|
||||
n = TraceError_n;
|
||||
TraceError_n ^= 1U;
|
||||
status = TraceStatus | TraceError[n];
|
||||
TraceError[n] = 0U;
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
// Set Trace Error flag(s)
|
||||
// flag: error flag(s) to set
|
||||
static void SetTraceError (uint8_t flag) {
|
||||
TraceError[TraceError_n] |= flag;
|
||||
}
|
||||
|
||||
|
||||
// Process SWO Transport command and prepare response
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t SWO_Transport (const uint8_t *request, uint8_t *response) {
|
||||
uint8_t transport;
|
||||
uint32_t result;
|
||||
|
||||
if (!(TraceStatus & DAP_SWO_CAPTURE_ACTIVE)) {
|
||||
transport = *request;
|
||||
switch (transport) {
|
||||
case 0:
|
||||
case 1:
|
||||
TraceTransport = transport;
|
||||
result = 1U;
|
||||
break;
|
||||
default:
|
||||
result = 0U;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
result = 0U;
|
||||
}
|
||||
|
||||
if (result != 0U) {
|
||||
*response = DAP_OK;
|
||||
} else {
|
||||
*response = DAP_ERROR;
|
||||
}
|
||||
|
||||
return ((1U << 16) | 1U);
|
||||
}
|
||||
|
||||
|
||||
// Process SWO Mode command and prepare response
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t SWO_Mode (const uint8_t *request, uint8_t *response) {
|
||||
uint8_t mode;
|
||||
uint32_t result;
|
||||
|
||||
mode = *request;
|
||||
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
UART_SWO_Mode(0U);
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
Manchester_SWO_Mode(0U);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
switch (mode) {
|
||||
case DAP_SWO_OFF:
|
||||
result = 1U;
|
||||
break;
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
result = UART_SWO_Mode(1U);
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
result = Manchester_SWO_Mode(1U);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = 0U;
|
||||
break;
|
||||
}
|
||||
if (result != 0U) {
|
||||
TraceMode = mode;
|
||||
} else {
|
||||
TraceMode = DAP_SWO_OFF;
|
||||
}
|
||||
TraceStatus = 0U;
|
||||
ClearTrace();
|
||||
|
||||
if (result != 0U) {
|
||||
*response = DAP_OK;
|
||||
} else {
|
||||
*response = DAP_ERROR;
|
||||
}
|
||||
|
||||
return ((1U << 16) | 1U);
|
||||
}
|
||||
|
||||
|
||||
// Process SWO Baudrate command and prepare response
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t SWO_Baudrate (const uint8_t *request, uint8_t *response) {
|
||||
uint32_t baudrate;
|
||||
|
||||
baudrate = (*(request+0) << 0) |
|
||||
(*(request+1) << 8) |
|
||||
(*(request+2) << 16) |
|
||||
(*(request+3) << 24);
|
||||
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
baudrate = UART_SWO_Baudrate(baudrate);
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
baudrate = Manchester_SWO_Baudrate(baudrate);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
baudrate = 0U;
|
||||
break;
|
||||
}
|
||||
|
||||
if (baudrate == 0U) {
|
||||
TraceStatus = 0U;
|
||||
}
|
||||
|
||||
*response++ = (uint8_t)(baudrate >> 0);
|
||||
*response++ = (uint8_t)(baudrate >> 8);
|
||||
*response++ = (uint8_t)(baudrate >> 16);
|
||||
*response = (uint8_t)(baudrate >> 24);
|
||||
|
||||
return ((4U << 16) | 4U);
|
||||
}
|
||||
|
||||
|
||||
// Process SWO Control command and prepare response
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t SWO_Control (const uint8_t *request, uint8_t *response) {
|
||||
uint8_t active;
|
||||
uint32_t result;
|
||||
|
||||
active = *request & DAP_SWO_CAPTURE_ACTIVE;
|
||||
|
||||
if (active != (TraceStatus & DAP_SWO_CAPTURE_ACTIVE)) {
|
||||
if (active) {
|
||||
ClearTrace();
|
||||
}
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
result = UART_SWO_Control(active);
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
result = Manchester_SWO_Control(active);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
result = 0U;
|
||||
break;
|
||||
}
|
||||
if (result != 0U) {
|
||||
TraceStatus = active;
|
||||
}
|
||||
} else {
|
||||
result = 1U;
|
||||
}
|
||||
|
||||
if (result != 0U) {
|
||||
*response = DAP_OK;
|
||||
} else {
|
||||
*response = DAP_ERROR;
|
||||
}
|
||||
|
||||
return ((1U << 16) | 1U);
|
||||
}
|
||||
|
||||
|
||||
// Process SWO Status command and prepare response
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response
|
||||
uint32_t SWO_Status (uint8_t *response) {
|
||||
uint8_t status;
|
||||
uint32_t count;
|
||||
|
||||
if (TraceStatus == DAP_SWO_CAPTURE_ACTIVE) {
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
UART_SWO_Update();
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
Manchester_SWO_Update();
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
status = GetTraceStatus();
|
||||
count = GetTraceCount();
|
||||
|
||||
*response++ = status;
|
||||
*response++ = (uint8_t)(count >> 0);
|
||||
*response++ = (uint8_t)(count >> 8);
|
||||
*response++ = (uint8_t)(count >> 16);
|
||||
*response = (uint8_t)(count >> 24);
|
||||
|
||||
return (5U);
|
||||
}
|
||||
|
||||
|
||||
// Process SWO Data command and prepare response
|
||||
// request: pointer to request data
|
||||
// response: pointer to response data
|
||||
// return: number of bytes in response (lower 16 bits)
|
||||
// number of bytes in request (upper 16 bits)
|
||||
uint32_t SWO_Data (const uint8_t *request, uint8_t *response) {
|
||||
uint8_t status;
|
||||
uint32_t count;
|
||||
uint32_t n;
|
||||
|
||||
if (TraceStatus == DAP_SWO_CAPTURE_ACTIVE) {
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
UART_SWO_Update();
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
Manchester_SWO_Update();
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
status = GetTraceStatus();
|
||||
count = GetTraceCount();
|
||||
|
||||
if (TraceTransport == 1U) {
|
||||
n = (*(request+0) << 0) |
|
||||
(*(request+1) << 8);
|
||||
} else {
|
||||
n = 0U;
|
||||
}
|
||||
if (count > n) {
|
||||
count = n;
|
||||
}
|
||||
|
||||
*response++ = status;
|
||||
*response++ = (uint8_t)(count >> 0);
|
||||
*response++ = (uint8_t)(count >> 8);
|
||||
|
||||
for (n = count; n; n--) {
|
||||
*response++ = TraceBuf[TraceOut++ & (SWO_BUFFER_SIZE-1U)];
|
||||
}
|
||||
|
||||
if (TraceStatus == (DAP_SWO_CAPTURE_ACTIVE | DAP_SWO_CAPTURE_PAUSED)) {
|
||||
n = GetTraceSpace();
|
||||
if (n != 0U) {
|
||||
switch (TraceMode) {
|
||||
#if (SWO_UART != 0)
|
||||
case DAP_SWO_UART:
|
||||
UART_SWO_Capture(&TraceBuf[TraceIn & (SWO_BUFFER_SIZE-1U)], n);
|
||||
TraceStatus = DAP_SWO_CAPTURE_ACTIVE;
|
||||
break;
|
||||
#endif
|
||||
#if (SWO_MANCHESTER != 0)
|
||||
case DAP_SWO_MANCHESTER:
|
||||
Manchester_SWO_Capture(&TraceBuf[TraceIn & (SWO_BUFFER_SIZE-1U)], n);
|
||||
TraceStatus = DAP_SWO_CAPTURE_ACTIVE;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ((2U << 16) | (3U + count));
|
||||
}
|
||||
|
||||
|
||||
#endif /* ((SWO_UART != 0) || (SWO_MANCHESTER != 0)) */
|
||||
@@ -0,0 +1,237 @@
|
||||
/******************************************************************************
|
||||
* @file SW_DP.c
|
||||
* @brief CMSIS-DAP SW DP I/O
|
||||
* @version V1.10
|
||||
* @date 20. May 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
|
||||
|
||||
// SW Macros
|
||||
|
||||
#define PIN_SWCLK_SET PIN_SWCLK_TCK_SET
|
||||
#define PIN_SWCLK_CLR PIN_SWCLK_TCK_CLR
|
||||
|
||||
#define SW_CLOCK_CYCLE() \
|
||||
PIN_SWCLK_CLR(); \
|
||||
PIN_DELAY(); \
|
||||
PIN_SWCLK_SET(); \
|
||||
PIN_DELAY()
|
||||
|
||||
#define SW_WRITE_BIT(bit) \
|
||||
PIN_SWDIO_OUT(bit); \
|
||||
PIN_SWCLK_CLR(); \
|
||||
PIN_DELAY(); \
|
||||
PIN_SWCLK_SET(); \
|
||||
PIN_DELAY()
|
||||
|
||||
#define SW_READ_BIT(bit) \
|
||||
PIN_SWCLK_CLR(); \
|
||||
PIN_DELAY(); \
|
||||
bit = PIN_SWDIO_IN(); \
|
||||
PIN_SWCLK_SET(); \
|
||||
PIN_DELAY()
|
||||
|
||||
#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
|
||||
|
||||
|
||||
// Generate SWJ Sequence
|
||||
// count: sequence bit count
|
||||
// data: pointer to sequence bit data
|
||||
// return: none
|
||||
#if ((DAP_SWD != 0) || (DAP_JTAG != 0))
|
||||
void SWJ_Sequence (uint32_t count, const uint8_t *data) {
|
||||
uint32_t val;
|
||||
uint32_t n;
|
||||
|
||||
val = 0U;
|
||||
n = 0U;
|
||||
while (count--) {
|
||||
if (n == 0U) {
|
||||
val = *data++;
|
||||
n = 8U;
|
||||
}
|
||||
if (val & 1U) {
|
||||
PIN_SWDIO_TMS_SET();
|
||||
} else {
|
||||
PIN_SWDIO_TMS_CLR();
|
||||
}
|
||||
SW_CLOCK_CYCLE();
|
||||
val >>= 1;
|
||||
n--;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if (DAP_SWD != 0)
|
||||
|
||||
|
||||
// SWD Transfer I/O
|
||||
// request: A[3:2] RnW APnDP
|
||||
// data: DATA[31:0]
|
||||
// return: ACK[2:0]
|
||||
#define SWD_TransferFunction(speed) /**/ \
|
||||
uint8_t SWD_Transfer##speed (uint32_t request, uint32_t *data) { \
|
||||
uint32_t ack; \
|
||||
uint32_t bit; \
|
||||
uint32_t val; \
|
||||
uint32_t parity; \
|
||||
\
|
||||
uint32_t n; \
|
||||
\
|
||||
/* Packet Request */ \
|
||||
parity = 0U; \
|
||||
SW_WRITE_BIT(1U); /* Start Bit */ \
|
||||
bit = request >> 0; \
|
||||
SW_WRITE_BIT(bit); /* APnDP Bit */ \
|
||||
parity += bit; \
|
||||
bit = request >> 1; \
|
||||
SW_WRITE_BIT(bit); /* RnW Bit */ \
|
||||
parity += bit; \
|
||||
bit = request >> 2; \
|
||||
SW_WRITE_BIT(bit); /* A2 Bit */ \
|
||||
parity += bit; \
|
||||
bit = request >> 3; \
|
||||
SW_WRITE_BIT(bit); /* A3 Bit */ \
|
||||
parity += bit; \
|
||||
SW_WRITE_BIT(parity); /* Parity Bit */ \
|
||||
SW_WRITE_BIT(0U); /* Stop Bit */ \
|
||||
SW_WRITE_BIT(1U); /* Park Bit */ \
|
||||
\
|
||||
/* Turnaround */ \
|
||||
PIN_SWDIO_OUT_DISABLE(); \
|
||||
for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); \
|
||||
} \
|
||||
\
|
||||
/* Acknowledge response */ \
|
||||
SW_READ_BIT(bit); \
|
||||
ack = bit << 0; \
|
||||
SW_READ_BIT(bit); \
|
||||
ack |= bit << 1; \
|
||||
SW_READ_BIT(bit); \
|
||||
ack |= bit << 2; \
|
||||
\
|
||||
if (ack == DAP_TRANSFER_OK) { /* OK response */ \
|
||||
/* Data transfer */ \
|
||||
if (request & DAP_TRANSFER_RnW) { \
|
||||
/* Read data */ \
|
||||
val = 0U; \
|
||||
parity = 0U; \
|
||||
for (n = 32U; n; n--) { \
|
||||
SW_READ_BIT(bit); /* Read RDATA[0:31] */ \
|
||||
parity += bit; \
|
||||
val >>= 1; \
|
||||
val |= bit << 31; \
|
||||
} \
|
||||
SW_READ_BIT(bit); /* Read Parity */ \
|
||||
if ((parity ^ bit) & 1U) { \
|
||||
ack = DAP_TRANSFER_ERROR; \
|
||||
} \
|
||||
if (data) { *data = val; } \
|
||||
/* Turnaround */ \
|
||||
for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); \
|
||||
} \
|
||||
PIN_SWDIO_OUT_ENABLE(); \
|
||||
} else { \
|
||||
/* Turnaround */ \
|
||||
for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); \
|
||||
} \
|
||||
PIN_SWDIO_OUT_ENABLE(); \
|
||||
/* Write data */ \
|
||||
val = *data; \
|
||||
parity = 0U; \
|
||||
for (n = 32U; n; n--) { \
|
||||
SW_WRITE_BIT(val); /* Write WDATA[0:31] */ \
|
||||
parity += val; \
|
||||
val >>= 1; \
|
||||
} \
|
||||
SW_WRITE_BIT(parity); /* Write Parity Bit */ \
|
||||
} \
|
||||
/* Idle cycles */ \
|
||||
n = DAP_Data.transfer.idle_cycles; \
|
||||
if (n) { \
|
||||
PIN_SWDIO_OUT(0U); \
|
||||
for (; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); \
|
||||
} \
|
||||
} \
|
||||
PIN_SWDIO_OUT(1U); \
|
||||
return ((uint8_t)ack); \
|
||||
} \
|
||||
\
|
||||
if ((ack == DAP_TRANSFER_WAIT) || (ack == DAP_TRANSFER_FAULT)) { \
|
||||
/* WAIT or FAULT response */ \
|
||||
if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) != 0U)) { \
|
||||
for (n = 32U+1U; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); /* Dummy Read RDATA[0:31] + Parity */ \
|
||||
} \
|
||||
} \
|
||||
/* Turnaround */ \
|
||||
for (n = DAP_Data.swd_conf.turnaround; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); \
|
||||
} \
|
||||
PIN_SWDIO_OUT_ENABLE(); \
|
||||
if (DAP_Data.swd_conf.data_phase && ((request & DAP_TRANSFER_RnW) == 0U)) { \
|
||||
PIN_SWDIO_OUT(0U); \
|
||||
for (n = 32U+1U; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); /* Dummy Write WDATA[0:31] + Parity */ \
|
||||
} \
|
||||
} \
|
||||
PIN_SWDIO_OUT(1U); \
|
||||
return ((uint8_t)ack); \
|
||||
} \
|
||||
\
|
||||
/* Protocol error */ \
|
||||
for (n = DAP_Data.swd_conf.turnaround + 32U + 1U; n; n--) { \
|
||||
SW_CLOCK_CYCLE(); /* Back off data phase */ \
|
||||
} \
|
||||
PIN_SWDIO_OUT_ENABLE(); \
|
||||
PIN_SWDIO_OUT(1U); \
|
||||
return ((uint8_t)ack); \
|
||||
}
|
||||
|
||||
|
||||
#undef PIN_DELAY
|
||||
#define PIN_DELAY() PIN_DELAY_FAST()
|
||||
SWD_TransferFunction(Fast);
|
||||
|
||||
#undef PIN_DELAY
|
||||
#define PIN_DELAY() PIN_DELAY_SLOW(DAP_Data.clock_delay)
|
||||
SWD_TransferFunction(Slow);
|
||||
|
||||
|
||||
// SWD Transfer I/O
|
||||
// request: A[3:2] RnW APnDP
|
||||
// data: DATA[31:0]
|
||||
// return: ACK[2:0]
|
||||
uint8_t SWD_Transfer(uint32_t request, uint32_t *data) {
|
||||
if (DAP_Data.fast_clock) {
|
||||
return SWD_TransferFast(request, data);
|
||||
} else {
|
||||
return SWD_TransferSlow(request, data);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#endif /* (DAP_SWD != 0) */
|
||||
Reference in New Issue
Block a user