terry/ChipTest
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

添加PAN159资料

Browse Source
This commit is contained in:
SXHome
2021-09-26 17:19:12 +08:00
parent 2109411cf7
commit 7fd213ef33
3783 changed files with 1783056 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Examples/XMC4200/RTE/CMSIS/RTX_Conf_CM.c
+311
View File
@@ -0,0 +1,311 @@
/*----------------------------------------------------------------------------
* CMSIS-RTOS - RTX
*----------------------------------------------------------------------------
* Name: RTX_Conf_CM.C
* Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
* Rev.: V4.70.1
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
#include "cmsis_os.h"
/*----------------------------------------------------------------------------
* RTX User configuration part BEGIN
*---------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
//
// <h>Thread Configuration
// =======================
//
// <o>Number of concurrent running user threads <1-250>
// <i> Defines max. number of user threads that will run at the same time.
// <i> Default: 6
#ifndef OS_TASKCNT
#define OS_TASKCNT 4
#endif
// <o>Default Thread stack size [bytes] <64-4096:8><#/4>
// <i> Defines default stack size for threads with osThreadDef stacksz = 0
// <i> Default: 200
#ifndef OS_STKSIZE
#define OS_STKSIZE 64 // this stack size value is in words
#endif
// <o>Main Thread stack size [bytes] <64-32768:8><#/4>
// <i> Defines stack size for main thread.
// <i> Default: 200
#ifndef OS_MAINSTKSIZE
#define OS_MAINSTKSIZE 128 // this stack size value is in words
#endif
// <o>Number of threads with user-provided stack size <0-250>
// <i> Defines the number of threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVCNT
#define OS_PRIVCNT 3
#endif
// <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
// <i> Defines the combined stack size for threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVSTKSIZE
#define OS_PRIVSTKSIZE 384 // this stack size value is in words
#endif
// <q>Stack overflow checking
// <i> Enable stack overflow checks at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STKCHECK
#define OS_STKCHECK 1
#endif
// <q>Stack usage watermark
// <i> Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer.
// <i> Enabling this option increases significantly the execution time of osThreadCreate.
#ifndef OS_STKINIT
#define OS_STKINIT 1
#endif
// <o>Processor mode for thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_RUNPRIV
#define OS_RUNPRIV 1
#endif
// </h>
// <h>RTX Kernel Timer Tick Configuration
// ======================================
// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
// <i> Cortex-M processors provide in most cases a SysTick timer that can be used as
// <i> as time-base for RTX.
#ifndef OS_SYSTICK
#define OS_SYSTICK 1
#endif
//
// <o>RTOS Kernel Timer input clock frequency [Hz] <1-1000000000>
// <i> Defines the input frequency of the RTOS Kernel Timer.
// <i> When the Cortex-M SysTick timer is used, the input clock
// <i> is on most systems identical with the core clock.
#ifndef OS_CLOCK
#define OS_CLOCK 80000000
#endif
// <o>RTX Timer tick interval value [us] <1-1000000>
// <i> The RTX Timer tick interval value is used to calculate timeout values.
// <i> When the Cortex-M SysTick timer is enabled, the value also configures the SysTick timer.
// <i> Default: 1000 (1ms)
#ifndef OS_TICK
#define OS_TICK 1000
#endif
// </h>
// <h>System Configuration
// =======================
//
// <e>Round-Robin Thread switching
// ===============================
//
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN
#define OS_ROBIN 1
#endif
// <o>Round-Robin Timeout [ticks] <1-1000>
// <i> Defines how long a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBINTOUT
#define OS_ROBINTOUT 5
#endif
// </e>
// <e>User Timers
// ==============
// <i> Enables user Timers
#ifndef OS_TIMERS
#define OS_TIMERS 1
#endif
// <o>Timer Thread Priority
// <1=> Low
// <2=> Below Normal <3=> Normal <4=> Above Normal
// <5=> High
// <6=> Realtime (highest)
// <i> Defines priority for Timer Thread
// <i> Default: High
#ifndef OS_TIMERPRIO
#define OS_TIMERPRIO 5
#endif
// <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
// <i> Defines stack size for Timer thread.
// <i> Default: 200
#ifndef OS_TIMERSTKSZ
#define OS_TIMERSTKSZ 128 // this stack size value is in words
#endif
// <o>Timer Callback Queue size <1-32>
// <i> Number of concurrent active timer callback functions.
// <i> Default: 4
#ifndef OS_TIMERCBQS
#define OS_TIMERCBQS 4
#endif
// </e>
// <o>ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
// <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries
// <48=> 48 entries <64=> 64 entries
// <96=> 96 entries
// <i> ISR functions store requests to this buffer,
// <i> when they are called from the interrupt handler.
// <i> Default: 16 entries
#ifndef OS_FIFOSZ
#define OS_FIFOSZ 16
#endif
// </h>
//------------- <<< end of configuration section >>> -----------------------
// Standard library system mutexes
// ===============================
// Define max. number system mutexes that are used to protect
// the arm standard runtime library. For microlib they are not used.
#ifndef OS_MUTEXCNT
#define OS_MUTEXCNT 8
#endif
/*----------------------------------------------------------------------------
* RTX User configuration part END
*---------------------------------------------------------------------------*/
#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
/*----------------------------------------------------------------------------
* Global Functions
*---------------------------------------------------------------------------*/
/*--------------------------- os_idle_demon ---------------------------------*/
/// \brief The idle demon is running when no other thread is ready to run
void os_idle_demon (void) {
for (;;) {
/* HERE: include optional user code to be executed when no thread runs.*/
}
}
#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer
/*--------------------------- os_tick_init ----------------------------------*/
/// \brief Initializes an alternative hardware timer as RTX kernel timer
/// \return IRQ number of the alternative hardware timer
int os_tick_init (void) {
return (-1); /* Return IRQ number of timer (0..239) */
}
/*--------------------------- os_tick_val -----------------------------------*/
/// \brief Get alternative hardware timer's current value (0 .. OS_TRV)
/// \return Current value of the alternative hardware timer
uint32_t os_tick_val (void) {
return (0);
}
/*--------------------------- os_tick_ovf -----------------------------------*/
/// \brief Get alternative hardware timer's overflow flag
/// \return Overflow flag\n
/// - 1 : overflow
/// - 0 : no overflow
uint32_t os_tick_ovf (void) {
return (0);
}
/*--------------------------- os_tick_irqack --------------------------------*/
/// \brief Acknowledge alternative hardware timer interrupt
void os_tick_irqack (void) {
/* ... */
}
#endif // (OS_SYSTICK == 0)
/*--------------------------- os_error --------------------------------------*/
/* OS Error Codes */
#define OS_ERROR_STACK_OVF 1
#define OS_ERROR_FIFO_OVF 2
#define OS_ERROR_MBX_OVF 3
#define OS_ERROR_TIMER_OVF 4
extern osThreadId svcThreadGetId (void);
/// \brief Called when a runtime error is detected
/// \param[in] error_code actual error code that has been detected
void os_error (uint32_t error_code) {
/* HERE: include optional code to be executed on runtime error. */
switch (error_code) {
case OS_ERROR_STACK_OVF:
/* Stack overflow detected for the currently running task. */
/* Thread can be identified by calling svcThreadGetId(). */
break;
case OS_ERROR_FIFO_OVF:
/* ISR FIFO Queue buffer overflow detected. */
break;
case OS_ERROR_MBX_OVF:
/* Mailbox overflow detected. */
break;
case OS_ERROR_TIMER_OVF:
/* User Timer Callback Queue overflow detected. */
break;
}
for (;;);
}
/*----------------------------------------------------------------------------
* RTX Configuration Functions
*---------------------------------------------------------------------------*/
#include "RTX_CM_lib.h"
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Examples/XMC4200/RTE/Device/XMC4200-Q48x256/RTE_Device.h
+897
View File
@@ -0,0 +1,897 @@
/*
*
* Copyright (c) 2015, Infineon Technologies AG
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,are permitted provided that the
* following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this list of conditions and the following
* disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided with the distribution.
*
* Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote
* products derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY,OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* To improve the quality of the software, users are encouraged to share modifications, enhancements or bug fixes with
* Infineon Technologies AG [email protected]).
*
*/
/**
* @file RTE_Device.h
* @date 24 July, 2015
* @version 1.0.1
*
* @brief RTE Device Configuration for Infineon XMC4200_Q48
*
* History
*
* Version 1.0.1
* Fix pin assignment
* Version 1.0.0
* Initial version
*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
#ifndef __RTE_DEVICE_H
#define __RTE_DEVICE_H
#include "xmc_device.h"
#include "xmc4_gpio_map.h"
#include "xmc4_usic_map.h"
#define NO_FIFO 0
#define FIFO_SIZE_2 1
#define FIFO_SIZE_4 2
#define FIFO_SIZE_8 3
#define FIFO_SIZE_16 4
#define FIFO_SIZE_32 5
#define FIFO_SIZE_64 6
// <e> UART0 (Universal asynchronous receiver transmitter) [Driver_USART0]
// <i> Configuration settings for Driver_USART0 in component ::Drivers:UART
#define RTE_UART0 0
// <o> UART0_TX Pin <0=>P1_5
#define RTE_UART0_TX_ID 0
#if (RTE_UART0_TX_ID == 0)
#define RTE_UART0_TX_PORT P1_5
#define RTE_UART0_TX_AF P1_5_AF_U0C0_DOUT0
#else
#error "Invalid UART0_TX Pin Configuration!"
#endif
// <o> UART0_RX Pin <0=>P1_5 <1=>P1_4
#define RTE_UART0_RX_ID 1
#if (RTE_UART0_RX_ID == 0)
#define RTE_UART0_RX_PORT P1_5
#define RTE_UART0_RX_INPUT USIC0_C0_DX0_P1_5
#elif (RTE_UART0_RX_ID == 1)
#define RTE_UART0_RX_PORT P1_4
#define RTE_UART0_RX_INPUT USIC0_C0_DX0_P1_4
#else
#error "Invalid UART0_RX Pin Configuration!"
#endif
// <o> UART0_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_UART0_RX_FIFO_SIZE_ID 5
#if (RTE_UART0_RX_FIFO_SIZE_ID == 0)
#define RTE_UART0_RX_FIFO_SIZE NO_FIFO
#define RTE_UART0_RX_FIFO_SIZE_NUM 0
#elif (RTE_UART0_RX_FIFO_SIZE_ID == 1)
#define RTE_UART0_RX_FIFO_SIZE FIFO_SIZE_2
#define RTE_UART0_RX_FIFO_SIZE_NUM 2
#elif (RTE_UART0_RX_FIFO_SIZE_ID == 2)
#define RTE_UART0_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART0_RX_FIFO_SIZE_NUM 4
#elif (RTE_UART0_RX_FIFO_SIZE_ID == 3)
#define RTE_UART0_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART0_RX_FIFO_SIZE_NUM 4
#elif (RTE_UART0_RX_FIFO_SIZE_ID == 4)
#define RTE_UART0_RX_FIFO_SIZE FIFO_SIZE_16
#define RTE_UART0_RX_FIFO_SIZE_NUM 16
#elif (RTE_UART0_RX_FIFO_SIZE_ID == 5)
#define RTE_UART0_RX_FIFO_SIZE FIFO_SIZE_32
#define RTE_UART0_RX_FIFO_SIZE_NUM 32
#elif (RTE_UART0_RX_FIFO_SIZE_ID == 6)
#define RTE_UART0_RX_FIFO_SIZE FIFO_SIZE_64
#define RTE_UART0_RX_FIFO_SIZE_NUM 64
#else
#error "Invalid UART0_RX FIFO SIZE Configuration!"
#endif
// <o> UART0_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_UART0_TX_FIFO_SIZE_ID 5
#if (RTE_UART0_TX_FIFO_SIZE_ID == 0)
#define RTE_UART0_TX_FIFO_SIZE NO_FIFO
#define RTE_UART0_TX_FIFO_SIZE_NUM 0
#elif (RTE_UART0_TX_FIFO_SIZE_ID == 1)
#define RTE_UART0_TX_FIFO_SIZE FIFO_SIZE_2
#define RTE_UART0_TX_FIFO_SIZE_NUM 2
#elif (RTE_UART0_TX_FIFO_SIZE_ID == 2)
#define RTE_UART0_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART0_TX_FIFO_SIZE_NUM 4
#elif (RTE_UART0_TX_FIFO_SIZE_ID == 3)
#define RTE_UART0_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART0_TX_FIFO_SIZE_NUM 4
#elif (RTE_UART0_TX_FIFO_SIZE_ID == 4)
#define RTE_UART0_TX_FIFO_SIZE FIFO_SIZE_16
#define RTE_UART0_TX_FIFO_SIZE_NUM 16
#elif (RTE_UART0_TX_FIFO_SIZE_ID == 5)
#define RTE_UART0_TX_FIFO_SIZE FIFO_SIZE_32
#define RTE_UART0_TX_FIFO_SIZE_NUM 32
#elif (RTE_UART0_TX_FIFO_SIZE_ID == 6)
#define RTE_UART0_TX_FIFO_SIZE FIFO_SIZE_64
#define RTE_UART0_TX_FIFO_SIZE_NUM 64
#else
#error "Invalid UART0_TX FIFO SIZE Configuration!"
#endif
//</e>
// <e> UART1 (Universal asynchronous receiver transmitter) [Driver_USART1]
// <i> Configuration settings for Driver_USART1 in component ::Drivers:UART
#define RTE_UART1 0
// <o> UART1_TX Pin <0=>P2_5
#define RTE_UART1_TX_ID 0
#if (RTE_UART1_TX_ID == 0)
#define RTE_UART1_TX_PORT P2_5
#define RTE_UART1_TX_AF P2_5_AF_U0C1_DOUT0
#else
#error "Invalid UART1_TX Pin Configuration!"
#endif
// <o> UART1_RX Pin <0=>P2_2 <1=>P2_5
#define RTE_UART1_RX_ID 1
#if (RTE_UART1_RX_ID == 0)
#define RTE_UART1_RX_PORT P2_2
#define RTE_UART1_RX_INPUT USIC0_C1_DX0_P2_2
#elif (RTE_UART1_RX_ID == 1)
#define RTE_UART1_RX_PORT P2_5
#define RTE_UART1_RX_INPUT USIC0_C1_DX0_P2_5
#else
#error "Invalid UART1_RX Pin Configuration!"
#endif
// <o> UART1_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_UART1_RX_FIFO_SIZE_ID 2
#if (RTE_UART1_RX_FIFO_SIZE_ID == 0)
#define RTE_UART1_RX_FIFO_SIZE NO_FIFO
#define RTE_UART1_RX_FIFO_SIZE_NUM 0
#elif (RTE_UART1_RX_FIFO_SIZE_ID == 1)
#define RTE_UART1_RX_FIFO_SIZE FIFO_SIZE_2
#define RTE_UART1_RX_FIFO_SIZE_NUM 2
#elif (RTE_UART1_RX_FIFO_SIZE_ID == 2)
#define RTE_UART1_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART1_RX_FIFO_SIZE_NUM 4
#elif (RTE_UART1_RX_FIFO_SIZE_ID == 3)
#define RTE_UART1_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART1_RX_FIFO_SIZE_NUM 4
#elif (RTE_UART1_RX_FIFO_SIZE_ID == 4)
#define RTE_UART1_RX_FIFO_SIZE FIFO_SIZE_16
#define RTE_UART1_RX_FIFO_SIZE_NUM 16
#elif (RTE_UART1_RX_FIFO_SIZE_ID == 5)
#define RTE_UART1_RX_FIFO_SIZE FIFO_SIZE_32
#define RTE_UART1_RX_FIFO_SIZE_NUM 32
#elif (RTE_UART1_RX_FIFO_SIZE_ID == 6)
#define RTE_UART1_RX_FIFO_SIZE FIFO_SIZE_64
#define RTE_UART1_RX_FIFO_SIZE_NUM 64
#else
#error "Invalid UART1_RX FIFO SIZE Configuration!"
#endif
// <o> UART1_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_UART1_TX_FIFO_SIZE_ID 2
#if (RTE_UART1_TX_FIFO_SIZE_ID == 0)
#define RTE_UART1_TX_FIFO_SIZE NO_FIFO
#define RTE_UART1_TX_FIFO_SIZE_NUM 0
#elif (RTE_UART1_TX_FIFO_SIZE_ID == 1)
#define RTE_UART1_TX_FIFO_SIZE FIFO_SIZE_2
#define RTE_UART1_TX_FIFO_SIZE_NUM 2
#elif (RTE_UART1_TX_FIFO_SIZE_ID == 2)
#define RTE_UART1_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART1_TX_FIFO_SIZE_NUM 4
#elif (RTE_UART1_TX_FIFO_SIZE_ID == 3)
#define RTE_UART1_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART1_TX_FIFO_SIZE_NUM 4
#elif (RTE_UART1_TX_FIFO_SIZE_ID == 4)
#define RTE_UART1_TX_FIFO_SIZE FIFO_SIZE_16
#define RTE_UART1_TX_FIFO_SIZE_NUM 16
#elif (RTE_UART1_TX_FIFO_SIZE_ID == 5)
#define RTE_UART1_TX_FIFO_SIZE FIFO_SIZE_32
#define RTE_UART1_TX_FIFO_SIZE_NUM 32
#elif (RTE_UART1_TX_FIFO_SIZE_ID == 6)
#define RTE_UART1_TX_FIFO_SIZE FIFO_SIZE_64
#define RTE_UART1_TX_FIFO_SIZE_NUM 64
#else
#error "Invalid UART1_TX FIFO SIZE Configuration!"
#endif
//</e>
// <e> UART2 (Universal asynchronous receiver transmitter) [Driver_USART2]
// <i> Configuration settings for Driver_USART2 in component ::Drivers:UART
#define RTE_UART2 1
// <o> UART2_TX Pin <0=>P0_5
#define RTE_UART2_TX_ID 0
#if (RTE_UART2_TX_ID == 0)
#define RTE_UART2_TX_PORT P0_5
#define RTE_UART2_TX_AF P0_5_AF_U1C0_DOUT0
#else
#error "Invalid UART2_TX Pin Configuration!"
#endif
// <o> UART2_RX Pin <0=> P0_4 <1=> P0_5
#define RTE_UART2_RX_ID 0
#if (RTE_UART2_RX_ID == 0)
#define RTE_UART2_RX_PORT P0_4
#define RTE_UART2_RX_INPUT USIC1_C0_DX0_P0_4
#elif (RTE_UART2_RX_ID == 1)
#define RTE_UART2_RX_PORT P0_5
#define RTE_UART2_RX_INPUT USIC1_C0_DX0_P0_5
#else
#error "Invalid UART2_RX Pin Configuration!"
#endif
// <o> UART2_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_UART2_RX_FIFO_SIZE_ID 0
#if (RTE_UART2_RX_FIFO_SIZE_ID == 0)
#define RTE_UART2_RX_FIFO_SIZE NO_FIFO
#define RTE_UART2_RX_FIFO_SIZE_NUM 0
#elif (RTE_UART2_RX_FIFO_SIZE_ID == 1)
#define RTE_UART2_RX_FIFO_SIZE FIFO_SIZE_2
#define RTE_UART2_RX_FIFO_SIZE_NUM 2
#elif (RTE_UART2_RX_FIFO_SIZE_ID == 2)
#define RTE_UART2_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART2_RX_FIFO_SIZE_NUM 4
#elif (RTE_UART2_RX_FIFO_SIZE_ID == 3)
#define RTE_UART2_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART2_RX_FIFO_SIZE_NUM 4
#elif (RTE_UART2_RX_FIFO_SIZE_ID == 4)
#define RTE_UART2_RX_FIFO_SIZE FIFO_SIZE_16
#define RTE_UART2_RX_FIFO_SIZE_NUM 16
#elif (RTE_UART2_RX_FIFO_SIZE_ID == 5)
#define RTE_UART2_RX_FIFO_SIZE FIFO_SIZE_32
#define RTE_UART2_RX_FIFO_SIZE_NUM 32
#elif (RTE_UART2_RX_FIFO_SIZE_ID == 6)
#define RTE_UART2_RX_FIFO_SIZE FIFO_SIZE_64
#define RTE_UART2_RX_FIFO_SIZE_NUM 64
#else
#error "Invalid UART2_RX FIFO SIZE Configuration!"
#endif
// <o> UART2_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_UART2_TX_FIFO_SIZE_ID 0
#if (RTE_UART2_TX_FIFO_SIZE_ID == 0)
#define RTE_UART2_TX_FIFO_SIZE NO_FIFO
#define RTE_UART2_TX_FIFO_SIZE_NUM 0
#elif (RTE_UART2_TX_FIFO_SIZE_ID == 1)
#define RTE_UART2_TX_FIFO_SIZE FIFO_SIZE_2
#define RTE_UART2_TX_FIFO_SIZE_NUM 2
#elif (RTE_UART2_TX_FIFO_SIZE_ID == 2)
#define RTE_UART2_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART2_TX_FIFO_SIZE_NUM 4
#elif (RTE_UART2_TX_FIFO_SIZE_ID == 3)
#define RTE_UART2_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART2_TX_FIFO_SIZE_NUM 4
#elif (RTE_UART2_TX_FIFO_SIZE_ID == 4)
#define RTE_UART2_TX_FIFO_SIZE FIFO_SIZE_16
#define RTE_UART2_TX_FIFO_SIZE_NUM 16
#elif (RTE_UART2_TX_FIFO_SIZE_ID == 5)
#define RTE_UART2_TX_FIFO_SIZE FIFO_SIZE_32
#define RTE_UART2_TX_FIFO_SIZE_NUM 32
#elif (RTE_UART2_TX_FIFO_SIZE_ID == 6)
#define RTE_UART2_TX_FIFO_SIZE FIFO_SIZE_64
#define RTE_UART2_TX_FIFO_SIZE_NUM 64
#else
#error "Invalid UART2_TX FIFO SIZE Configuration!"
#endif
//</e>
// <e> UART3 (Universal asynchronous receiver transmitter) [Driver_USART3]
// <i> Configuration settings for Driver_USART3 in component ::Drivers:UART
#define RTE_UART3 0
// <o> UART3_TX Pin <0=>P0_1
#define RTE_UART3_TX_ID 0
#if (RTE_UART3_TX_ID == 0)
#define RTE_UART3_TX_PORT P0_1
#define RTE_UART3_TX_AF P0_1_AF_U1C1_DOUT0
#else
#error "Invalid UART3_TX Pin Configuration!"
#endif
// <o> UART3_RX Pin <0=>P0_1
#define RTE_UART3_RX_ID 0
#if (RTE_UART3_RX_ID == 0)
#define RTE_UART3_RX_PORT P0_0
#define RTE_UART3_RX_INPUT USIC1_C1_DX0_P0_0
#else
#error "Invalid UART3_RX Pin Configuration!"
#endif
// <o> UART3_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_UART3_RX_FIFO_SIZE_ID 2
#if (RTE_UART3_RX_FIFO_SIZE_ID == 0)
#define RTE_UART3_RX_FIFO_SIZE NO_FIFO
#define RTE_UART3_RX_FIFO_SIZE_NUM 0
#elif (RTE_UART3_RX_FIFO_SIZE_ID == 1)
#define RTE_UART3_RX_FIFO_SIZE FIFO_SIZE_2
#define RTE_UART3_RX_FIFO_SIZE_NUM 2
#elif (RTE_UART3_RX_FIFO_SIZE_ID == 2)
#define RTE_UART3_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART3_RX_FIFO_SIZE_NUM 4
#elif (RTE_UART3_RX_FIFO_SIZE_ID == 3)
#define RTE_UART3_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART3_RX_FIFO_SIZE_NUM 4
#elif (RTE_UART3_RX_FIFO_SIZE_ID == 4)
#define RTE_UART3_RX_FIFO_SIZE FIFO_SIZE_16
#define RTE_UART3_RX_FIFO_SIZE_NUM 16
#elif (RTE_UART3_RX_FIFO_SIZE_ID == 5)
#define RTE_UART3_RX_FIFO_SIZE FIFO_SIZE_32
#define RTE_UART3_RX_FIFO_SIZE_NUM 32
#elif (RTE_UART3_RX_FIFO_SIZE_ID == 6)
#define RTE_UART3_RX_FIFO_SIZE FIFO_SIZE_64
#define RTE_UART3_RX_FIFO_SIZE_NUM 64
#else
#error "Invalid UART3_RX FIFO SIZE Configuration!"
#endif
// <o> UART3_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_UART3_TX_FIFO_SIZE_ID 2
#if (RTE_UART3_TX_FIFO_SIZE_ID == 0)
#define RTE_UART3_TX_FIFO_SIZE NO_FIFO
#define RTE_UART3_TX_FIFO_SIZE_NUM 0
#elif (RTE_UART3_TX_FIFO_SIZE_ID == 1)
#define RTE_UART3_TX_FIFO_SIZE FIFO_SIZE_2
#define RTE_UART3_TX_FIFO_SIZE_NUM 2
#elif (RTE_UART3_TX_FIFO_SIZE_ID == 2)
#define RTE_UART3_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART3_TX_FIFO_SIZE_NUM 4
#elif (RTE_UART3_TX_FIFO_SIZE_ID == 3)
#define RTE_UART3_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_UART3_TX_FIFO_SIZE_NUM 4
#elif (RTE_UART3_TX_FIFO_SIZE_ID == 4)
#define RTE_UART3_TX_FIFO_SIZE FIFO_SIZE_16
#define RTE_UART3_TX_FIFO_SIZE_NUM 16
#elif (RTE_UART3_TX_FIFO_SIZE_ID == 5)
#define RTE_UART3_TX_FIFO_SIZE FIFO_SIZE_32
#define RTE_UART3_TX_FIFO_SIZE_NUM 32
#elif (RTE_UART3_TX_FIFO_SIZE_ID == 6)
#define RTE_UART3_TX_FIFO_SIZE FIFO_SIZE_64
#define RTE_UART3_TX_FIFO_SIZE_NUM 64
#else
#error "Invalid UART3_TX FIFO SIZE Configuration!"
#endif
// </e>
// <e> SPI0 (Serial peripheral interface) [Driver_SPI0]
// <i> Configuration settings for Driver_SPI0 in component ::Drivers:SPI
#define RTE_SPI0 0
// <o> SPI0 TX: MOSI(master) MISO(slave) Pin <0=>P1_5
#define RTE_SPI0_TX_ID 0
#if (RTE_SPI0_TX_ID == 0)
#define RTE_SPI0_TX_PORT P1_5
#define RTE_SPI0_TX_AF P1_5_AF_U0C0_DOUT0
#else
#error "Invalid SPI0_TX Pin Configuration!"
#endif
// <o> SPI0 RX MISO(master) MOSI(slave) Pin <0=>P1_5
#define RTE_SPI0_RX_ID 0
#if (RTE_SPI0_RX_ID == 0)
#define RTE_SPI0_RX_PORT P1_5
#define RTE_SPI0_RX_INPUT USIC0_C0_DX0_P1_5
#else
#error "Invalid SPI0_RX Pin Configuration!"
#endif
// <o> SPI0_CLK OUTPUT Pin <0=>P0_8 <1=>P1_1
#define RTE_SPI0_CLK_OUTPUT_ID 0
#if (RTE_SPI0_CLK_OUTPUT_ID == 0)
#define RTE_SPI0_CLK_OUTPUT_PORT P0_8
#define RTE_SPI0_CLK_AF P0_8_AF_U0C0_SCLKOUT
#elif (RTE_SPI0_CLK_OUTPUT_ID == 1)
#define RTE_SPI0_CLK_OUTPUT_PORT P1_1
#define RTE_SPI0_CLK_AF P1_1_AF_U0C0_SCLKOUT
#else
#error "Invalid SPI0 CLOCK OUTPUT Pin Configuration!"
#endif
// <h> SPI0_SLAVE SELECT Pins
// <e> SLAVE SELECT LINE 0
// <i> Enable slave select line 0
#define RTE_SPI0_SLAVE_SELECT_LINE0 1
// <o> SPI0_SLAVE SELECT LINE 0 Pin <0=>P0_7 <1=>P1_0
#define RTE_SPI0_SLAVE_SELECT_LINE_0_ID 1
#if (RTE_SPI0_SLAVE_SELECT_LINE_0_ID == 0)
#define RTE_SPI0_SLAVE_SELECT_LINE_0_PORT P0_7
#define RTE_SPI0_SLAVE_SELECT_LINE_0_AF P0_7_AF_U0C0_SELO0
#elif (RTE_SPI0_SLAVE_SELECT_LINE_0_ID == 1)
#define RTE_SPI0_SLAVE_SELECT_LINE_0_PORT P1_0
#define RTE_SPI0_SLAVE_SELECT_LINE_0_AF P1_0_AF_U0C0_SELO0
#else
#error "Invalid SPI0 SLAVE SELECT LINE 0 Pin Configuration!"
#endif
// </e>
// <e> SLAVE SELECT LINE 1
// <i> Enable slave select line 1
#define RTE_SPI0_SLAVE_SELECT_LINE1 1
// <o> SPI0_SLAVE SELECT LINE 1 Pin <0=>P1_8
#define RTE_SPI0_SLAVE_SELECT_LINE_1_ID 0
#if (RTE_SPI0_SLAVE_SELECT_LINE_1_ID == 0)
#define RTE_SPI0_SLAVE_SELECT_LINE_1_PORT P1_8
#define RTE_SPI0_SLAVE_SELECT_LINE_1_AF P1_8_AF_U0C0_SELO1
#else
#error "Invalid SPI0 SLAVE SELECT LINE 1 Pin Configuration!"
#endif
// </e>
// <e> SLAVE SELECT LINE 2
// <i> Enable slave select line 2
#define RTE_SPI0_SLAVE_SELECT_LINE2 0
#if (RTE_SPI0_SLAVE_SELECT_LINE2 == 1)
#error "Invalid SPI0 SLAVE SELECT LINE 2 Pin Configuration!"
#endif
//</e>
// <e> SLAVE SELECT LINE 3
// <i> Enable slave select line 3
#define RTE_SPI0_SLAVE_SELECT_LINE3 0
#if (RTE_SPI0_SLAVE_SELECT_LINE3 == 1)
#error "Invalid SPI0 SLAVE SELECT LINE 3 Pin Configuration!"
#endif
//</e>
// <e> SLAVE SELECT LINE 4
// <i> Enable slave select line 4
#define RTE_SPI0_SLAVE_SELECT_LINE4 0
#if (RTE_SPI0_SLAVE_SELECT_LINE4 == 1)
#error "Invalid SPI0 SLAVE SELECT LINE 4 Pin Configuration!"
#endif
//</e>
// <e> SLAVE SELECT LINE 5
// <i> Enable slave select line 5
#define RTE_SPI0_SLAVE_SELECT_LINE5 0
#if (RTE_SPI0_SLAVE_SELECT_LINE5 == 1)
#error "Invalid SPI0 SLAVE SELECT LINE 5 Pin Configuration!"
#endif
//</e>
// </h>
// <o> SPI0_CLK INPUT Pin <0=>P1_1 <1=>P0_8
#define RTE_SPI0_CLK_INPUT_ID 0
#if (RTE_SPI0_CLK_INPUT_ID == 0)
#define RTE_SPI0_CLK_INPUT_PORT P1_1
#define RTE_SPI0_CLK_INPUT USIC0_C0_DX1_P1_1
#elif (RTE_SPI0_CLK_INPUT_ID == 1)
#define RTE_SPI0_CLK_INPUT_PORT P0_8
#define RTE_SPI0_CLK_INPUT USIC0_C0_DX1_P0_8
#else
#error "Invalid SPI0 CLOCK INPUT Pin Configuration!"
#endif
// <o> RTE_SPI0_SLAVE_SELECT INPUT Pin <0=>P1_0
#define RTE_SPI0_SLAVE_SELECT_INPUT_ID 0
#if (RTE_SPI0_SLAVE_SELECT_INPUT_ID == 0)
#define RTE_SPI0_SLAVE_SELECT_INPUT_PORT P1_0
#define RTE_SPI0_SLAVE_SELECT_INPUT USIC0_C0_DX2_P1_0
#else
#error "Invalid SPI0 SLAVE SELECT INPUT Pin Configuration!"
#endif
// <o> SPI0_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_SPI0_RX_FIFO_SIZE_ID 2
#if (RTE_SPI0_RX_FIFO_SIZE_ID == 0)
#define RTE_SPI0_RX_FIFO_SIZE NO_FIFO
#define RTE_SPI0_RX_FIFO_SIZE_NUM 0
#elif (RTE_SPI0_RX_FIFO_SIZE_ID == 1)
#define RTE_SPI0_RX_FIFO_SIZE FIFO_SIZE_2
#define RTE_SPI0_RX_FIFO_SIZE_NUM 2
#elif (RTE_SPI0_RX_FIFO_SIZE_ID == 2)
#define RTE_SPI0_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_SPI0_RX_FIFO_SIZE_NUM 4
#elif (RTE_SPI0_RX_FIFO_SIZE_ID == 3)
#define RTE_SPI0_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_SPI0_RX_FIFO_SIZE_NUM 4
#elif (RTE_SPI0_RX_FIFO_SIZE_ID == 4)
#define RTE_SPI0_RX_FIFO_SIZE FIFO_SIZE_16
#define RTE_SPI0_RX_FIFO_SIZE_NUM 16
#elif (RTE_SPI0_RX_FIFO_SIZE_ID == 5)
#define RTE_SPI0_RX_FIFO_SIZE FIFO_SIZE_32
#define RTE_SPI0_RX_FIFO_SIZE_NUM 32
#elif (RTE_SPI0_RX_FIFO_SIZE_ID == 6)
#define RTE_SPI0_RX_FIFO_SIZE FIFO_SIZE_64
#define RTE_SPI0_RX_FIFO_SIZE_NUM 64
#else
#error "Invalid SPI0_RX FIFO SIZE Configuration!"
#endif
// <o> SPI0_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_SPI0_TX_FIFO_SIZE_ID 4
#if (RTE_SPI0_TX_FIFO_SIZE_ID == 0)
#define RTE_SPI0_TX_FIFO_SIZE NO_FIFO
#define RTE_SPI0_TX_FIFO_SIZE_NUM 0
#elif (RTE_SPI0_TX_FIFO_SIZE_ID == 1)
#define RTE_SPI0_TX_FIFO_SIZE FIFO_SIZE_2
#define RTE_SPI0_TX_FIFO_SIZE_NUM 2
#elif (RTE_SPI0_TX_FIFO_SIZE_ID == 2)
#define RTE_SPI0_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_SPI0_TX_FIFO_SIZE_NUM 4
#elif (RTE_SPI0_TX_FIFO_SIZE_ID == 3)
#define RTE_SPI0_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_SPI0_TX_FIFO_SIZE_NUM 4
#elif (RTE_SPI0_TX_FIFO_SIZE_ID == 4)
#define RTE_SPI0_TX_FIFO_SIZE FIFO_SIZE_16
#define RTE_SPI0_TX_FIFO_SIZE_NUM 16
#elif (RTE_SPI0_TX_FIFO_SIZE_ID == 5)
#define RTE_SPI0_TX_FIFO_SIZE FIFO_SIZE_32
#define RTE_SPI0_TX_FIFO_SIZE_NUM 32
#elif (RTE_SPI0_TX_FIFO_SIZE_ID == 6)
#define RTE_SPI0_TX_FIFO_SIZE FIFO_SIZE_64
#define RTE_SPI0_TX_FIFO_SIZE_NUM 64
#else
#error "Invalid SPI0_TX FIFO SIZE Configuration!"
#endif
//</e>
// <e> SPI1 (Serial peripheral interface) [Driver_SPI1]
// <i> Configuration settings for Driver_SPI1 in component ::Drivers:SPI
#define RTE_SPI1 0
// <o> SPI1 TX MOSI(master) MISO(slave) Pin <0=>P2_5
#define RTE_SPI1_TX_ID 0
#if (RTE_SPI1_TX_ID == 0)
#define RTE_SPI1_TX_PORT P2_5
#define RTE_SPI1_TX_AF P2_5_AF_U0C1_DOUT0
#else
#error "Invalid SPI1_TX Pin Configuration!"
#endif
// <o> SPI1 RX MISO(master) MOSI(slave) Pin <0=>P2_2 <1=>P2_5
#define RTE_SPI1_RX_ID 1
#if (RTE_SPI1_RX_ID == 0)
#define RTE_SPI1_RX_PORT P2_2
#define RTE_SPI1_RX_INPUT USIC0_C1_DX0_P2_2
#elif (RTE_SPI1_RX_ID == 1)
#define RTE_SPI1_RX_PORT P2_5
#define RTE_SPI1_RX_INPUT USIC0_C1_DX0_P2_5
#else
#error "Invalid SPI1_RX Pin Configuration!"
#endif
// <o> SPI1_CLK OUTPUT Pin <0=>P2_4
#define RTE_SPI1_CLK_OUTPUT_ID 0
#if (RTE_SPI1_CLK_OUTPUT_ID == 0)
#define RTE_SPI1_CLK_OUTPUT_PORT P2_4
#define RTE_SPI1_CLK_AF P2_4_AF_U0C1_SCLKOUT
#else
#error "Invalid SPI1 CLOCK OUTPUT Pin Configuration!"
#endif
// <h> SPI1_SLAVE SELECT Pins
// <e> SLAVE SELECT LINE 0
// <i> Enable slave select line 0
#define RTE_SPI1_SLAVE_SELECT_LINE0 1
// <o> SPI1_SLAVE SELECT LINE 0 Pin <0=>P2_3
#define RTE_SPI1_SLAVE_SELECT_LINE_0_ID 0
#if (RTE_SPI1_SLAVE_SELECT_LINE_0_ID == 0)
#define RTE_SPI1_SLAVE_SELECT_LINE_0_PORT P2_3
#define RTE_SPI1_SLAVE_SELECT_LINE_0_AF P2_3_AF_U0C1_SELO0
#else
#error "Invalid SPI1 SLAVE SELECT LINE 0 Pin Configuration!"
#endif
// </e>
// <e> SLAVE SELECT LINE 1
// <i> Enable slave select line 1
#define RTE_SPI1_SLAVE_SELECT_LINE1 0
#if (RTE_SPI1_SLAVE_SELECT_LINE1 == 1)
#error "Invalid SPI1 SLAVE SELECT LINE 1 Pin Configuration!"
#endif
//</e>
// <e> SLAVE SELECT LINE 2
// <i> Enable slave select line 2
#define RTE_SPI1_SLAVE_SELECT_LINE2 0
#if (RTE_SPI1_SLAVE_SELECT_LINE2 == 1)
#error "Invalid SPI1 SLAVE SELECT LINE 2 Pin Configuration!"
#endif
//</e>
// <e> SLAVE SELECT LINE 3
// <i> Enable slave select line 3
#define RTE_SPI1_SLAVE_SELECT_LINE3 0
#if (RTE_SPI1_SLAVE_SELECT_LINE3 == 1)
#error "Invalid SPI1 SLAVE SELECT LINE 3 Pin Configuration!"
#endif
//</e>
// </h>
// <o> SPI1_CLK INPUT Pin <0=>P2_4
#define RTE_SPI1_CLK_INPUT_ID 0
#if (RTE_SPI1_CLK_INPUT_ID == 0)
#define RTE_SPI1_CLK_INPUT_PORT P2_4
#define RTE_SPI1_CLK_INPUT USIC0_C1_DX1_P2_4
#else
#error "Invalid SPI1 CLOCK INPUT Pin Configuration!"
#endif
// <o> RTE_SPI1_SLAVE_SELECT INPUT Pin <0=>P2_3
#define RTE_SPI1_SLAVE_SELECT_INPUT_ID 0
#if (RTE_SPI1_SLAVE_SELECT_INPUT_ID == 0)
#define RTE_SPI1_SLAVE_SELECT_INPUT_PORT P2_3
#define RTE_SPI1_SLAVE_SELECT_INPUT USIC0_C1_DX2_P2_3
#else
#error "Invalid SPI1 SLAVE SELECT INPUT Pin Configuration!"
#endif
// <o> SPI1_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_SPI1_RX_FIFO_SIZE_ID 2
#if (RTE_SPI1_RX_FIFO_SIZE_ID == 0)
#define RTE_SPI1_RX_FIFO_SIZE NO_FIFO
#define RTE_SPI1_RX_FIFO_SIZE_NUM 0
#elif (RTE_SPI1_RX_FIFO_SIZE_ID == 1)
#define RTE_SPI1_RX_FIFO_SIZE FIFO_SIZE_2
#define RTE_SPI1_RX_FIFO_SIZE_NUM 2
#elif (RTE_SPI1_RX_FIFO_SIZE_ID == 2)
#define RTE_SPI1_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_SPI1_RX_FIFO_SIZE_NUM 4
#elif (RTE_SPI1_RX_FIFO_SIZE_ID == 3)
#define RTE_SPI1_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_SPI1_RX_FIFO_SIZE_NUM 4
#elif (RTE_SPI1_RX_FIFO_SIZE_ID == 4)
#define RTE_SPI1_RX_FIFO_SIZE FIFO_SIZE_16
#define RTE_SPI1_RX_FIFO_SIZE_NUM 16
#elif (RTE_SPI1_RX_FIFO_SIZE_ID == 5)
#define RTE_SPI1_RX_FIFO_SIZE FIFO_SIZE_32
#define RTE_SPI1_RX_FIFO_SIZE_NUM 32
#elif (RTE_SPI1_RX_FIFO_SIZE_ID == 6)
#define RTE_SPI1_RX_FIFO_SIZE FIFO_SIZE_64
#define RTE_SPI1_RX_FIFO_SIZE_NUM 64
#else
#error "Invalid SPI1_RX FIFO SIZE Configuration!"
#endif
// <o> SPI1_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_SPI1_TX_FIFO_SIZE_ID 2
#if (RTE_SPI1_TX_FIFO_SIZE_ID == 0)
#define RTE_SPI1_TX_FIFO_SIZE NO_FIFO
#define RTE_SPI1_TX_FIFO_SIZE_NUM 0
#elif (RTE_SPI1_TX_FIFO_SIZE_ID == 1)
#define RTE_SPI1_TX_FIFO_SIZE FIFO_SIZE_2
#define RTE_SPI1_TX_FIFO_SIZE_NUM 2
#elif (RTE_SPI1_TX_FIFO_SIZE_ID == 2)
#define RTE_SPI1_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_SPI1_TX_FIFO_SIZE_NUM 4
#elif (RTE_SPI1_TX_FIFO_SIZE_ID == 3)
#define RTE_SPI1_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_SPI1_TX_FIFO_SIZE_NUM 4
#elif (RTE_SPI1_TX_FIFO_SIZE_ID == 4)
#define RTE_SPI1_TX_FIFO_SIZE FIFO_SIZE_16
#define RTE_SPI1_TX_FIFO_SIZE_NUM 16
#elif (RTE_SPI1_TX_FIFO_SIZE_ID == 5)
#define RTE_SPI1_TX_FIFO_SIZE FIFO_SIZE_32
#define RTE_SPI1_TX_FIFO_SIZE_NUM 32
#elif (RTE_SPI1_TX_FIFO_SIZE_ID == 6)
#define RTE_SPI1_TX_FIFO_SIZE FIFO_SIZE_64
#define RTE_SPI1_TX_FIFO_SIZE_NUM 64
#else
#error "Invalid SPI1_TX FIFO SIZE Configuration!"
#endif
//</e>
// <e> I2C0 (Inter-Integrated circuit) [Driver_I2C0]
// <i> Configuration settings for Driver_I2C0 in component ::Drivers:I2C
#define RTE_I2C0 0
// <o> I2C0_TX Pin <0=>P1_5
#define RTE_I2C0_TX_ID 0
#if (RTE_I2C0_TX_ID == 0)
#define RTE_I2C0_TX_PORT P1_5
#define RTE_I2C0_TX_AF P1_5_AF_U0C0_DOUT0
#else
#error "Invalid I2C0_TX Pin Configuration!"
#endif
// <o> I2C0_RX Pin <0=>P1_5
#define RTE_I2C0_RX_ID 0
#if (RTE_I2C0_RX_ID == 0)
#define RTE_I2C0_RX_PORT P1_5
#define RTE_I2C0_RX_INPUT USIC0_C0_DX0_P1_5
#else
#error "Invalid I2C0_RX Pin Configuration!"
#endif
// <o> I2C0_CLK OUTPUT Pin <0=>P0_8 <1=>P1_1
#define RTE_I2C0_CLK_OUTPUT_ID 1
#if (RTE_I2C0_CLK_OUTPUT_ID == 0)
#define RTE_I2C0_CLK_OUTPUT_PORT P0_8
#define RTE_I2C0_CLK_AF P0_8_AF_U0C0_SCLKOUT
#elif (RTE_I2C0_CLK_OUTPUT_ID == 1)
#define RTE_I2C0_CLK_OUTPUT_PORT P1_1
#define RTE_I2C0_CLK_AF P1_1_AF_U0C0_SCLKOUT
#else
#error "Invalid I2C0 CLOCK OUTPUT Pin Configuration!"
#endif
// <o> I2C0_CLK INPUT Pin <0=>P1_1 <1=>P0_8
#define RTE_I2C0_CLK_INPUT_ID 1
#if (RTE_I2C0_CLK_INPUT_ID == 0)
#define RTE_I2C0_CLK_INPUT_PORT P1_1
#define RTE_I2C0_CLK_INPUT USIC0_C0_DX1_P1_1
#elif (RTE_I2C0_CLK_INPUT_ID == 1)
#define RTE_I2C0_CLK_INPUT_PORT P0_8
#define RTE_I2C0_CLK_INPUT USIC0_C0_DX1_P0_8
#else
#error "Invalid I2C0 CLOCK INPUT Pin Configuration!"
#endif
// <o> I2C0_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_I2C0_RX_FIFO_SIZE_ID 2
#if (RTE_I2C0_RX_FIFO_SIZE_ID == 0)
#define RTE_I2C0_RX_FIFO_SIZE NO_FIFO
#define RTE_I2C0_RX_FIFO_SIZE_NUM 0
#elif (RTE_I2C0_RX_FIFO_SIZE_ID == 1)
#define RTE_I2C0_RX_FIFO_SIZE FIFO_SIZE_2
#define RTE_I2C0_RX_FIFO_SIZE_NUM 2
#elif (RTE_I2C0_RX_FIFO_SIZE_ID == 2)
#define RTE_I2C0_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_I2C0_RX_FIFO_SIZE_NUM 4
#elif (RTE_I2C0_RX_FIFO_SIZE_ID == 3)
#define RTE_I2C0_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_I2C0_RX_FIFO_SIZE_NUM 4
#elif (RTE_I2C0_RX_FIFO_SIZE_ID == 4)
#define RTE_I2C0_RX_FIFO_SIZE FIFO_SIZE_16
#define RTE_I2C0_RX_FIFO_SIZE_NUM 16
#elif (RTE_I2C0_RX_FIFO_SIZE_ID == 5)
#define RTE_I2C0_RX_FIFO_SIZE FIFO_SIZE_32
#define RTE_I2C0_RX_FIFO_SIZE_NUM 32
#elif (RTE_I2C0_RX_FIFO_SIZE_ID == 6)
#define RTE_I2C0_RX_FIFO_SIZE FIFO_SIZE_64
#define RTE_I2C0_RX_FIFO_SIZE_NUM 64
#else
#error "Invalid I2C0_RX FIFO SIZE Configuration!"
#endif
// <o> I2C0_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_I2C0_TX_FIFO_SIZE_ID 2
#if (RTE_I2C0_TX_FIFO_SIZE_ID == 0)
#define RTE_I2C0_TX_FIFO_SIZE NO_FIFO
#define RTE_I2C0_TX_FIFO_SIZE_NUM 0
#elif (RTE_I2C0_TX_FIFO_SIZE_ID == 1)
#define RTE_I2C0_TX_FIFO_SIZE FIFO_SIZE_2
#define RTE_I2C0_TX_FIFO_SIZE_NUM 2
#elif (RTE_I2C0_TX_FIFO_SIZE_ID == 2)
#define RTE_I2C0_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_I2C0_TX_FIFO_SIZE_NUM 4
#elif (RTE_I2C0_TX_FIFO_SIZE_ID == 3)
#define RTE_I2C0_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_I2C0_TX_FIFO_SIZE_NUM 4
#elif (RTE_I2C0_TX_FIFO_SIZE_ID == 4)
#define RTE_I2C0_TX_FIFO_SIZE FIFO_SIZE_16
#define RTE_I2C0_TX_FIFO_SIZE_NUM 16
#elif (RTE_I2C0_TX_FIFO_SIZE_ID == 5)
#define RTE_I2C0_TX_FIFO_SIZE FIFO_SIZE_32
#define RTE_I2C0_TX_FIFO_SIZE_NUM 32
#elif (RTE_I2C0_TX_FIFO_SIZE_ID == 6)
#define RTE_I2C0_TX_FIFO_SIZE FIFO_SIZE_64
#define RTE_I2C0_TX_FIFO_SIZE_NUM 64
#else
#error "Invalid I2C0_TX FIFO SIZE Configuration!"
#endif
//</e>
// <e> I2C1 (Inter-Integrated circuit) [Driver_I2C1]
// <i> Configuration settings for Driver_I2C1 in component ::Drivers:I2C
#define RTE_I2C1 0
// <o> I2C1_TX Pin <0=>P2_5
#define RTE_I2C1_TX_ID 0
#if (RTE_I2C1_TX_ID == 0)
#define RTE_I2C1_TX_PORT P2_5
#define RTE_I2C1_TX_AF P2_5_AF_U0C1_DOUT0
#else
#error "Invalid I2C1_TX Pin Configuration!"
#endif
// <o> I2C1_RX Pin <0=>P2_2 <1=>P2_5
#define RTE_I2C1_RX_ID 1
#if (RTE_I2C1_RX_ID == 0)
#define RTE_I2C1_RX_PORT P2_2
#define RTE_I2C1_RX_INPUT USIC0_C1_DX0_P2_2
#elif (RTE_I2C1_RX_ID == 1)
#define RTE_I2C1_RX_PORT P2_5
#define RTE_I2C1_RX_INPUT USIC0_C1_DX0_P2_5
#else
#error "Invalid I2C1_RX Pin Configuration!"
#endif
// <o> I2C1_CLK OUTPUT Pin <0=>P2_4
#define RTE_I2C1_CLK_OUTPUT_ID 0
#if (RTE_I2C1_CLK_OUTPUT_ID == 0)
#define RTE_I2C1_CLK_OUTPUT_PORT P2_4
#define RTE_I2C1_CLK_AF P2_4_AF_U0C1_SCLKOUT
#else
#error "Invalid I2C1 CLOCK OUTPUT Pin Configuration!"
#endif
// <o> I2C1_CLK INPUT Pin <0=>P2_4
#define RTE_I2C1_CLK_INPUT_ID 0
#if (RTE_I2C1_CLK_INPUT_ID == 0)
#define RTE_I2C1_CLK_INPUT_PORT P2_4
#define RTE_I2C1_CLK_INPUT USIC0_C1_DX1_P2_4
#else
#error "Invalid I2C1 CLOCK INPUT Pin Configuration!"
#endif
// <o> I2C1_RX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_I2C1_RX_FIFO_SIZE_ID 2
#if (RTE_I2C1_RX_FIFO_SIZE_ID == 0)
#define RTE_I2C1_RX_FIFO_SIZE NO_FIFO
#define RTE_I2C1_RX_FIFO_SIZE_NUM 0
#elif (RTE_I2C1_RX_FIFO_SIZE_ID == 1)
#define RTE_I2C1_RX_FIFO_SIZE FIFO_SIZE_2
#define RTE_I2C1_RX_FIFO_SIZE_NUM 2
#elif (RTE_I2C1_RX_FIFO_SIZE_ID == 2)
#define RTE_I2C1_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_I2C1_RX_FIFO_SIZE_NUM 4
#elif (RTE_I2C1_RX_FIFO_SIZE_ID == 3)
#define RTE_I2C1_RX_FIFO_SIZE FIFO_SIZE_4
#define RTE_I2C1_RX_FIFO_SIZE_NUM 4
#elif (RTE_I2C1_RX_FIFO_SIZE_ID == 4)
#define RTE_I2C1_RX_FIFO_SIZE FIFO_SIZE_16
#define RTE_I2C1_RX_FIFO_SIZE_NUM 16
#elif (RTE_I2C1_RX_FIFO_SIZE_ID == 5)
#define RTE_I2C1_RX_FIFO_SIZE FIFO_SIZE_32
#define RTE_I2C1_RX_FIFO_SIZE_NUM 32
#elif (RTE_I2C1_RX_FIFO_SIZE_ID == 6)
#define RTE_I2C1_RX_FIFO_SIZE FIFO_SIZE_64
#define RTE_I2C1_RX_FIFO_SIZE_NUM 64
#else
#error "Invalid I2C1_RX FIFO SIZE Configuration!"
#endif
// <o> I2C1_TX FIFO ENTRIES <0=>0 <1=>2 <2=>4 <3=>8 <4=>16 <5=>32 <6=>64
#define RTE_I2C1_TX_FIFO_SIZE_ID 2
#if (RTE_I2C1_TX_FIFO_SIZE_ID == 0)
#define RTE_I2C1_TX_FIFO_SIZE NO_FIFO
#define RTE_I2C1_TX_FIFO_SIZE_NUM 0
#elif (RTE_I2C1_TX_FIFO_SIZE_ID == 1)
#define RTE_I2C1_TX_FIFO_SIZE FIFO_SIZE_2
#define RTE_I2C1_TX_FIFO_SIZE_NUM 2
#elif (RTE_I2C1_TX_FIFO_SIZE_ID == 2)
#define RTE_I2C1_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_I2C1_TX_FIFO_SIZE_NUM 4
#elif (RTE_I2C1_TX_FIFO_SIZE_ID == 3)
#define RTE_I2C1_TX_FIFO_SIZE FIFO_SIZE_4
#define RTE_I2C1_TX_FIFO_SIZE_NUM 4
#elif (RTE_I2C1_TX_FIFO_SIZE_ID == 4)
#define RTE_I2C1_TX_FIFO_SIZE FIFO_SIZE_16
#define RTE_I2C1_TX_FIFO_SIZE_NUM 16
#elif (RTE_I2C1_TX_FIFO_SIZE_ID == 5)
#define RTE_I2C1_TX_FIFO_SIZE FIFO_SIZE_32
#define RTE_I2C1_TX_FIFO_SIZE_NUM 32
#elif (RTE_I2C1_TX_FIFO_SIZE_ID == 6)
#define RTE_I2C1_TX_FIFO_SIZE FIFO_SIZE_64
#define RTE_I2C1_TX_FIFO_SIZE_NUM 64
#else
#error "Invalid I2C1_TX FIFO SIZE Configuration!"
#endif
//</e>
#if ((RTE_UART0+RTE_I2C0+RTE_SPI0)>1)
#error "Choose just one Driver_I2C/SPI/UART0 driver !"
#elif ((RTE_UART1+RTE_I2C1+RTE_SPI1)>1)
#error "Choose just one Driver_I2C/SPI/UART1 driver !"
#elif ((RTE_UART2+RTE_I2C2+RTE_SPI2)>1)
#error "Choose just one Driver_I2C/SPI/UART2 driver !"
#elif ((RTE_UART3+RTE_I2C3+RTE_SPI3)>1)
#error "Choose just one Driver_I2C/SPI/UART3 driver !"
#endif
#endif /* __RTE_DEVICE_H */
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Examples/XMC4200/RTE/Device/XMC4200-Q48x256/startup_XMC4200.s
+535
View File
@@ -0,0 +1,535 @@
;*******************************************************************************
;* @file startup_XMC4200.s
;* @brief CMSIS Core Device Startup File for
;* Infineon XMC4200 Device Series
;* @version V1.2
;* @date November 2014
;*
;* Copyright (C) 2014 Infineon Technologies AG. All rights reserved.
;*
;*
;* @par
;* Infineon Technologies AG (Infineon) is supplying this software for use with
;* Infineon's microcontrollers. This file can be freely distributed
;* within development tools that are supporting such microcontrollers.
;*
;* @par
;* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
;* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
;* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
;* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
;* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
;*
;******************************************************************************
;************************** Version History ************************************
; V0.1, September 2012, First version
; V1.0, February 2013, FIX for CPU prefetch bug implemented
; V1.1, August 2013, Fix the bug of stack pointer alignment to a 8 byte boundary
; V1.2, November 2014, Disable CPU workaround. Increased stack size.
; Removed DAVE3 dependency
;*******************************************************************************
; ------------------ <<< Use Configuration Wizard in Context Menu >>> ------------------
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000800
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
IF :DEF:ENABLE_CPU_CM_001_WORKAROUND
MACRO
Entry $Handler
DCD $Handler._Veneer
MEND
ELSE
MACRO
Entry $Handler
DCD $Handler
MEND
ENDIF
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
Entry NMI_Handler ; 2 NMI Handler
Entry HardFault_Handler ; 3 Hard Fault Handler
Entry MemManage_Handler ; 4 MPU Fault Handler
Entry BusFault_Handler ; 5 Bus Fault Handler
Entry UsageFault_Handler ; 6 Usage Fault Handler
DCD 0 ; 7 Reserved
DCD 0 ; 8 Reserved
DCD 0 ; 9 Reserved
DCD 0 ; 10 Reserved
Entry SVC_Handler ; 11 SVCall Handler
Entry DebugMon_Handler ; 12 Debug Monitor Handler
DCD 0 ; 13 Reserved
Entry PendSV_Handler ; 14 PendSV Handler
Entry SysTick_Handler ; 15 SysTick Handler
; Interrupt Handlers for Service Requests (SR) from XMC4200 Peripherals */
Entry SCU_0_IRQHandler ; Handler name for SR SCU_0
Entry ERU0_0_IRQHandler ; Handler name for SR ERU0_0
Entry ERU0_1_IRQHandler ; Handler name for SR ERU0_1
Entry ERU0_2_IRQHandler ; Handler name for SR ERU0_2
Entry ERU0_3_IRQHandler ; Handler name for SR ERU0_3
Entry ERU1_0_IRQHandler ; Handler name for SR ERU1_0
Entry ERU1_1_IRQHandler ; Handler name for SR ERU1_1
Entry ERU1_2_IRQHandler ; Handler name for SR ERU1_2
Entry ERU1_3_IRQHandler ; Handler name for SR ERU1_3
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
Entry PMU0_0_IRQHandler ; Handler name for SR PMU0_0
DCD 0 ; Not Available
Entry VADC0_C0_0_IRQHandler ; Handler name for SR VADC0_C0_0
Entry VADC0_C0_1_IRQHandler ; Handler name for SR VADC0_C0_1
Entry VADC0_C0_2_IRQHandler ; Handler name for SR VADC0_C0_1
Entry VADC0_C0_3_IRQHandler ; Handler name for SR VADC0_C0_3
Entry VADC0_G0_0_IRQHandler ; Handler name for SR VADC0_G0_0
Entry VADC0_G0_1_IRQHandler ; Handler name for SR VADC0_G0_1
Entry VADC0_G0_2_IRQHandler ; Handler name for SR VADC0_G0_2
Entry VADC0_G0_3_IRQHandler ; Handler name for SR VADC0_G0_3
Entry VADC0_G1_0_IRQHandler ; Handler name for SR VADC0_G1_0
Entry VADC0_G1_1_IRQHandler ; Handler name for SR VADC0_G1_1
Entry VADC0_G1_2_IRQHandler ; Handler name for SR VADC0_G1_2
Entry VADC0_G1_3_IRQHandler ; Handler name for SR VADC0_G1_3
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
Entry DAC0_0_IRQHandler ; Handler name for SR DAC0_0
Entry DAC0_1_IRQHandler ; Handler name for SR DAC0_1
Entry CCU40_0_IRQHandler ; Handler name for SR CCU40_0
Entry CCU40_1_IRQHandler ; Handler name for SR CCU40_1
Entry CCU40_2_IRQHandler ; Handler name for SR CCU40_2
Entry CCU40_3_IRQHandler ; Handler name for SR CCU40_3
Entry CCU41_0_IRQHandler ; Handler name for SR CCU41_0
Entry CCU41_1_IRQHandler ; Handler name for SR CCU41_1
Entry CCU41_2_IRQHandler ; Handler name for SR CCU41_2
Entry CCU41_3_IRQHandler ; Handler name for SR CCU41_3
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
Entry CCU80_0_IRQHandler ; Handler name for SR CCU80_0
Entry CCU80_1_IRQHandler ; Handler name for SR CCU80_1
Entry CCU80_2_IRQHandler ; Handler name for SR CCU80_2
Entry CCU80_3_IRQHandler ; Handler name for SR CCU80_3
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
Entry POSIF0_0_IRQHandler ; Handler name for SR POSIF0_0
Entry POSIF0_1_IRQHandler ; Handler name for SR POSIF0_1
DCD 0 ; Not Available
DCD 0 ; Not Available
Entry HRPWM_0_IRQHandler ; Handler name for SR HRPWM_0
Entry HRPWM_1_IRQHandler ; Handler name for SR HRPWM_1
Entry HRPWM_2_IRQHandler ; Handler name for SR HRPWM_2
Entry HRPWM_3_IRQHandler ; Handler name for SR HRPWM_3
Entry CAN0_0_IRQHandler ; Handler name for SR CAN0_0
Entry CAN0_1_IRQHandler ; Handler name for SR CAN0_1
Entry CAN0_2_IRQHandler ; Handler name for SR CAN0_2
Entry CAN0_3_IRQHandler ; Handler name for SR CAN0_3
Entry CAN0_4_IRQHandler ; Handler name for SR CAN0_4
Entry CAN0_5_IRQHandler ; Handler name for SR CAN0_5
Entry CAN0_6_IRQHandler ; Handler name for SR CAN0_6
Entry CAN0_7_IRQHandler ; Handler name for SR CAN0_7
Entry USIC0_0_IRQHandler ; Handler name for SR USIC0_0
Entry USIC0_1_IRQHandler ; Handler name for SR USIC0_1
Entry USIC0_2_IRQHandler ; Handler name for SR USIC0_2
Entry USIC0_3_IRQHandler ; Handler name for SR USIC0_3
Entry USIC0_4_IRQHandler ; Handler name for SR USIC0_4
Entry USIC0_5_IRQHandler ; Handler name for SR USIC0_5
Entry USIC1_0_IRQHandler ; Handler name for SR USIC1_0
Entry USIC1_1_IRQHandler ; Handler name for SR USIC1_1
Entry USIC1_2_IRQHandler ; Handler name for SR USIC1_2
Entry USIC1_3_IRQHandler ; Handler name for SR USIC1_3
Entry USIC1_4_IRQHandler ; Handler name for SR USIC1_4
Entry USIC1_5_IRQHandler ; Handler name for SR USIC1_5
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
Entry LEDTS0_0_IRQHandler ; Handler name for SR LEDTS0_0
DCD 0 ; Not Available
Entry FCE0_0_IRQHandler ; Handler name for SR FCE0_0
Entry GPDMA0_0_IRQHandler ; Handler name for SR GPDMA0_0
DCD 0 ; Not Available
Entry USB0_0_IRQHandler ; Handler name for SR USB0_0
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
DCD 0 ; Not Available
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR SP, =__initial_sp
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
Default_Handler PROC
EXPORT NMI_Handler [WEAK]
EXPORT HardFault_Handler [WEAK]
EXPORT MemManage_Handler [WEAK]
EXPORT BusFault_Handler [WEAK]
EXPORT UsageFault_Handler [WEAK]
EXPORT SVC_Handler [WEAK]
EXPORT DebugMon_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
EXPORT SCU_0_IRQHandler [WEAK]
EXPORT ERU0_0_IRQHandler [WEAK]
EXPORT ERU0_1_IRQHandler [WEAK]
EXPORT ERU0_2_IRQHandler [WEAK]
EXPORT ERU0_3_IRQHandler [WEAK]
EXPORT ERU1_0_IRQHandler [WEAK]
EXPORT ERU1_1_IRQHandler [WEAK]
EXPORT ERU1_2_IRQHandler [WEAK]
EXPORT ERU1_3_IRQHandler [WEAK]
EXPORT PMU0_0_IRQHandler [WEAK]
EXPORT VADC0_C0_0_IRQHandler [WEAK]
EXPORT VADC0_C0_1_IRQHandler [WEAK]
EXPORT VADC0_C0_2_IRQHandler [WEAK]
EXPORT VADC0_C0_3_IRQHandler [WEAK]
EXPORT VADC0_G0_0_IRQHandler [WEAK]
EXPORT VADC0_G0_1_IRQHandler [WEAK]
EXPORT VADC0_G0_2_IRQHandler [WEAK]
EXPORT VADC0_G0_3_IRQHandler [WEAK]
EXPORT VADC0_G1_0_IRQHandler [WEAK]
EXPORT VADC0_G1_1_IRQHandler [WEAK]
EXPORT VADC0_G1_2_IRQHandler [WEAK]
EXPORT VADC0_G1_3_IRQHandler [WEAK]
EXPORT DSD0_0_IRQHandler [WEAK]
EXPORT DSD0_1_IRQHandler [WEAK]
EXPORT DSD0_2_IRQHandler [WEAK]
EXPORT DSD0_3_IRQHandler [WEAK]
EXPORT DSD0_4_IRQHandler [WEAK]
EXPORT DSD0_5_IRQHandler [WEAK]
EXPORT DSD0_6_IRQHandler [WEAK]
EXPORT DSD0_7_IRQHandler [WEAK]
EXPORT DAC0_0_IRQHandler [WEAK]
EXPORT DAC0_1_IRQHandler [WEAK]
EXPORT CCU40_0_IRQHandler [WEAK]
EXPORT CCU40_1_IRQHandler [WEAK]
EXPORT CCU40_2_IRQHandler [WEAK]
EXPORT CCU40_3_IRQHandler [WEAK]
EXPORT CCU41_0_IRQHandler [WEAK]
EXPORT CCU41_1_IRQHandler [WEAK]
EXPORT CCU41_2_IRQHandler [WEAK]
EXPORT CCU41_3_IRQHandler [WEAK]
EXPORT CCU80_0_IRQHandler [WEAK]
EXPORT CCU80_1_IRQHandler [WEAK]
EXPORT CCU80_2_IRQHandler [WEAK]
EXPORT CCU80_3_IRQHandler [WEAK]
EXPORT POSIF0_0_IRQHandler [WEAK]
EXPORT POSIF0_1_IRQHandler [WEAK]
EXPORT HRPWM_0_IRQHandler [WEAK]
EXPORT HRPWM_1_IRQHandler [WEAK]
EXPORT HRPWM_2_IRQHandler [WEAK]
EXPORT HRPWM_3_IRQHandler [WEAK]
EXPORT CAN0_0_IRQHandler [WEAK]
EXPORT CAN0_1_IRQHandler [WEAK]
EXPORT CAN0_2_IRQHandler [WEAK]
EXPORT CAN0_3_IRQHandler [WEAK]
EXPORT CAN0_4_IRQHandler [WEAK]
EXPORT CAN0_5_IRQHandler [WEAK]
EXPORT CAN0_6_IRQHandler [WEAK]
EXPORT CAN0_7_IRQHandler [WEAK]
EXPORT USIC0_0_IRQHandler [WEAK]
EXPORT USIC0_1_IRQHandler [WEAK]
EXPORT USIC0_2_IRQHandler [WEAK]
EXPORT USIC0_3_IRQHandler [WEAK]
EXPORT USIC0_4_IRQHandler [WEAK]
EXPORT USIC0_5_IRQHandler [WEAK]
EXPORT USIC1_0_IRQHandler [WEAK]
EXPORT USIC1_1_IRQHandler [WEAK]
EXPORT USIC1_2_IRQHandler [WEAK]
EXPORT USIC1_3_IRQHandler [WEAK]
EXPORT USIC1_4_IRQHandler [WEAK]
EXPORT USIC1_5_IRQHandler [WEAK]
EXPORT LEDTS0_0_IRQHandler [WEAK]
EXPORT FCE0_0_IRQHandler [WEAK]
EXPORT GPDMA0_0_IRQHandler [WEAK]
EXPORT USB0_0_IRQHandler [WEAK]
NMI_Handler
HardFault_Handler
MemManage_Handler
BusFault_Handler
UsageFault_Handler
SVC_Handler
DebugMon_Handler
PendSV_Handler
SysTick_Handler
SCU_0_IRQHandler
ERU0_0_IRQHandler
ERU0_1_IRQHandler
ERU0_2_IRQHandler
ERU0_3_IRQHandler
ERU1_0_IRQHandler
ERU1_1_IRQHandler
ERU1_2_IRQHandler
ERU1_3_IRQHandler
PMU0_0_IRQHandler
VADC0_C0_0_IRQHandler
VADC0_C0_1_IRQHandler
VADC0_C0_2_IRQHandler
VADC0_C0_3_IRQHandler
VADC0_G0_0_IRQHandler
VADC0_G0_1_IRQHandler
VADC0_G0_2_IRQHandler
VADC0_G0_3_IRQHandler
VADC0_G1_0_IRQHandler
VADC0_G1_1_IRQHandler
VADC0_G1_2_IRQHandler
VADC0_G1_3_IRQHandler
DSD0_0_IRQHandler
DSD0_1_IRQHandler
DSD0_2_IRQHandler
DSD0_3_IRQHandler
DSD0_4_IRQHandler
DSD0_5_IRQHandler
DSD0_6_IRQHandler
DSD0_7_IRQHandler
DAC0_0_IRQHandler
DAC0_1_IRQHandler
CCU40_0_IRQHandler
CCU40_1_IRQHandler
CCU40_2_IRQHandler
CCU40_3_IRQHandler
CCU41_0_IRQHandler
CCU41_1_IRQHandler
CCU41_2_IRQHandler
CCU41_3_IRQHandler
CCU80_0_IRQHandler
CCU80_1_IRQHandler
CCU80_2_IRQHandler
CCU80_3_IRQHandler
POSIF0_0_IRQHandler
POSIF0_1_IRQHandler
HRPWM_0_IRQHandler
HRPWM_1_IRQHandler
HRPWM_2_IRQHandler
HRPWM_3_IRQHandler
CAN0_0_IRQHandler
CAN0_1_IRQHandler
CAN0_2_IRQHandler
CAN0_3_IRQHandler
CAN0_4_IRQHandler
CAN0_5_IRQHandler
CAN0_6_IRQHandler
CAN0_7_IRQHandler
USIC0_0_IRQHandler
USIC0_1_IRQHandler
USIC0_2_IRQHandler
USIC0_3_IRQHandler
USIC0_4_IRQHandler
USIC0_5_IRQHandler
USIC1_0_IRQHandler
USIC1_1_IRQHandler
USIC1_2_IRQHandler
USIC1_3_IRQHandler
USIC1_4_IRQHandler
USIC1_5_IRQHandler
LEDTS0_0_IRQHandler
FCE0_0_IRQHandler
GPDMA0_0_IRQHandler
USB0_0_IRQHandler
B .
ENDP
IF :DEF:ENABLE_CPU_CM_001_WORKAROUND
MACRO
Insert_ExceptionHandlerVeneer $Handler_Func
$Handler_Func._Veneer\
PROC
EXPORT $Handler_Func._Veneer
LDR R0, =$Handler_Func
PUSH {LR} ;/* Breaks AAPCS */
SUB SP,#4 ;/* Restores AAPCS */
BLX R0
ADD SP,#4
POP {PC}
ALIGN
LTORG
ENDP
MEND
Insert_ExceptionHandlerVeneer NMI_Handler
Insert_ExceptionHandlerVeneer HardFault_Handler
Insert_ExceptionHandlerVeneer MemManage_Handler
Insert_ExceptionHandlerVeneer BusFault_Handler
Insert_ExceptionHandlerVeneer UsageFault_Handler
Insert_ExceptionHandlerVeneer SVC_Handler
Insert_ExceptionHandlerVeneer DebugMon_Handler
Insert_ExceptionHandlerVeneer PendSV_Handler
Insert_ExceptionHandlerVeneer SysTick_Handler
Insert_ExceptionHandlerVeneer SCU_0_IRQHandler
Insert_ExceptionHandlerVeneer ERU0_0_IRQHandler
Insert_ExceptionHandlerVeneer ERU0_1_IRQHandler
Insert_ExceptionHandlerVeneer ERU0_2_IRQHandler
Insert_ExceptionHandlerVeneer ERU0_3_IRQHandler
Insert_ExceptionHandlerVeneer ERU1_0_IRQHandler
Insert_ExceptionHandlerVeneer ERU1_1_IRQHandler
Insert_ExceptionHandlerVeneer ERU1_2_IRQHandler
Insert_ExceptionHandlerVeneer ERU1_3_IRQHandler
Insert_ExceptionHandlerVeneer PMU0_0_IRQHandler
Insert_ExceptionHandlerVeneer VADC0_C0_0_IRQHandler
Insert_ExceptionHandlerVeneer VADC0_C0_1_IRQHandler
Insert_ExceptionHandlerVeneer VADC0_C0_2_IRQHandler
Insert_ExceptionHandlerVeneer VADC0_C0_3_IRQHandler
Insert_ExceptionHandlerVeneer VADC0_G0_0_IRQHandler
Insert_ExceptionHandlerVeneer VADC0_G0_1_IRQHandler
Insert_ExceptionHandlerVeneer VADC0_G0_2_IRQHandler
Insert_ExceptionHandlerVeneer VADC0_G0_3_IRQHandler
Insert_ExceptionHandlerVeneer VADC0_G1_0_IRQHandler
Insert_ExceptionHandlerVeneer VADC0_G1_1_IRQHandler
Insert_ExceptionHandlerVeneer VADC0_G1_2_IRQHandler
Insert_ExceptionHandlerVeneer VADC0_G1_3_IRQHandler
Insert_ExceptionHandlerVeneer DSD0_0_IRQHandler
Insert_ExceptionHandlerVeneer DSD0_1_IRQHandler
Insert_ExceptionHandlerVeneer DSD0_2_IRQHandler
Insert_ExceptionHandlerVeneer DSD0_3_IRQHandler
Insert_ExceptionHandlerVeneer DSD0_4_IRQHandler
Insert_ExceptionHandlerVeneer DSD0_5_IRQHandler
Insert_ExceptionHandlerVeneer DSD0_6_IRQHandler
Insert_ExceptionHandlerVeneer DSD0_7_IRQHandler
Insert_ExceptionHandlerVeneer DAC0_0_IRQHandler
Insert_ExceptionHandlerVeneer DAC0_1_IRQHandler
Insert_ExceptionHandlerVeneer CCU40_0_IRQHandler
Insert_ExceptionHandlerVeneer CCU40_1_IRQHandler
Insert_ExceptionHandlerVeneer CCU40_2_IRQHandler
Insert_ExceptionHandlerVeneer CCU40_3_IRQHandler
Insert_ExceptionHandlerVeneer CCU41_0_IRQHandler
Insert_ExceptionHandlerVeneer CCU41_1_IRQHandler
Insert_ExceptionHandlerVeneer CCU41_2_IRQHandler
Insert_ExceptionHandlerVeneer CCU41_3_IRQHandler
Insert_ExceptionHandlerVeneer CCU80_0_IRQHandler
Insert_ExceptionHandlerVeneer CCU80_1_IRQHandler
Insert_ExceptionHandlerVeneer CCU80_2_IRQHandler
Insert_ExceptionHandlerVeneer CCU80_3_IRQHandler
Insert_ExceptionHandlerVeneer POSIF0_0_IRQHandler
Insert_ExceptionHandlerVeneer POSIF0_1_IRQHandler
Insert_ExceptionHandlerVeneer HRPWM_0_IRQHandler
Insert_ExceptionHandlerVeneer HRPWM_1_IRQHandler
Insert_ExceptionHandlerVeneer HRPWM_2_IRQHandler
Insert_ExceptionHandlerVeneer HRPWM_3_IRQHandler
Insert_ExceptionHandlerVeneer CAN0_0_IRQHandler
Insert_ExceptionHandlerVeneer CAN0_1_IRQHandler
Insert_ExceptionHandlerVeneer CAN0_2_IRQHandler
Insert_ExceptionHandlerVeneer CAN0_3_IRQHandler
Insert_ExceptionHandlerVeneer CAN0_4_IRQHandler
Insert_ExceptionHandlerVeneer CAN0_5_IRQHandler
Insert_ExceptionHandlerVeneer CAN0_6_IRQHandler
Insert_ExceptionHandlerVeneer CAN0_7_IRQHandler
Insert_ExceptionHandlerVeneer USIC0_0_IRQHandler
Insert_ExceptionHandlerVeneer USIC0_1_IRQHandler
Insert_ExceptionHandlerVeneer USIC0_2_IRQHandler
Insert_ExceptionHandlerVeneer USIC0_3_IRQHandler
Insert_ExceptionHandlerVeneer USIC0_4_IRQHandler
Insert_ExceptionHandlerVeneer USIC0_5_IRQHandler
Insert_ExceptionHandlerVeneer USIC1_0_IRQHandler
Insert_ExceptionHandlerVeneer USIC1_1_IRQHandler
Insert_ExceptionHandlerVeneer USIC1_2_IRQHandler
Insert_ExceptionHandlerVeneer USIC1_3_IRQHandler
Insert_ExceptionHandlerVeneer USIC1_4_IRQHandler
Insert_ExceptionHandlerVeneer USIC1_5_IRQHandler
Insert_ExceptionHandlerVeneer LEDTS0_0_IRQHandler
Insert_ExceptionHandlerVeneer FCE0_0_IRQHandler
Insert_ExceptionHandlerVeneer GPDMA0_0_IRQHandler
Insert_ExceptionHandlerVeneer USB0_0_IRQHandler
ENDIF
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Examples/XMC4200/RTE/Device/XMC4200-Q48x256/system_XMC4200.c
+649
View File
@@ -0,0 +1,649 @@
/******************************************************************************
* @file system_XMC4200.c
* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File
* for the Infineon XMC4200 Device Series
* @version V3.1.0
* @date 20. Dec 2014
*
* Copyright (C) 2014 Infineon Technologies AG. All rights reserved.
*
*
* @par
* Infineon Technologies AG (Infineon) is supplying this software for use with
* Infineon's microcontrollers. This file can be freely distributed
* within development tools that are supporting such microcontrollers.
*
* @par
* THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/********************** Version History ***************************************
* V3.1.0, Dec 2014, Added options to configure clock settings
******************************************************************************/
/*******************************************************************************
* HEADER FILES
*******************************************************************************/
#include <string.h>
#include <XMC4200.h>
#include "system_XMC4200.h"
/*******************************************************************************
* MACROS
*******************************************************************************/
#define CHIPID_LOC ((uint8_t *)0x20000000UL)
#define HRPWM_CHARDATA_LOC ((uint8_t *)0x20000084UL)
/* Define WEAK attribute */
#if !defined(__WEAK)
#if defined ( __CC_ARM )
#define __WEAK __attribute__ ((weak))
#elif defined ( __ICCARM__ )
#define __WEAK __weak
#elif defined ( __GNUC__ )
#define __WEAK __attribute__ ((weak))
#elif defined ( __TASKING__ )
#define __WEAK __attribute__ ((weak))
#endif
#endif
#define PMU_FLASH_WS (0x2U)
#define FPLL_FREQUENCY (80000000U)
#define FOSCREF (2500000U)
#define DELAY_CNT_50US_50MHZ (2500UL)
#define DELAY_CNT_150US_50MHZ (7500UL)
#define DELAY_CNT_50US_60MHZ (3000UL)
#define DELAY_CNT_50US_80MHZ (4000UL)
#define SCU_PLL_PLLSTAT_OSC_USABLE (SCU_PLL_PLLSTAT_PLLHV_Msk | \
SCU_PLL_PLLSTAT_PLLLV_Msk | \
SCU_PLL_PLLSTAT_PLLSP_Msk)
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*
// <h> Clock configuration
*/
/*
// <o> External crystal frequency [Hz]
// <8000000=> 8MHz
// <12000000=> 12MHz
// <16000000=> 16MHz
// <i> Defines external crystal frequency
// <i> Default: 8MHz
*/
#define OSCHP_FREQUENCY (12000000U)
#if OSCHP_FREQUENCY == 8000000U
#define USB_PDIV (1U)
#define USB_NDIV (95U)
#define USB_DIV (3U)
#elif OSCHP_FREQUENCY == 12000000U
#define USB_PDIV (1U)
#define USB_NDIV (63U)
#define USB_DIV (3U)
#elif OSCHP_FREQUENCY == 16000000U
#define USB_PDIV (1U)
#define USB_NDIV (47U)
#define USB_DIV (3U)
#else
#error "External crystal frequency not supported"
#endif
/*
// <o> System clock (fSYS) source selection
// <0=> Backup clock (24MHz)
// <1=> Maximum clock frequency using PLL (80MHz)
// <i> Default: Maximum clock frequency using PLL (80MHz)
*/
#define SYS_CLOCK_SRC 1
#define SYS_CLOCK_SRC_OFI 0
#define SYS_CLOCK_SRC_PLL 1
/*
// <o> Backup clock calibration mode
// <0=> Factory calibration
// <1=> Automatic calibration
// <i> Default: Automatic calibration
*/
#define FOFI_CALIBRATION_MODE 1
#define FOFI_CALIBRATION_MODE_FACTORY 0
#define FOFI_CALIBRATION_MODE_AUTOMATIC 1
/*
// <o> Standby clock (fSTDBY) source selection
// <0=> Internal slow oscillator (32768Hz)
// <1=> External crystal (32768Hz)
// <i> Default: Internal slow oscillator (32768Hz)
*/
#define STDBY_CLOCK_SRC 0
#define STDBY_CLOCK_SRC_OSI 0
#define STDBY_CLOCK_SRC_OSCULP 1
/*
// <o> PLL clock source selection
// <0=> External crystal
// <1=> External direct input
// <2=> Internal fast oscillator
// <i> Default: External crystal
*/
#define PLL_CLOCK_SRC 0
#define PLL_CLOCK_SRC_EXT_XTAL 0
#define PLL_CLOCK_SRC_EXT_DIRECT 1
#define PLL_CLOCK_SRC_OFI 2
#if PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL
#if OSCHP_FREQUENCY == 8000000U
#define PLL_PDIV (1U)
#define PLL_NDIV (79U)
#define PLL_K2DIV (3U)
#elif OSCHP_FREQUENCY == 12000000U
#define PLL_PDIV (2U)
#define PLL_NDIV (79U)
#define PLL_K2DIV (3U)
#elif OSCHP_FREQUENCY == 16000000U
#define PLL_PDIV (1U)
#define PLL_NDIV (39U)
#define PLL_K2DIV (3U)
#else
#error "External crystal frequency not supported"
#endif
#define VCO ((OSCHP_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
#else /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_EXT_XTAL */
#define PLL_PDIV (5U)
#define PLL_NDIV (79U)
#define PLL_K2DIV (3U)
#define VCO ((OFI_FREQUENCY / (PLL_PDIV + 1UL)) * (PLL_NDIV + 1UL))
#endif /* PLL_CLOCK_SRC == PLL_CLOCK_SRC_OFI */
#define PLL_K2DIV_0 ((VCO / OFI_FREQUENCY) - 1UL)
#define PLL_K2DIV_1 ((VCO / 60000000U) - 1UL)
#define SCU_CLK_CLKCLR_ENABLE_USBCLK SCU_CLK_CLKCLR_USBCDI_Msk
#define SCU_CLK_CLKCLR_ENABLE_CCUCLK SCU_CLK_CLKCLR_CCUCDI_Msk
#define SCU_CLK_CLKCLR_ENABLE_WDTCLK SCU_CLK_CLKCLR_WDTCDI_Msk
#define SCU_CLK_USBCLKCR_USBSEL_USBPLL (0U << SCU_CLK_USBCLKCR_USBSEL_Pos)
#define SCU_CLK_USBCLKCR_USBSEL_PLL (1U << SCU_CLK_USBCLKCR_USBSEL_Pos)
#define SCU_CLK_WDTCLKCR_WDTSEL_OFI (0U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
#define SCU_CLK_WDTCLKCR_WDTSEL_STANDBY (1U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
#define SCU_CLK_WDTCLKCR_WDTSEL_PLL (2U << SCU_CLK_WDTCLKCR_WDTSEL_Pos)
#define SCU_CLK_EXTCLKCR_ECKSEL_SYS (0U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
#define SCU_CLK_EXTCLKCR_ECKSEL_USBPLL (2U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
#define SCU_CLK_EXTCLKCR_ECKSEL_PLL (3U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
#define SCU_CLK_EXTCLKCR_ECKSEL_STANDBY (4U << SCU_CLK_EXTCLKCR_ECKSEL_Pos)
#define EXTCLK_PIN_P0_8 (0)
#define EXTCLK_PIN_P1_15 (1)
/*
// <h> Clock tree
// <o1.0> CPU clock divider
// <0=> fCPU = fSYS
// <1=> fCPU = fSYS / 2
// <o2.0> Peripheral clock divider
// <0=> fPB = fCPU
// <1=> fPB = fCPU / 2
// <e.4> Enable CCU clock
// <o3.0> CCU clock divider
// <0=> fCCU = fCPU
// <1=> fCCU = fCPU / 2
// </e>
// <e.5> Enable WDT clock
// <o4.0..7> WDT clock divider <1-256><#-1>
// <o4.16..17> WDT clock source <0=> fOFI
// <1=> fSTDBY
// <2=> fPLL
// </e>
// <e.0> Enable USB clock
// <o5.16> USB clock source <0=> USBPLL
// <1=> PLL
// </e>
// <e6> External Clock configuration
// <o7.0..2> External clock source selection
// <0=> System clock
// <2=> USB PLL clock
// <3=> PLL clock
// <4=> Standby clock
// <o7.16..24> External clock divider <1-512><#-1>
// <i> Only valid for USB PLL and PLL clocks
// <o8.0> External Pin Selection
// <0=> P0.8
// <1=> P1.15
// </e>
// </h>
*/
#define ENABLE_SCUCLK (0U)
#define CPUCLKDIV (0U)
#define PBCLKDIV (0U)
#define CCUCLKDIV (0U)
#define WDTCLKDIV (0U | SCU_CLK_WDTCLKCR_WDTSEL_OFI)
#define USBCLKDIV (0U | SCU_CLK_USBCLKCR_USBSEL_USBPLL | USB_DIV)
#define ENABLE_EXTCLK (0U)
#define EXTCLKDIV (0U | SCU_CLK_EXTCLKCR_ECKSEL_SYS)
#define EXTCLK_PIN (0U)
#define ENABLE_PLL \
(SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL) || \
(((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_PLL)) || \
(((ENABLE_SCUCLK & SCU_CLK_CLKSET_WDTCEN_Msk) != 0) && ((WDTCLKDIV & SCU_CLK_WDTCLKCR_WDTSEL_Msk) == SCU_CLK_WDTCLKCR_WDTSEL_PLL))
/*
// </h>
*/
/*
//-------- <<< end of configuration section >>> ------------------
*/
/*******************************************************************************
* GLOBAL VARIABLES
*******************************************************************************/
#if defined ( __CC_ARM )
uint32_t SystemCoreClock __attribute__((at(0x20005FC0)));
uint8_t g_chipid[16] __attribute__((at(0x20005FC4)));
uint32_t g_hrpwm_char_data[3] __attribute__((at(0x20005FD4)));
#elif defined ( __ICCARM__ )
__no_init uint32_t SystemCoreClock;
__no_init uint8_t g_chipid[16];
__no_init uint32_t g_hrpwm_char_data[3];
#elif defined ( __GNUC__ )
uint32_t SystemCoreClock __attribute__((section(".no_init")));
uint8_t g_chipid[16] __attribute__((section(".no_init")));
uint32_t g_hrpwm_char_data[3] __attribute__((section(".no_init")));
#elif defined ( __TASKING__ )
uint32_t SystemCoreClock __at( 0x20005FC0 );
uint8_t g_chipid[16] __at( 0x20005FC4 );
uint32_t g_hrpwm_char_data[3] __at( 0x20005FD4 );
#endif
extern uint32_t __Vectors;
/*******************************************************************************
* LOCAL FUNCTIONS
*******************************************************************************/
static void delay(uint32_t cycles)
{
volatile uint32_t i;
for(i = 0UL; i < cycles ;++i)
{
__NOP();
}
}
/*******************************************************************************
* API IMPLEMENTATION
*******************************************************************************/
__WEAK void SystemInit(void)
{
memcpy(g_chipid, CHIPID_LOC, 16);
memcpy(g_hrpwm_char_data, HRPWM_CHARDATA_LOC, 12);
SystemCoreSetup();
SystemCoreClockSetup();
}
__WEAK void SystemCoreSetup(void)
{
uint32_t temp;
/* relocate vector table */
__disable_irq();
SCB->VTOR = (uint32_t)(&__Vectors);
__DSB();
__enable_irq();
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Enable unaligned memory access - SCB_CCR.UNALIGN_TRP = 0 */
SCB->CCR &= ~(SCB_CCR_UNALIGN_TRP_Msk);
temp = FLASH0->FCON;
temp &= ~FLASH_FCON_WSPFLASH_Msk;
temp |= PMU_FLASH_WS;
FLASH0->FCON = temp;
}
__WEAK void SystemCoreClockSetup(void)
{
#if FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_FACTORY
/* Enable factory calibration */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FOTR_Msk;
#else
/* Automatic calibration uses the fSTDBY */
/* Enable HIB domain */
/* Power up HIB domain if and only if it is currently powered down */
if((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
{
SCU_POWER->PWRSET |= SCU_POWER_PWRSET_HIB_Msk;
while((SCU_POWER->PWRSTAT & SCU_POWER_PWRSTAT_HIBEN_Msk) == 0)
{
/* wait until HIB domain is enabled */
}
}
/* Remove the reset only if HIB domain were in a state of reset */
if((SCU_RESET->RSTSTAT) & SCU_RESET_RSTSTAT_HIBRS_Msk)
{
SCU_RESET->RSTCLR |= SCU_RESET_RSTCLR_HIBRS_Msk;
delay(DELAY_CNT_150US_50MHZ);
}
#if STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP
/* Enable OSC_ULP */
if ((SCU_HIBERNATE->OSCULCTRL & SCU_HIBERNATE_OSCULCTRL_MODE_Msk) != 0UL)
{
/*enable OSC_ULP*/
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_OSCULCTRL_Msk)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
SCU_HIBERNATE->OSCULCTRL &= ~SCU_HIBERNATE_OSCULCTRL_MODE_Msk;
/* Check if the clock is OK using OSCULP Oscillator Watchdog*/
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_ULPWDGEN_Msk;
/* wait till clock is stable */
do
{
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCLR_Msk)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
SCU_HIBERNATE->HDCLR |= SCU_HIBERNATE_HDCLR_ULPWDG_Msk;
delay(DELAY_CNT_50US_50MHZ);
} while ((SCU_HIBERNATE->HDSTAT & SCU_HIBERNATE_HDSTAT_ULPWDG_Msk) != 0UL);
}
/* now OSC_ULP is running and can be used*/
/* Select OSC_ULP as the clock source for RTC and STDBY*/
while (SCU_GENERAL->MIRRSTS & SCU_GENERAL_MIRRSTS_HDCR_Msk)
{
/* check SCU_MIRRSTS to ensure that no transfer over serial interface is pending */
}
SCU_HIBERNATE->HDCR |= SCU_HIBERNATE_HDCR_RCS_Msk | SCU_HIBERNATE_HDCR_STDBYSEL_Msk;
#endif /* STDBY_CLOCK_SRC == STDBY_CLOCK_SRC_OSCULP */
/* Enable automatic calibration of internal fast oscillator */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_AOTREN_Msk;
#endif /* FOFI_CALIBRATION_MODE == FOFI_CALIBRATION_MODE_AUTOMATIC */
delay(DELAY_CNT_50US_50MHZ);
#if ENABLE_PLL
/* enable PLL */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
#if PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI
/* enable OSC_HP */
if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
{
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Pos);
SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
/* select OSC_HP clock as PLL input */
SCU_PLL->PLLCON2 &= ~SCU_PLL_PLLCON2_PINSEL_Msk;
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
{
/* wait till OSC_HP output frequency is usable */
}
}
#else /* PLL_CLOCK_SRC != PLL_CLOCK_SRC_OFI */
/* select backup clock as PLL input */
SCU_PLL->PLLCON2 |= SCU_PLL_PLLCON2_PINSEL_Msk;
#endif
/* Go to bypass the Main PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_VCOBYP_Msk;
/* disconnect Oscillator from PLL */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_FINDIS_Msk;
/* Setup divider settings for main PLL */
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
(PLL_K2DIV_0 << SCU_PLL_PLLCON1_K2DIV_Pos) |
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
/* Set OSCDISCDIS */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
/* connect Oscillator to PLL */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->PLLCON0 |= SCU_PLL_PLLCON0_RESLD_Msk;
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
{
/* wait for PLL Lock */
}
/* Disable bypass- put PLL clock back */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_VCOBYP_Msk;
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOBYST_Msk) != 0U)
{
/* wait for normal mode */
}
#endif /* ENABLE_PLL */
#if (SYS_CLOCK_SRC == SYS_CLOCK_SRC_PLL)
/* Switch system clock to PLL */
SCU_CLK->SYSCLKCR |= SCU_CLK_SYSCLKCR_SYSSEL_Msk;
#else
/* Switch system clock to backup clock */
SCU_CLK->SYSCLKCR &= ~SCU_CLK_SYSCLKCR_SYSSEL_Msk;
#endif
/* Before scaling to final frequency we need to setup the clock dividers */
SCU_CLK->PBCLKCR = PBCLKDIV;
SCU_CLK->CPUCLKCR = CPUCLKDIV;
SCU_CLK->CCUCLKCR = CCUCLKDIV;
SCU_CLK->WDTCLKCR = WDTCLKDIV;
SCU_CLK->USBCLKCR = USBCLKDIV;
#if ENABLE_PLL
/* PLL frequency stepping...*/
/* Reset OSCDISCDIS */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCDISCDIS_Msk;
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
(PLL_K2DIV_1 << SCU_PLL_PLLCON1_K2DIV_Pos) |
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
delay(DELAY_CNT_50US_60MHZ);
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
{
/* wait for PLL Lock */
}
SCU_PLL->PLLCON1 = ((PLL_NDIV << SCU_PLL_PLLCON1_NDIV_Pos) |
(PLL_K2DIV << SCU_PLL_PLLCON1_K2DIV_Pos) |
(PLL_PDIV << SCU_PLL_PLLCON1_PDIV_Pos));
delay(DELAY_CNT_50US_80MHZ);
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk) == 0U)
{
/* wait for PLL Lock */
}
SCU_TRAP->TRAPCLR = SCU_TRAP_TRAPCLR_SOSCWDGT_Msk | SCU_TRAP_TRAPCLR_SVCOLCKT_Msk;
#endif /* ENABLE_PLL */
#if (((ENABLE_SCUCLK & SCU_CLK_CLKSET_USBCEN_Msk) != 0) && ((USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) == SCU_CLK_USBCLKCR_USBSEL_USBPLL))
/* enable USB PLL first */
SCU_PLL->USBPLLCON &= ~(SCU_PLL_USBPLLCON_VCOPWD_Msk | SCU_PLL_USBPLLCON_PLLPWD_Msk);
/* USB PLL uses as clock input the OSC_HP */
/* check and if not already running enable OSC_HP */
if ((SCU_OSC->OSCHPCTRL & SCU_OSC_OSCHPCTRL_MODE_Msk) != 0U)
{
/* check if Main PLL is switched on for OSC WDG*/
if ((SCU_PLL->PLLCON0 &(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk)) != 0UL)
{
/* enable PLL first */
SCU_PLL->PLLCON0 &= ~(SCU_PLL_PLLCON0_VCOPWD_Msk | SCU_PLL_PLLCON0_PLLPWD_Msk);
}
SCU_OSC->OSCHPCTRL &= ~(SCU_OSC_OSCHPCTRL_MODE_Msk | SCU_OSC_OSCHPCTRL_OSCVAL_Pos);
SCU_OSC->OSCHPCTRL |= ((OSCHP_GetFrequency() / FOSCREF) - 1UL) << SCU_OSC_OSCHPCTRL_OSCVAL_Pos;
/* restart OSC Watchdog */
SCU_PLL->PLLCON0 &= ~SCU_PLL_PLLCON0_OSCRES_Msk;
while ((SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_OSC_USABLE) != SCU_PLL_PLLSTAT_OSC_USABLE)
{
/* wait till OSC_HP output frequency is usable */
}
}
/* Setup USB PLL */
/* Go to bypass the USB PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_VCOBYP_Msk;
/* disconnect Oscillator from USB PLL */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_FINDIS_Msk;
/* Setup Divider settings for USB PLL */
SCU_PLL->USBPLLCON = ((USB_NDIV << SCU_PLL_USBPLLCON_NDIV_Pos) |
(USB_PDIV << SCU_PLL_USBPLLCON_PDIV_Pos));
/* Set OSCDISCDIS */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_OSCDISCDIS_Msk;
/* connect Oscillator to USB PLL */
SCU_PLL->USBPLLCON &= ~SCU_PLL_USBPLLCON_FINDIS_Msk;
/* restart PLL Lock detection */
SCU_PLL->USBPLLCON |= SCU_PLL_USBPLLCON_RESLD_Msk;
while ((SCU_PLL->USBPLLSTAT & SCU_PLL_USBPLLSTAT_VCOLOCK_Msk) == 0U)
{
/* wait for PLL Lock */
}
#endif /* (USBCLKDIV & SCU_CLK_USBCLKCR_USBSEL_Msk) */
/* Enable selected clocks */
SCU_CLK->CLKSET = ENABLE_SCUCLK;
#if ENABLE_EXTCLK == 1
/* Configure external clock */
SCU_CLK->EXTCLKCR = EXTCLKDIV;
#if EXTCLK_PIN == EXTCLK_PIN_P1_15
/* P1.15 */
PORT1->PDR1 &= ~PORT1_PDR1_PD15_Msk;
PORT1->IOCR12 = (PORT1->IOCR12 & ~PORT0_IOCR12_PC15_Msk) | (0x11U << PORT0_IOCR12_PC15_Pos);
#else
/* P0.8 */
PORT0->HWSEL &= ~PORT0_HWSEL_HW8_Msk;
PORT0->PDR1 &= ~PORT0_PDR1_PD8_Msk;
PORT0->IOCR8 = (PORT0->IOCR8 & ~PORT0_IOCR8_PC8_Msk) | (0x11U << PORT0_IOCR8_PC8_Pos);
#endif
#endif /* ENABLE_EXTCLK == 1 */
SystemCoreClockUpdate();
}
__WEAK void SystemCoreClockUpdate(void)
{
uint32_t pdiv;
uint32_t ndiv;
uint32_t kdiv;
uint32_t temp;
if (SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSSEL_Msk)
{
/* fPLL is clock source for fSYS */
if(SCU_PLL->PLLCON2 & SCU_PLL_PLLCON2_PINSEL_Msk)
{
/* PLL input clock is the backup clock (fOFI) */
temp = OFI_FREQUENCY;
}
else
{
/* PLL input clock is the high performance osicllator (fOSCHP) */
temp = OSCHP_GetFrequency();
}
/* check if PLL is locked */
if (SCU_PLL->PLLSTAT & SCU_PLL_PLLSTAT_VCOLOCK_Msk)
{
/* PLL normal mode */
/* read back divider settings */
pdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_PDIV_Msk) >> SCU_PLL_PLLCON1_PDIV_Pos) + 1;
ndiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_NDIV_Msk) >> SCU_PLL_PLLCON1_NDIV_Pos) + 1;
kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K2DIV_Msk) >> SCU_PLL_PLLCON1_K2DIV_Pos) + 1;
temp = (temp / (pdiv * kdiv)) * ndiv;
}
else
{
/* PLL prescalar mode */
/* read back divider settings */
kdiv = ((SCU_PLL->PLLCON1 & SCU_PLL_PLLCON1_K1DIV_Msk) >> SCU_PLL_PLLCON1_K1DIV_Pos) + 1;
temp = (temp / kdiv);
}
}
else
{
/* fOFI is clock source for fSYS */
temp = OFI_FREQUENCY;
}
temp = temp / ((SCU_CLK->SYSCLKCR & SCU_CLK_SYSCLKCR_SYSDIV_Msk) + 1);
temp = temp / ((SCU_CLK->CPUCLKCR & SCU_CLK_CPUCLKCR_CPUDIV_Msk) + 1);
SystemCoreClock = temp;
}
__WEAK uint32_t OSCHP_GetFrequency(void)
{
return OSCHP_FREQUENCY;
}
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Examples/XMC4200/RTE/RTE_Components.h
+25
View File
@@ -0,0 +1,25 @@
/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'CMSIS_DAP'
* Target: 'XMC4200'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#define RTE_CMSIS_RTOS /* CMSIS-RTOS */
#define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */
#define RTE_DEVICE
#define RTE_DEVICE_STARTUP
#define RTE_DEVICE_XMCLIB_GPIO
#define RTE_DEVICE_XMCLIB_SCU
#define RTE_DEVICE_XMCLIB_UART
#define RTE_Drivers_USBD
#define RTE_USB_Core /* USB Core */
#define RTE_USB_Device_0 /* USB Device 0 */
#define RTE_USB_Device_HID_0 /* USB Device HID instance 0 */
#endif /* RTE_COMPONENTS_H */
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Examples/XMC4200/RTE/USB/USBD_Config_0.c
+171
View File
@@ -0,0 +1,171 @@
/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device
* Copyright (c) 2004-2014 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_Config_0.c
* Purpose: USB Device Configuration
* Rev.: V5.00
*------------------------------------------------------------------------------
* Use the following configuration settings in the Device Class configuration
* files to assign a Device Class to this USB Device 0.
*
* Configuration Setting Value
* --------------------- -----
* Assign Device Class to USB Device # = 0
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>USB Device 0
// <o>Connect to hardware via Driver_USBD# <0-255>
// <i>Select driver control block for hardware interface.
#define USBD0_PORT 0
// <o.0>High-speed
// <i>Enable High-speed functionality (if device supports it).
#define USBD0_HS 0
// <h>Device Settings
// <i>These settings are used to create the Device Descriptor
// <o>Max Endpoint 0 Packet Size
// <i>Maximum packet size for Endpoint 0 (bMaxPacketSize0).
// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes
#define USBD0_MAX_PACKET0 64
// <o.0..15>Vendor ID <0x0000-0xFFFF>
// <i>Vendor ID assigned by USB-IF (idVendor).
#define USBD0_DEV_DESC_IDVENDOR 0xC251
// <o.0..15>Product ID <0x0000-0xFFFF>
// <i>Product ID assigned by manufacturer (idProduct).
#define USBD0_DEV_DESC_IDPRODUCT 0xF008
// <o.0..15>Device Release Number <0x0000-0xFFFF>
// <i>Device Release Number in binary-coded decimal (bcdDevice)
#define USBD0_DEV_DESC_BCDDEVICE 0x0100
// </h>
// <h>Configuration Settings
// <i>These settings are used to create the Configuration Descriptor.
// <o.6>Power
// <i>Default Power Setting (D6: of bmAttributes).
// <0=>Bus-powered
// <1=>Self-powered
// <o.5>Remote Wakeup
// <i>Configuration support for Remote Wakeup (D5: of bmAttributes).
#define USBD0_CFG_DESC_BMATTRIBUTES 0x80
// <o.0..7>Maximum Power Consumption (in mA) <0-510><#/2>
// <i>Maximum Power Consumption of USB Device from bus in this
// <i>specific configuration when device is fully operational (bMaxPower).
#define USBD0_CFG_DESC_BMAXPOWER 250
// </h>
// <h>String Settings
// <i>These settings are used to create the String Descriptor.
// <o.0..15>Language ID <0x0000-0xFCFF>
// <i>English (United States) = 0x0409.
#define USBD0_STR_DESC_LANGID 0x0409
// <s.126>Manufacturer String
// <i>String Descriptor describing Manufacturer.
#define USBD0_STR_DESC_MAN L"KEIL - Tools By ARM"
// <s.126>Product String
// <i>String Descriptor describing Product.
#define USBD0_STR_DESC_PROD L"XMC4200 CMSIS-DAP"
// <e.0>Serial Number
// <i>Enable Serial Number String.
// <i>If disabled Serial Number String will not be assigned to USB Device.
#define USBD0_STR_DESC_SER_EN 1
// <s.126>Serial Number String
// <i>String Descriptor describing device's Serial Number.
#define USBD0_STR_DESC_SER L"0001A0000000"
// </e>
// </h>
// <h>OS Resources Settings
// <i>These settings are used to optimize usage of OS resources.
// <o>Core Thread Stack Size <64-65536>
#define USBD0_CORE_THREAD_STACK_SIZE 512
// Core Thread Priority
#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal
// </h>
// </h>
#include "..\RTE_Components.h"
#ifdef RTE_USB_Device_CustomClass_0
#include "USBD_Config_CustomClass_0.h"
#endif
#ifdef RTE_USB_Device_CustomClass_1
#include "USBD_Config_CustomClass_1.h"
#endif
#ifdef RTE_USB_Device_CustomClass_2
#include "USBD_Config_CustomClass_2.h"
#endif
#ifdef RTE_USB_Device_CustomClass_3
#include "USBD_Config_CustomClass_3.h"
#endif
#ifdef RTE_USB_Device_HID_0
#include "USBD_Config_HID_0.h"
#endif
#ifdef RTE_USB_Device_HID_1
#include "USBD_Config_HID_1.h"
#endif
#ifdef RTE_USB_Device_HID_2
#include "USBD_Config_HID_2.h"
#endif
#ifdef RTE_USB_Device_HID_3
#include "USBD_Config_HID_3.h"
#endif
#ifdef RTE_USB_Device_MSC_0
#include "USBD_Config_MSC_0.h"
#endif
#ifdef RTE_USB_Device_MSC_1
#include "USBD_Config_MSC_1.h"
#endif
#ifdef RTE_USB_Device_MSC_2
#include "USBD_Config_MSC_2.h"
#endif
#ifdef RTE_USB_Device_MSC_3
#include "USBD_Config_MSC_3.h"
#endif
#ifdef RTE_USB_Device_CDC_0
#include "USBD_Config_CDC_0.h"
#endif
#ifdef RTE_USB_Device_CDC_1
#include "USBD_Config_CDC_1.h"
#endif
#ifdef RTE_USB_Device_CDC_2
#include "USBD_Config_CDC_2.h"
#endif
#ifdef RTE_USB_Device_CDC_3
#include "USBD_Config_CDC_3.h"
#endif
#ifdef RTE_USB_Device_ADC_0
#include "USBD_Config_ADC_0.h"
#endif
#ifdef RTE_USB_Device_ADC_1
#include "USBD_Config_ADC_1.h"
#endif
#ifdef RTE_USB_Device_ADC_2
#include "USBD_Config_ADC_2.h"
#endif
#ifdef RTE_USB_Device_ADC_3
#include "USBD_Config_ADC_3.h"
#endif
#include "usbd_config.h"
PAN159/PAN159-Template/Library/CMSIS/DAP/Firmware/Examples/XMC4200/RTE/USB/USBD_Config_HID_0.h
+171
View File
@@ -0,0 +1,171 @@
/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device
* Copyright (c) 2004-2015 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_Config_HID_0.h
* Purpose: USB Device Human Interface Device class (HID) Configuration
* Rev.: V5.0.1
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>USB Device: Human Interface Device class (HID) 0
// <o>Assign Device Class to USB Device # <0-3>
// <i>Select USB Device that is used for this Device Class instance
#define USBD_HID0_DEV 0
// <h>Interrupt Endpoint Settings
// <i>By default, the settings match the first USB Class instance in a USB Device.
// <i>Endpoint conflicts are flagged by compile-time error messages.
//
// <h>Interrupt IN Endpoint Settings
// <o.0..3>Interrupt IN Endpoint Number
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
#define USBD_HID0_EP_INT_IN 1
// <h>Endpoint Settings
// <i>Parameters are used to create USB Descriptors, HID Device Descriptor
// <i>and for memory allocation in the USB component.
//
// <h>Full/Low-speed (High-speed disabled)
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 64.
#define USBD_HID0_EP_INT_IN_WMAXPACKETSIZE 64
// <o.0..7>Endpoint polling Interval (in ms) <1-255>
// <i>Specifies the frequency of requests initiated by USB Host for
// <i>function USBD_HIDn_GetReport.
#define USBD_HID0_EP_INT_IN_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
//
// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 1024.
// <o.11..12>Additional transactions per microframe
// <i>Additional transactions improve communication performance.
// <0=>None <1=>1 additional <2=>2 additional
#define USBD_HID0_EP_INT_IN_HS_WMAXPACKETSIZE 64
// <o.0..4>Endpoint polling Interval (in 125 us intervals)
// <i>Specifies the frequency of requests initiated by USB Host for
// <i>function USBD_HIDn_GetReport.
// <1=> 1 <2=> 2 <3=> 4 <4=> 8
// <5=> 16 <6=> 32 <7=> 64 <8=> 128
// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
// <13=>4096 <14=>8192 <15=>16384 <16=>32768
#define USBD_HID0_EP_INT_IN_HS_BINTERVAL 1
// </h>
// </h>
// </h>
// <h>Interrupt OUT Endpoint Settings
// <o.0..3>Interrupt OUT Endpoint Number
// <i>When OUT Endpoint is set to "Not used" the USB Host uses
// <i>the Control Endpoint 0 for Out Reports.
// <0=>Not used
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
#define USBD_HID0_EP_INT_OUT 1
// <h>Endpoint Settings
// <i>Parameters are used to create USB Descriptors, HID Device Descriptor
// <i>and for memory allocation in the USB component.
//
// <h>Full/Low-speed (High-speed disabled)
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 64.
#define USBD_HID0_EP_INT_OUT_WMAXPACKETSIZE 64
// <o.0..7>Endpoint polling Interval (in ms) <1-255>
// <i>Specifies the frequency of requests initiated by USB Host for
// <i>function USBD_HIDn_GetReport.
#define USBD_HID0_EP_INT_OUT_BINTERVAL 1
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
//
// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 1024.
// <o.11..12>Additional transactions per microframe
// <i>Additional transactions improve communication performance.
// <0=>None <1=>1 additional <2=>2 additional
#define USBD_HID0_EP_INT_OUT_HS_WMAXPACKETSIZE 64
// <o.0..4>Endpoint polling Interval (in 125 us intervals)
// <i>Specifies the frequency of requests initiated by USB Host for
// <i>function USBD_HIDn_GetReport.
// <1=> 1 <2=> 2 <3=> 4 <4=> 8
// <5=> 16 <6=> 32 <7=> 64 <8=> 128
// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
// <13=>4096 <14=>8192 <15=>16384 <16=>32768
#define USBD_HID0_EP_INT_OUT_HS_BINTERVAL 1
// </h>
// </h>
// </h>
// </h>
// <h>Human Interface Device Class Settings
// <i>Parameters are used to create USB Descriptors, USB HID Report Descriptor
// <i>and for memory allocation in the USB component.
//
// <s.126>HID Interface String
#define USBD_HID0_STR_DESC L"XMC4200 CMSIS-DAP"
// <o.0..4>Number of Input Reports <1-32>
// <i>Configures max 'rid' value for USBD_HID0_GetReport and USBD_HID_GetReportTrigger
#define USBD_HID0_IN_REPORT_NUM 1
// <o.0..4>Number of Output Reports <1-32>
// <i>Configures max 'rid' value for USBD_HID0_SetReport
#define USBD_HID0_OUT_REPORT_NUM 1
// <o.0..15>Maximum Input Report Size (in bytes) <1-65535>
// <i>Allocates memory and configures 'len' value for USBD_HID0_GetReport
// <i>and USBD_HID_GetReportTrigger
#define USBD_HID0_IN_REPORT_MAX_SZ 64
// <o.0..15>Maximum Output Report Size (in bytes) <1-65535>
// <i>Allocates memory and configures 'len' value for USBD_HID0_SetReport
// <i>when rtype=HID_REPORT_OUTPUT.
#define USBD_HID0_OUT_REPORT_MAX_SZ 64
// <o.0..15>Maximum Feature Report Size (in bytes) <1-65535>
// <i>Allocates memory and configures 'len' value for USBD_HID0_SetReport
// <i>when rtype=HID_REPORT_FEATURE
#define USBD_HID0_FEAT_REPORT_MAX_SZ 1
// <e.0>Use User Provided HID Report Descriptor
// <i>User needs to provide HID Report Descriptor in array
// <i>const uint8_t usbd_hid0_report_descriptor[]
#define USBD_HID0_USER_REPORT_DESCRIPTOR 0
// <o>User Provided HID Report Descriptor Size (in bytes) <1-65535>
#define USBD_HID0_USER_REPORT_DESCRIPTOR_SIZE 33
// </e>
// </h>
// <h>OS Resources Settings
// <i>These settings are used to optimize usage of OS resources.
// <o>Human Interface Device Class Thread Stack Size <64-65536>
#define USBD_HID0_THREAD_STACK_SIZE 512
// Human Interface Device Class Thread Priority
#define USBD_HID0_THREAD_PRIORITY osPriorityAboveNormal
// </h>
// </h>