添加PAN159资料
This commit is contained in:
SXHome
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CMSIS-DAP USB HID Firmware for NXP LPC-Link-II board.
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+2583
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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||||
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
|
||||
|
||||
<SchemaVersion>1.0</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
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||||
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||||
<Extensions>
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||||
<cExt>*.c</cExt>
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||||
<aExt>*.s*; *.src; *.a*</aExt>
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||||
<oExt>*.obj</oExt>
|
||||
<lExt>*.lib</lExt>
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||||
<tExt>*.txt; *.h; *.inc</tExt>
|
||||
<pExt>*.plm</pExt>
|
||||
<CppX>*.cpp</CppX>
|
||||
<nMigrate>0</nMigrate>
|
||||
</Extensions>
|
||||
|
||||
<DaveTm>
|
||||
<dwLowDateTime>0</dwLowDateTime>
|
||||
<dwHighDateTime>0</dwHighDateTime>
|
||||
</DaveTm>
|
||||
|
||||
<Target>
|
||||
<TargetName>LPC4320 SPIFI</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
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||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<CLKADS>12000000</CLKADS>
|
||||
<OPTTT>
|
||||
<gFlags>1</gFlags>
|
||||
<BeepAtEnd>1</BeepAtEnd>
|
||||
<RunSim>0</RunSim>
|
||||
<RunTarget>1</RunTarget>
|
||||
<RunAbUc>0</RunAbUc>
|
||||
</OPTTT>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<FlashByte>65535</FlashByte>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
</OPTHX>
|
||||
<OPTLEX>
|
||||
<PageWidth>79</PageWidth>
|
||||
<PageLength>66</PageLength>
|
||||
<TabStop>8</TabStop>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
</OPTLEX>
|
||||
<ListingPage>
|
||||
<CreateCListing>1</CreateCListing>
|
||||
<CreateAListing>1</CreateAListing>
|
||||
<CreateLListing>1</CreateLListing>
|
||||
<CreateIListing>0</CreateIListing>
|
||||
<AsmCond>1</AsmCond>
|
||||
<AsmSymb>1</AsmSymb>
|
||||
<AsmXref>0</AsmXref>
|
||||
<CCond>1</CCond>
|
||||
<CCode>0</CCode>
|
||||
<CListInc>0</CListInc>
|
||||
<CSymb>0</CSymb>
|
||||
<LinkerCodeListing>0</LinkerCodeListing>
|
||||
</ListingPage>
|
||||
<OPTXL>
|
||||
<LMap>1</LMap>
|
||||
<LComments>1</LComments>
|
||||
<LGenerateSymbols>1</LGenerateSymbols>
|
||||
<LLibSym>1</LLibSym>
|
||||
<LLines>1</LLines>
|
||||
<LLocSym>1</LLocSym>
|
||||
<LPubSym>1</LPubSym>
|
||||
<LXref>0</LXref>
|
||||
<LExpSel>0</LExpSel>
|
||||
</OPTXL>
|
||||
<OPTFL>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<IsCurrentTarget>1</IsCurrentTarget>
|
||||
</OPTFL>
|
||||
<CpuCode>8</CpuCode>
|
||||
<DebugOpt>
|
||||
<uSim>0</uSim>
|
||||
<uTrg>1</uTrg>
|
||||
<sLdApp>1</sLdApp>
|
||||
<sGomain>1</sGomain>
|
||||
<sRbreak>1</sRbreak>
|
||||
<sRwatch>1</sRwatch>
|
||||
<sRmem>1</sRmem>
|
||||
<sRfunc>1</sRfunc>
|
||||
<sRbox>1</sRbox>
|
||||
<tLdApp>1</tLdApp>
|
||||
<tGomain>1</tGomain>
|
||||
<tRbreak>1</tRbreak>
|
||||
<tRwatch>1</tRwatch>
|
||||
<tRmem>1</tRmem>
|
||||
<tRfunc>0</tRfunc>
|
||||
<tRbox>1</tRbox>
|
||||
<tRtrace>1</tRtrace>
|
||||
<sRSysVw>1</sRSysVw>
|
||||
<tRSysVw>1</tRSysVw>
|
||||
<sRunDeb>0</sRunDeb>
|
||||
<sLrtime>0</sLrtime>
|
||||
<nTsel>1</nTsel>
|
||||
<sDll></sDll>
|
||||
<sDllPa></sDllPa>
|
||||
<sDlgDll></sDlgDll>
|
||||
<sDlgPa></sDlgPa>
|
||||
<sIfile></sIfile>
|
||||
<tDll></tDll>
|
||||
<tDllPa></tDllPa>
|
||||
<tDlgDll></tDlgDll>
|
||||
<tDlgPa></tDlgPa>
|
||||
<tIfile></tIfile>
|
||||
<pMon>BIN\UL2CM3.DLL</pMon>
|
||||
</DebugOpt>
|
||||
<TargetDriverDllRegistry>
|
||||
<SetRegEntry>
|
||||
<Number>0</Number>
|
||||
<Key>UL2CM3</Key>
|
||||
<Name>-UV0001BDE -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC180000000 -TP21 -TDS802F -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD10000000 -FC4000 -FN1 -FF0LPC18xx43xx_S25FL032 -FS014000000 -FL0400000</Name>
|
||||
</SetRegEntry>
|
||||
</TargetDriverDllRegistry>
|
||||
<Breakpoint/>
|
||||
<Tracepoint>
|
||||
<THDelay>0</THDelay>
|
||||
</Tracepoint>
|
||||
<DebugFlag>
|
||||
<trace>0</trace>
|
||||
<periodic>1</periodic>
|
||||
<aLwin>0</aLwin>
|
||||
<aCover>0</aCover>
|
||||
<aSer1>0</aSer1>
|
||||
<aSer2>0</aSer2>
|
||||
<aPa>0</aPa>
|
||||
<viewmode>0</viewmode>
|
||||
<vrSel>0</vrSel>
|
||||
<aSym>0</aSym>
|
||||
<aTbox>0</aTbox>
|
||||
<AscS1>0</AscS1>
|
||||
<AscS2>0</AscS2>
|
||||
<AscS3>0</AscS3>
|
||||
<aSer3>0</aSer3>
|
||||
<eProf>0</eProf>
|
||||
<aLa>0</aLa>
|
||||
<aPa1>0</aPa1>
|
||||
<AscS4>0</AscS4>
|
||||
<aSer4>0</aSer4>
|
||||
<StkLoc>0</StkLoc>
|
||||
<TrcWin>0</TrcWin>
|
||||
<newCpu>0</newCpu>
|
||||
<uProt>0</uProt>
|
||||
</DebugFlag>
|
||||
<LintExecutable></LintExecutable>
|
||||
<LintConfigFile></LintConfigFile>
|
||||
<bLintAuto>0</bLintAuto>
|
||||
</TargetOption>
|
||||
</Target>
|
||||
|
||||
<Group>
|
||||
<GroupName>Source</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>1</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\main.c</PathWithFileName>
|
||||
<FilenameWithoutPath>main.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>1</GroupNumber>
|
||||
<FileNumber>2</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\USBD_User_HID_0.c</PathWithFileName>
|
||||
<FilenameWithoutPath>USBD_User_HID_0.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>Documentation</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>2</GroupNumber>
|
||||
<FileNumber>3</FileNumber>
|
||||
<FileType>5</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>.\Abstract.txt</PathWithFileName>
|
||||
<FilenameWithoutPath>Abstract.txt</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>CMSIS DAP</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>0</RteFlg>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>4</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Source\DAP.c</PathWithFileName>
|
||||
<FilenameWithoutPath>DAP.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>5</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Source\JTAG_DP.c</PathWithFileName>
|
||||
<FilenameWithoutPath>JTAG_DP.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>6</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Source\SW_DP.c</PathWithFileName>
|
||||
<FilenameWithoutPath>SW_DP.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
<File>
|
||||
<GroupNumber>3</GroupNumber>
|
||||
<FileNumber>7</FileNumber>
|
||||
<FileType>1</FileType>
|
||||
<tvExp>0</tvExp>
|
||||
<Focus>0</Focus>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<bDave2>0</bDave2>
|
||||
<PathWithFileName>..\..\Source\SWO.c</PathWithFileName>
|
||||
<FilenameWithoutPath>SWO.c</FilenameWithoutPath>
|
||||
<RteFlg>0</RteFlg>
|
||||
<bShared>0</bShared>
|
||||
</File>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::CMSIS Driver</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
<Group>
|
||||
<GroupName>::USB</GroupName>
|
||||
<tvExp>1</tvExp>
|
||||
<tvExpOptDlg>0</tvExpOptDlg>
|
||||
<cbSel>0</cbSel>
|
||||
<RteFlg>1</RteFlg>
|
||||
</Group>
|
||||
|
||||
</ProjectOpt>
|
||||
+665
@@ -0,0 +1,665 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
|
||||
|
||||
<SchemaVersion>2.1</SchemaVersion>
|
||||
|
||||
<Header>### uVision Project, (C) Keil Software</Header>
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>LPC4320 SPIFI</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<TargetOption>
|
||||
<TargetCommonOption>
|
||||
<Device>LPC4320:Cortex-M4</Device>
|
||||
<Vendor>NXP</Vendor>
|
||||
<PackID>Keil.LPC4300_DFP.2.4.0</PackID>
|
||||
<PackURL>http://www.keil.com/pack/</PackURL>
|
||||
<Cpu>IRAM(0x10000000,0x18000) IRAM2(0x20000000,0x10000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE</Cpu>
|
||||
<FlashUtilSpec></FlashUtilSpec>
|
||||
<StartupFile></StartupFile>
|
||||
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD10000000 -FC1000)</FlashDriverDll>
|
||||
<DeviceId>0</DeviceId>
|
||||
<RegisterFile>$$Device:LPC4320$Device\Include\LPC43xx.h</RegisterFile>
|
||||
<MemoryEnv></MemoryEnv>
|
||||
<Cmp></Cmp>
|
||||
<Asm></Asm>
|
||||
<Linker></Linker>
|
||||
<OHString></OHString>
|
||||
<InfinionOptionDll></InfinionOptionDll>
|
||||
<SLE66CMisc></SLE66CMisc>
|
||||
<SLE66AMisc></SLE66AMisc>
|
||||
<SLE66LinkerMisc></SLE66LinkerMisc>
|
||||
<SFDFile>$$Device:LPC4320$SVD\LPC43xx.svd</SFDFile>
|
||||
<bCustSvd>0</bCustSvd>
|
||||
<UseEnv>0</UseEnv>
|
||||
<BinPath></BinPath>
|
||||
<IncludePath></IncludePath>
|
||||
<LibPath></LibPath>
|
||||
<RegisterFilePath></RegisterFilePath>
|
||||
<DBRegisterFilePath></DBRegisterFilePath>
|
||||
<TargetStatus>
|
||||
<Error>0</Error>
|
||||
<ExitCodeStop>0</ExitCodeStop>
|
||||
<ButtonStop>0</ButtonStop>
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>.\Objects\</OutputDirectory>
|
||||
<OutputName>CMSIS_DAP</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>0</CreateHexFile>
|
||||
<DebugInformation>1</DebugInformation>
|
||||
<BrowseInformation>1</BrowseInformation>
|
||||
<ListingPath>.\Listings\</ListingPath>
|
||||
<HexFormatSelection>1</HexFormatSelection>
|
||||
<Merge32K>0</Merge32K>
|
||||
<CreateBatchFile>0</CreateBatchFile>
|
||||
<BeforeCompile>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopU1X>0</nStopU1X>
|
||||
<nStopU2X>0</nStopU2X>
|
||||
</BeforeCompile>
|
||||
<BeforeMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopB1X>0</nStopB1X>
|
||||
<nStopB2X>0</nStopB2X>
|
||||
</BeforeMake>
|
||||
<AfterMake>
|
||||
<RunUserProg1>0</RunUserProg1>
|
||||
<RunUserProg2>0</RunUserProg2>
|
||||
<UserProg1Name></UserProg1Name>
|
||||
<UserProg2Name></UserProg2Name>
|
||||
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
|
||||
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
|
||||
<nStopA1X>0</nStopA1X>
|
||||
<nStopA2X>0</nStopA2X>
|
||||
</AfterMake>
|
||||
<SelectedForBatchBuild>0</SelectedForBatchBuild>
|
||||
<SVCSIdString></SVCSIdString>
|
||||
</TargetCommonOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>0</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>1</IncludeInBuild>
|
||||
<AlwaysBuild>0</AlwaysBuild>
|
||||
<GenerateAssemblyFile>0</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>0</AssembleAssemblyFile>
|
||||
<PublicsOnly>0</PublicsOnly>
|
||||
<StopOnExitCode>3</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<DllOption>
|
||||
<SimDllName>SARMCM3.DLL</SimDllName>
|
||||
<SimDllArguments> -MPU</SimDllArguments>
|
||||
<SimDlgDll>DCM.DLL</SimDlgDll>
|
||||
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
|
||||
<TargetDllName>SARMCM3.DLL</TargetDllName>
|
||||
<TargetDllArguments> -MPU</TargetDllArguments>
|
||||
<TargetDlgDll>TCM.DLL</TargetDlgDll>
|
||||
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
|
||||
</DllOption>
|
||||
<DebugOption>
|
||||
<OPTHX>
|
||||
<HexSelection>1</HexSelection>
|
||||
<HexRangeLowAddress>0</HexRangeLowAddress>
|
||||
<HexRangeHighAddress>0</HexRangeHighAddress>
|
||||
<HexOffset>0</HexOffset>
|
||||
<Oh166RecLen>16</Oh166RecLen>
|
||||
</OPTHX>
|
||||
<Simulator>
|
||||
<UseSimulator>0</UseSimulator>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>1</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<LimitSpeedToRealTime>0</LimitSpeedToRealTime>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Simulator>
|
||||
<Target>
|
||||
<UseTarget>1</UseTarget>
|
||||
<LoadApplicationAtStartup>1</LoadApplicationAtStartup>
|
||||
<RunToMain>1</RunToMain>
|
||||
<RestoreBreakpoints>1</RestoreBreakpoints>
|
||||
<RestoreWatchpoints>1</RestoreWatchpoints>
|
||||
<RestoreMemoryDisplay>1</RestoreMemoryDisplay>
|
||||
<RestoreFunctions>0</RestoreFunctions>
|
||||
<RestoreToolbox>1</RestoreToolbox>
|
||||
<RestoreTracepoints>1</RestoreTracepoints>
|
||||
<RestoreSysVw>1</RestoreSysVw>
|
||||
</Target>
|
||||
<RunDebugAfterBuild>0</RunDebugAfterBuild>
|
||||
<TargetSelection>1</TargetSelection>
|
||||
<SimDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
</SimDlls>
|
||||
<TargetDlls>
|
||||
<CpuDll></CpuDll>
|
||||
<CpuDllArguments></CpuDllArguments>
|
||||
<PeripheralDll></PeripheralDll>
|
||||
<PeripheralDllArguments></PeripheralDllArguments>
|
||||
<InitializationFile></InitializationFile>
|
||||
<Driver>BIN\UL2CM3.DLL</Driver>
|
||||
</TargetDlls>
|
||||
</DebugOption>
|
||||
<Utilities>
|
||||
<Flash1>
|
||||
<UseTargetDll>1</UseTargetDll>
|
||||
<UseExternalTool>0</UseExternalTool>
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
<pFcArmRoot></pFcArmRoot>
|
||||
<FcArmLst>0</FcArmLst>
|
||||
</Utilities>
|
||||
<TargetArmAds>
|
||||
<ArmAdsMisc>
|
||||
<GenerateListings>0</GenerateListings>
|
||||
<asHll>1</asHll>
|
||||
<asAsm>1</asAsm>
|
||||
<asMacX>1</asMacX>
|
||||
<asSyms>1</asSyms>
|
||||
<asFals>1</asFals>
|
||||
<asDbgD>1</asDbgD>
|
||||
<asForm>1</asForm>
|
||||
<ldLst>0</ldLst>
|
||||
<ldmm>1</ldmm>
|
||||
<ldXref>1</ldXref>
|
||||
<BigEnd>0</BigEnd>
|
||||
<AdsALst>1</AdsALst>
|
||||
<AdsACrf>1</AdsACrf>
|
||||
<AdsANop>0</AdsANop>
|
||||
<AdsANot>0</AdsANot>
|
||||
<AdsLLst>1</AdsLLst>
|
||||
<AdsLmap>1</AdsLmap>
|
||||
<AdsLcgr>1</AdsLcgr>
|
||||
<AdsLsym>1</AdsLsym>
|
||||
<AdsLszi>1</AdsLszi>
|
||||
<AdsLtoi>1</AdsLtoi>
|
||||
<AdsLsun>1</AdsLsun>
|
||||
<AdsLven>1</AdsLven>
|
||||
<AdsLsxf>1</AdsLsxf>
|
||||
<RvctClst>0</RvctClst>
|
||||
<GenPPlst>0</GenPPlst>
|
||||
<AdsCpuType>"Cortex-M4"</AdsCpuType>
|
||||
<RvctDeviceName></RvctDeviceName>
|
||||
<mOS>1</mOS>
|
||||
<uocRom>0</uocRom>
|
||||
<uocRam>0</uocRam>
|
||||
<hadIROM>0</hadIROM>
|
||||
<hadIRAM>1</hadIRAM>
|
||||
<hadXRAM>0</hadXRAM>
|
||||
<uocXRam>0</uocXRam>
|
||||
<RvdsVP>1</RvdsVP>
|
||||
<hadIRAM2>1</hadIRAM2>
|
||||
<hadIROM2>0</hadIROM2>
|
||||
<StupSel>1</StupSel>
|
||||
<useUlib>1</useUlib>
|
||||
<EndSel>0</EndSel>
|
||||
<uLtcg>0</uLtcg>
|
||||
<RoSelD>0</RoSelD>
|
||||
<RwSelD>3</RwSelD>
|
||||
<CodeSel>0</CodeSel>
|
||||
<OptFeed>0</OptFeed>
|
||||
<NoZi1>0</NoZi1>
|
||||
<NoZi2>0</NoZi2>
|
||||
<NoZi3>0</NoZi3>
|
||||
<NoZi4>0</NoZi4>
|
||||
<NoZi5>0</NoZi5>
|
||||
<Ro1Chk>1</Ro1Chk>
|
||||
<Ro2Chk>0</Ro2Chk>
|
||||
<Ro3Chk>0</Ro3Chk>
|
||||
<Ir1Chk>0</Ir1Chk>
|
||||
<Ir2Chk>0</Ir2Chk>
|
||||
<Ra1Chk>0</Ra1Chk>
|
||||
<Ra2Chk>0</Ra2Chk>
|
||||
<Ra3Chk>0</Ra3Chk>
|
||||
<Im1Chk>1</Im1Chk>
|
||||
<Im2Chk>0</Im2Chk>
|
||||
<OnChipMemories>
|
||||
<Ocm1>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm1>
|
||||
<Ocm2>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm2>
|
||||
<Ocm3>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm3>
|
||||
<Ocm4>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm4>
|
||||
<Ocm5>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm5>
|
||||
<Ocm6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</Ocm6>
|
||||
<IRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x10000000</StartAddress>
|
||||
<Size>0x18000</Size>
|
||||
</IRAM>
|
||||
<IROM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</IROM>
|
||||
<XRAM>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</XRAM>
|
||||
<OCR_RVCT1>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x14000000</StartAddress>
|
||||
<Size>0x400000</Size>
|
||||
</OCR_RVCT1>
|
||||
<OCR_RVCT2>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT2>
|
||||
<OCR_RVCT3>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT3>
|
||||
<OCR_RVCT4>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT4>
|
||||
<OCR_RVCT5>
|
||||
<Type>1</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT5>
|
||||
<OCR_RVCT6>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT6>
|
||||
<OCR_RVCT7>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT7>
|
||||
<OCR_RVCT8>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x0</StartAddress>
|
||||
<Size>0x0</Size>
|
||||
</OCR_RVCT8>
|
||||
<OCR_RVCT9>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x10000000</StartAddress>
|
||||
<Size>0x18000</Size>
|
||||
</OCR_RVCT9>
|
||||
<OCR_RVCT10>
|
||||
<Type>0</Type>
|
||||
<StartAddress>0x20000000</StartAddress>
|
||||
<Size>0x10000</Size>
|
||||
</OCR_RVCT10>
|
||||
</OnChipMemories>
|
||||
<RvctStartVector></RvctStartVector>
|
||||
</ArmAdsMisc>
|
||||
<Cads>
|
||||
<interw>1</interw>
|
||||
<Optim>4</Optim>
|
||||
<oTime>0</oTime>
|
||||
<SplitLS>0</SplitLS>
|
||||
<OneElfS>0</OneElfS>
|
||||
<Strict>0</Strict>
|
||||
<EnumInt>0</EnumInt>
|
||||
<PlainCh>0</PlainCh>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>0</uThumb>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<uC99>0</uC99>
|
||||
<useXO>0</useXO>
|
||||
<v6Lang>0</v6Lang>
|
||||
<v6LangP>0</v6LangP>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>.;..\..\Include</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
<interw>1</interw>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<thumb>0</thumb>
|
||||
<SplitLS>0</SplitLS>
|
||||
<SwStkChk>0</SwStkChk>
|
||||
<NoWarn>0</NoWarn>
|
||||
<uSurpInc>0</uSurpInc>
|
||||
<useXO>0</useXO>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define></Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Aads>
|
||||
<LDads>
|
||||
<umfTarg>1</umfTarg>
|
||||
<Ropi>0</Ropi>
|
||||
<Rwpi>0</Rwpi>
|
||||
<noStLib>0</noStLib>
|
||||
<RepFail>1</RepFail>
|
||||
<useFile>0</useFile>
|
||||
<TextAddressRange>0x00000000</TextAddressRange>
|
||||
<DataAddressRange>0x10000000</DataAddressRange>
|
||||
<pXoBase></pXoBase>
|
||||
<ScatterFile></ScatterFile>
|
||||
<IncludeLibs></IncludeLibs>
|
||||
<IncludeLibsPath></IncludeLibsPath>
|
||||
<Misc></Misc>
|
||||
<LinkerInputFile></LinkerInputFile>
|
||||
<DisabledWarnings></DisabledWarnings>
|
||||
</LDads>
|
||||
</TargetArmAds>
|
||||
</TargetOption>
|
||||
<Groups>
|
||||
<Group>
|
||||
<GroupName>Source</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\main.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>USBD_User_HID_0.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>.\USBD_User_HID_0.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>Documentation</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>Abstract.txt</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>.\Abstract.txt</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>CMSIS DAP</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>DAP.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Source\DAP.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>JTAG_DP.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Source\JTAG_DP.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>SW_DP.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Source\SW_DP.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>SWO.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\..\Source\SWO.c</FilePath>
|
||||
<FileOption>
|
||||
<CommonProperty>
|
||||
<UseCPPCompiler>2</UseCPPCompiler>
|
||||
<RVCTCodeConst>0</RVCTCodeConst>
|
||||
<RVCTZI>0</RVCTZI>
|
||||
<RVCTOtherData>0</RVCTOtherData>
|
||||
<ModuleSelection>0</ModuleSelection>
|
||||
<IncludeInBuild>2</IncludeInBuild>
|
||||
<AlwaysBuild>2</AlwaysBuild>
|
||||
<GenerateAssemblyFile>2</GenerateAssemblyFile>
|
||||
<AssembleAssemblyFile>2</AssembleAssemblyFile>
|
||||
<PublicsOnly>2</PublicsOnly>
|
||||
<StopOnExitCode>11</StopOnExitCode>
|
||||
<CustomArgument></CustomArgument>
|
||||
<IncludeLibraryModules></IncludeLibraryModules>
|
||||
<ComprImg>1</ComprImg>
|
||||
</CommonProperty>
|
||||
<FileArmAds>
|
||||
<Cads>
|
||||
<interw>2</interw>
|
||||
<Optim>0</Optim>
|
||||
<oTime>2</oTime>
|
||||
<SplitLS>2</SplitLS>
|
||||
<OneElfS>2</OneElfS>
|
||||
<Strict>2</Strict>
|
||||
<EnumInt>2</EnumInt>
|
||||
<PlainCh>2</PlainCh>
|
||||
<Ropi>2</Ropi>
|
||||
<Rwpi>2</Rwpi>
|
||||
<wLevel>2</wLevel>
|
||||
<uThumb>2</uThumb>
|
||||
<uSurpInc>2</uSurpInc>
|
||||
<uC99>2</uC99>
|
||||
<useXO>2</useXO>
|
||||
<v6Lang>0</v6Lang>
|
||||
<v6LangP>0</v6LangP>
|
||||
<VariousControls>
|
||||
<MiscControls></MiscControls>
|
||||
<Define>USART_PORT=1</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath></IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
</FileArmAds>
|
||||
</FileOption>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::CMSIS Driver</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::Device</GroupName>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>::USB</GroupName>
|
||||
</Group>
|
||||
</Groups>
|
||||
</Target>
|
||||
</Targets>
|
||||
|
||||
<RTE>
|
||||
<apis>
|
||||
<api Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USART" exclusive="0">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</api>
|
||||
<api Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USB Device" exclusive="0">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</api>
|
||||
<api Capiversion="1.0" Cclass="CMSIS" Cgroup="RTOS" exclusive="1">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</api>
|
||||
</apis>
|
||||
<components>
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="4.1.0" condition="CMSIS Core">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvendor="ARM" Cversion="4.78.0" condition="Cortex-M Device Startup">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="CORE" Cvendor="Keil" Cversion="6.4.0" condition="USB Core">
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Cvendor="Keil" Cversion="6.4.0" condition="USB Core and Device Driver" maxInstances="4">
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Csub="HID" Cvendor="Keil" Cversion="6.4.0" condition="USB Device" maxInstances="4">
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USART" Cvendor="Keil" Cversion="2.07" condition="LPC4300 CMSIS SCU GPDMA">
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Capiversion="2.01" Cclass="CMSIS Driver" Cgroup="USB Device" Csub="USB0" Cvendor="Keil" Cversion="2.07" condition="LPC4300 CMSIS SCU">
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="GPDMA" Cvendor="Keil" Cversion="1.03" condition="LPC4300 CMSIS">
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="SCU" Cvendor="Keil" Cversion="1.00" condition="LPC4300 CMSIS">
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS">
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI">
|
||||
<c>
|
||||
<Define>USE_SPIFI=1</Define>
|
||||
</c>
|
||||
<asm>
|
||||
<Define>NO_CRP</Define>
|
||||
</asm>
|
||||
</targetInfo>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
<files>
|
||||
<file attr="config" category="source" name="CMSIS\RTOS\RTX\Templates\RTX_Conf_CM.c" version="4.70.1">
|
||||
<instance index="0">RTE\CMSIS\RTX_Conf_CM.c</instance>
|
||||
<component Cclass="CMSIS" Cgroup="RTOS" Csub="Keil RTX" Cvendor="ARM" Cversion="4.78.0" condition="Cortex-M Device Startup"/>
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="4.3.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="header" name="RTE_Driver\Config\RTE_Device.h" version="2.00">
|
||||
<instance index="0">RTE\Device\LPC4320_Cortex-M4\RTE_Device.h</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS"/>
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" condition="CM4 ARM Compiler" name="Device\Source\ARM\startup_LPC43xx.s">
|
||||
<instance index="0">RTE\Device\LPC4320_Cortex-M4\startup_LPC43xx.s</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS"/>
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" condition="CM4" name="Device\Source\system_LPC43xx.c">
|
||||
<instance index="0">RTE\Device\LPC4320_Cortex-M4\system_LPC43xx.c</instance>
|
||||
<component Cclass="Device" Cgroup="Startup" Cvendor="Keil" Cversion="1.0.0" condition="LPC4300 CMSIS"/>
|
||||
<package name="LPC4300_DFP" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="2.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" name="USB\Config\USBD_Config.c" version="5.00">
|
||||
<instance index="0">RTE\USB\USBD_Config_0.c</instance>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Cvendor="Keil" Cversion="6.4.0" condition="USB Core and Device Driver" maxInstances="4"/>
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
<file attr="config" category="source" name="USB\Config\USBD_Config_HID.h" version="5.0.1">
|
||||
<instance index="0">RTE\USB\USBD_Config_HID_0.h</instance>
|
||||
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Device" Csub="HID" Cvendor="Keil" Cversion="6.4.0" condition="USB Device" maxInstances="4"/>
|
||||
<package name="MDK-Middleware" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="Keil" version="6.4.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="LPC4320 SPIFI"/>
|
||||
</targetInfos>
|
||||
</file>
|
||||
</files>
|
||||
</RTE>
|
||||
|
||||
</Project>
|
||||
@@ -0,0 +1,506 @@
|
||||
/**************************************************************************//**
|
||||
* @file DAP_config.h
|
||||
* @brief CMSIS-DAP Configuration File for LPC-Link-II
|
||||
* @version V1.10
|
||||
* @date 20. May 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __DAP_CONFIG_H__
|
||||
#define __DAP_CONFIG_H__
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_Debug_gr CMSIS-DAP Debug Unit Information
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
Provides definitions about the hardware and configuration of the Debug Unit.
|
||||
|
||||
This information includes:
|
||||
- Definition of Cortex-M processor parameters used in CMSIS-DAP Debug Unit.
|
||||
- Debug Unit communication packet size.
|
||||
- Debug Access Port communication mode (JTAG or SWD).
|
||||
- Optional information about a connected Target Device (for Evaluation Boards).
|
||||
*/
|
||||
|
||||
#include "LPC43xx.h" // Debug Unit Cortex-M Processor Header File
|
||||
|
||||
/// Processor Clock of the Cortex-M MCU used in the Debug Unit.
|
||||
/// This value is used to calculate the SWD/JTAG clock speed.
|
||||
#define CPU_CLOCK 180000000U ///< Specifies the CPU Clock in Hz
|
||||
|
||||
/// Number of processor cycles for I/O Port write operations.
|
||||
/// This value is used to calculate the SWD/JTAG clock speed that is generated with I/O
|
||||
/// Port write operations in the Debug Unit by a Cortex-M MCU. Most Cortex-M processors
|
||||
/// require 2 processor cycles for a I/O Port Write operation. If the Debug Unit uses
|
||||
/// a Cortex-M0+ processor with high-speed peripheral I/O only 1 processor cycle might be
|
||||
/// required.
|
||||
#define IO_PORT_WRITE_CYCLES 2U ///< I/O Cycles: 2=default, 1=Cortex-M0+ fast I/0
|
||||
|
||||
/// Indicate that Serial Wire Debug (SWD) communication mode is available at the Debug Access Port.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define DAP_SWD 1 ///< SWD Mode: 1 = available, 0 = not available
|
||||
|
||||
/// Indicate that JTAG communication mode is available at the Debug Port.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define DAP_JTAG 1 ///< JTAG Mode: 1 = available, 0 = not available.
|
||||
|
||||
/// Configure maximum number of JTAG devices on the scan chain connected to the Debug Access Port.
|
||||
/// This setting impacts the RAM requirements of the Debug Unit. Valid range is 1 .. 255.
|
||||
#define DAP_JTAG_DEV_CNT 8U ///< Maximum number of JTAG devices on scan chain
|
||||
|
||||
/// Default communication mode on the Debug Access Port.
|
||||
/// Used for the command \ref DAP_Connect when Port Default mode is selected.
|
||||
#define DAP_DEFAULT_PORT 1U ///< Default JTAG/SWJ Port Mode: 1 = SWD, 2 = JTAG.
|
||||
|
||||
/// Default communication speed on the Debug Access Port for SWD and JTAG mode.
|
||||
/// Used to initialize the default SWD/JTAG clock frequency.
|
||||
/// The command \ref DAP_SWJ_Clock can be used to overwrite this default setting.
|
||||
#define DAP_DEFAULT_SWJ_CLOCK 1000000U ///< Default SWD/JTAG clock frequency in Hz.
|
||||
|
||||
/// Maximum Package Size for Command and Response data.
|
||||
/// This configuration settings is used to optimized the communication performance with the
|
||||
/// debugger and depends on the USB peripheral. Change setting to 1024 for High-Speed USB.
|
||||
#define DAP_PACKET_SIZE 1024U ///< USB: 64 = Full-Speed, 1024 = High-Speed.
|
||||
|
||||
/// Maximum Package Buffers for Command and Response data.
|
||||
/// This configuration settings is used to optimized the communication performance with the
|
||||
/// debugger and depends on the USB peripheral. For devices with limited RAM or USB buffer the
|
||||
/// setting can be reduced (valid range is 1 .. 255). Change setting to 4 for High-Speed USB.
|
||||
#define DAP_PACKET_COUNT 4U ///< Buffers: 64 = Full-Speed, 4 = High-Speed.
|
||||
|
||||
/// Indicate that UART Serial Wire Output (SWO) trace is available.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define SWO_UART 1 ///< SWO UART: 1 = available, 0 = not available
|
||||
|
||||
/// Maximum SWO UART Baudrate
|
||||
#define SWO_UART_MAX_BAUDRATE 10000000U ///< SWO UART Maximum Baudrate in Hz
|
||||
|
||||
/// Indicate that Manchester Serial Wire Output (SWO) trace is available.
|
||||
/// This information is returned by the command \ref DAP_Info as part of <b>Capabilities</b>.
|
||||
#define SWO_MANCHESTER 0 ///< SWO Manchester: 1 = available, 0 = not available
|
||||
|
||||
/// SWO Trace Buffer Size.
|
||||
#define SWO_BUFFER_SIZE 8192U ///< SWO Trace Buffer Size in bytes (must be 2^n)
|
||||
|
||||
|
||||
/// Debug Unit is connected to fixed Target Device.
|
||||
/// The Debug Unit may be part of an evaluation board and always connected to a fixed
|
||||
/// known device. In this case a Device Vendor and Device Name string is stored which
|
||||
/// may be used by the debugger or IDE to configure device parameters.
|
||||
#define TARGET_DEVICE_FIXED 0 ///< Target Device: 1 = known, 0 = unknown;
|
||||
|
||||
#if TARGET_DEVICE_FIXED
|
||||
#define TARGET_DEVICE_VENDOR "" ///< String indicating the Silicon Vendor
|
||||
#define TARGET_DEVICE_NAME "" ///< String indicating the Target Device
|
||||
#endif
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
// LPC43xx peripheral register bit masks (used by macros)
|
||||
#define CCU_CLK_CFG_RUN (1U << 0)
|
||||
#define CCU_CLK_CFG_AUTO (1U << 1)
|
||||
#define CCU_CLK_STAT_RUN (1U << 0)
|
||||
#define SCU_SFS_EPD (1U << 3)
|
||||
#define SCU_SFS_EPUN (1U << 4)
|
||||
#define SCU_SFS_EHS (1U << 5)
|
||||
#define SCU_SFS_EZI (1U << 6)
|
||||
#define SCU_SFS_ZIF (1U << 7)
|
||||
|
||||
|
||||
// Debug Port I/O Pins
|
||||
|
||||
// SWCLK/TCK Pin P1_17: GPIO0[12]
|
||||
#define PIN_SWCLK_TCK_PORT 0
|
||||
#define PIN_SWCLK_TCK_BIT 12
|
||||
|
||||
// SWDIO/TMS Pin P1_6: GPIO1[9]
|
||||
#define PIN_SWDIO_TMS_PORT 1
|
||||
#define PIN_SWDIO_TMS_BIT 9
|
||||
|
||||
// SWDIO Output Enable Pin P1_5: GPIO1[8]
|
||||
#define PIN_SWDIO_OE_PORT 1
|
||||
#define PIN_SWDIO_OE_BIT 8
|
||||
|
||||
// TDI Pin P1_18: GPIO0[13]
|
||||
#define PIN_TDI_PORT 0
|
||||
#define PIN_TDI_BIT 13
|
||||
|
||||
// TDO Pin P1_14: GPIO1[7]
|
||||
#define PIN_TDO_PORT 1
|
||||
#define PIN_TDO_BIT 7
|
||||
|
||||
// nTRST Pin Not available
|
||||
#define PIN_nTRST_PORT
|
||||
#define PIN_nTRST_BIT
|
||||
|
||||
// nRESET Pin P2_5: GPIO5[5]
|
||||
#define PIN_nRESET_PORT 5
|
||||
#define PIN_nRESET_BIT 5
|
||||
|
||||
// nRESET Output Enable Pin P2_6: GPIO5[6]
|
||||
#define PIN_nRESET_OE_PORT 5
|
||||
#define PIN_nRESET_OE_BIT 6
|
||||
|
||||
|
||||
// Debug Unit LEDs
|
||||
|
||||
// Connected LED P1_1: GPIO0[8]
|
||||
#define LED_CONNECTED_PORT 0
|
||||
#define LED_CONNECTED_BIT 8
|
||||
|
||||
// Target Running LED Not available
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_PortIO_gr CMSIS-DAP Hardware I/O Pin Access
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
Standard I/O Pins of the CMSIS-DAP Hardware Debug Port support standard JTAG mode
|
||||
and Serial Wire Debug (SWD) mode. In SWD mode only 2 pins are required to implement the debug
|
||||
interface of a device. The following I/O Pins are provided:
|
||||
|
||||
JTAG I/O Pin | SWD I/O Pin | CMSIS-DAP Hardware pin mode
|
||||
---------------------------- | -------------------- | ---------------------------------------------
|
||||
TCK: Test Clock | SWCLK: Clock | Output Push/Pull
|
||||
TMS: Test Mode Select | SWDIO: Data I/O | Output Push/Pull; Input (for receiving data)
|
||||
TDI: Test Data Input | | Output Push/Pull
|
||||
TDO: Test Data Output | | Input
|
||||
nTRST: Test Reset (optional) | | Output Open Drain with pull-up resistor
|
||||
nRESET: Device Reset | nRESET: Device Reset | Output Open Drain with pull-up resistor
|
||||
|
||||
|
||||
DAP Hardware I/O Pin Access Functions
|
||||
-------------------------------------
|
||||
The various I/O Pins are accessed by functions that implement the Read, Write, Set, or Clear to
|
||||
these I/O Pins.
|
||||
|
||||
For the SWDIO I/O Pin there are additional functions that are called in SWD I/O mode only.
|
||||
This functions are provided to achieve faster I/O that is possible with some advanced GPIO
|
||||
peripherals that can independently write/read a single I/O pin without affecting any other pins
|
||||
of the same I/O port. The following SWDIO I/O Pin functions are provided:
|
||||
- \ref PIN_SWDIO_OUT_ENABLE to enable the output mode from the DAP hardware.
|
||||
- \ref PIN_SWDIO_OUT_DISABLE to enable the input mode to the DAP hardware.
|
||||
- \ref PIN_SWDIO_IN to read from the SWDIO I/O pin with utmost possible speed.
|
||||
- \ref PIN_SWDIO_OUT to write to the SWDIO I/O pin with utmost possible speed.
|
||||
*/
|
||||
|
||||
|
||||
// Configure DAP I/O pins ------------------------------
|
||||
|
||||
// LPC-Link-II HW uses buffers for debug port pins. Therefore it is not
|
||||
// possible to disable outputs SWCLK/TCK, TDI and they are left active.
|
||||
// Only SWDIO/TMS output can be disabled but it is also left active.
|
||||
// nRESET is configured for open drain mode.
|
||||
|
||||
/** Setup JTAG I/O pins: TCK, TMS, TDI, TDO, nTRST, and nRESET.
|
||||
Configures the DAP Hardware I/O pins for JTAG mode:
|
||||
- TCK, TMS, TDI, nTRST, nRESET to output mode and set to high level.
|
||||
- TDO to input mode.
|
||||
*/
|
||||
static __inline void PORT_JTAG_SETUP (void) {
|
||||
LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = 0U;
|
||||
LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = ~(1U << PIN_TDI_BIT);
|
||||
}
|
||||
|
||||
/** Setup SWD I/O pins: SWCLK, SWDIO, and nRESET.
|
||||
Configures the DAP Hardware I/O pins for Serial Wire Debug (SWD) mode:
|
||||
- SWCLK, SWDIO, nRESET to output mode and set to default high level.
|
||||
- TDI, nTRST to HighZ mode (pins are unused in SWD mode).
|
||||
*/
|
||||
static __inline void PORT_SWD_SETUP (void) {
|
||||
LPC_GPIO_PORT->MASK[PIN_TDI_PORT] = 0U;
|
||||
LPC_GPIO_PORT->MASK[PIN_SWDIO_TMS_PORT] = ~(1U << PIN_SWDIO_TMS_BIT);
|
||||
}
|
||||
|
||||
/** Disable JTAG/SWD I/O Pins.
|
||||
Disables the DAP Hardware I/O pins which configures:
|
||||
- TCK/SWCLK, TMS/SWDIO, TDI, TDO, nTRST, nRESET to High-Z mode.
|
||||
*/
|
||||
static __inline void PORT_OFF (void) {
|
||||
LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = (1U << PIN_SWCLK_TCK_BIT);
|
||||
LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = (1U << PIN_SWDIO_TMS_BIT);
|
||||
LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = (1U << PIN_SWDIO_OE_BIT);
|
||||
LPC_GPIO_PORT->SET[PIN_TDI_PORT] = (1U << PIN_TDI_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
|
||||
LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
|
||||
}
|
||||
|
||||
|
||||
// SWCLK/TCK I/O pin -------------------------------------
|
||||
|
||||
/** SWCLK/TCK I/O pin: Get Input.
|
||||
\return Current status of the SWCLK/TCK DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_SWCLK_TCK_IN (void) {
|
||||
return ((LPC_GPIO_PORT->PIN[PIN_SWCLK_TCK_PORT] >> PIN_SWCLK_TCK_BIT) & 1U);
|
||||
}
|
||||
|
||||
/** SWCLK/TCK I/O pin: Set Output to High.
|
||||
Set the SWCLK/TCK DAP hardware I/O pin to high level.
|
||||
*/
|
||||
static __forceinline void PIN_SWCLK_TCK_SET (void) {
|
||||
LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = 1U << PIN_SWCLK_TCK_BIT;
|
||||
}
|
||||
|
||||
/** SWCLK/TCK I/O pin: Set Output to Low.
|
||||
Set the SWCLK/TCK DAP hardware I/O pin to low level.
|
||||
*/
|
||||
static __forceinline void PIN_SWCLK_TCK_CLR (void) {
|
||||
LPC_GPIO_PORT->CLR[PIN_SWCLK_TCK_PORT] = 1U << PIN_SWCLK_TCK_BIT;
|
||||
}
|
||||
|
||||
|
||||
// SWDIO/TMS Pin I/O --------------------------------------
|
||||
|
||||
/** SWDIO/TMS I/O pin: Get Input.
|
||||
\return Current status of the SWDIO/TMS DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_SWDIO_TMS_IN (void) {
|
||||
return ((LPC_GPIO_PORT->PIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT) & 1U);
|
||||
}
|
||||
|
||||
/** SWDIO/TMS I/O pin: Set Output to High.
|
||||
Set the SWDIO/TMS DAP hardware I/O pin to high level.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_TMS_SET (void) {
|
||||
LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = 1U << PIN_SWDIO_TMS_BIT;
|
||||
}
|
||||
|
||||
/** SWDIO/TMS I/O pin: Set Output to Low.
|
||||
Set the SWDIO/TMS DAP hardware I/O pin to low level.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_TMS_CLR (void) {
|
||||
LPC_GPIO_PORT->CLR[PIN_SWDIO_TMS_PORT] = 1U << PIN_SWDIO_TMS_BIT;
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Get Input (used in SWD mode only).
|
||||
\return Current status of the SWDIO DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_SWDIO_IN (void) {
|
||||
return (LPC_GPIO_PORT->MPIN[PIN_SWDIO_TMS_PORT] >> PIN_SWDIO_TMS_BIT);
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Set Output (used in SWD mode only).
|
||||
\param bit Output value for the SWDIO DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_OUT (uint32_t bit) {
|
||||
LPC_GPIO_PORT->MPIN[PIN_SWDIO_TMS_PORT] = bit << PIN_SWDIO_TMS_BIT;
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Switch to Output mode (used in SWD mode only).
|
||||
Configure the SWDIO DAP hardware I/O pin to output mode. This function is
|
||||
called prior \ref PIN_SWDIO_OUT function calls.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_OUT_ENABLE (void) {
|
||||
LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = 1U << PIN_SWDIO_OE_BIT;
|
||||
}
|
||||
|
||||
/** SWDIO I/O pin: Switch to Input mode (used in SWD mode only).
|
||||
Configure the SWDIO DAP hardware I/O pin to input mode. This function is
|
||||
called prior \ref PIN_SWDIO_IN function calls.
|
||||
*/
|
||||
static __forceinline void PIN_SWDIO_OUT_DISABLE (void) {
|
||||
LPC_GPIO_PORT->CLR[PIN_SWDIO_OE_PORT] = 1U << PIN_SWDIO_OE_BIT;
|
||||
}
|
||||
|
||||
|
||||
// TDI Pin I/O ---------------------------------------------
|
||||
|
||||
/** TDI I/O pin: Get Input.
|
||||
\return Current status of the TDI DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_TDI_IN (void) {
|
||||
return ((LPC_GPIO_PORT->PIN [PIN_TDI_PORT] >> PIN_TDI_BIT) & 1U);
|
||||
}
|
||||
|
||||
/** TDI I/O pin: Set Output.
|
||||
\param bit Output value for the TDI DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline void PIN_TDI_OUT (uint32_t bit) {
|
||||
LPC_GPIO_PORT->MPIN[PIN_TDI_PORT] = bit << PIN_TDI_BIT;
|
||||
}
|
||||
|
||||
|
||||
// TDO Pin I/O ---------------------------------------------
|
||||
|
||||
/** TDO I/O pin: Get Input.
|
||||
\return Current status of the TDO DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_TDO_IN (void) {
|
||||
return ((LPC_GPIO_PORT->PIN[PIN_TDO_PORT] >> PIN_TDO_BIT) & 1U);
|
||||
}
|
||||
|
||||
|
||||
// nTRST Pin I/O -------------------------------------------
|
||||
|
||||
/** nTRST I/O pin: Get Input.
|
||||
\return Current status of the nTRST DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_nTRST_IN (void) {
|
||||
return (0U); // Not available
|
||||
}
|
||||
|
||||
/** nTRST I/O pin: Set Output.
|
||||
\param bit JTAG TRST Test Reset pin status:
|
||||
- 0: issue a JTAG TRST Test Reset.
|
||||
- 1: release JTAG TRST Test Reset.
|
||||
*/
|
||||
static __forceinline void PIN_nTRST_OUT (uint32_t bit) {
|
||||
; // Not available
|
||||
}
|
||||
|
||||
// nRESET Pin I/O------------------------------------------
|
||||
|
||||
/** nRESET I/O pin: Get Input.
|
||||
\return Current status of the nRESET DAP hardware I/O pin.
|
||||
*/
|
||||
static __forceinline uint32_t PIN_nRESET_IN (void) {
|
||||
return ((LPC_GPIO_PORT->PIN[PIN_nRESET_PORT] >> PIN_nRESET_BIT) & 1U);
|
||||
}
|
||||
|
||||
/** nRESET I/O pin: Set Output.
|
||||
\param bit target device hardware reset pin status:
|
||||
- 0: issue a device hardware reset.
|
||||
- 1: release device hardware reset.
|
||||
*/
|
||||
static __forceinline void PIN_nRESET_OUT (uint32_t bit) {
|
||||
if (bit) {
|
||||
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
|
||||
LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
|
||||
} else {
|
||||
LPC_GPIO_PORT->SET[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] |= (1U << PIN_nRESET_BIT);
|
||||
}
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_LEDs_gr CMSIS-DAP Hardware Status LEDs
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
CMSIS-DAP Hardware may provide LEDs that indicate the status of the CMSIS-DAP Debug Unit.
|
||||
|
||||
It is recommended to provide the following LEDs for status indication:
|
||||
- Connect LED: is active when the DAP hardware is connected to a debugger.
|
||||
- Running LED: is active when the debugger has put the target device into running state.
|
||||
*/
|
||||
|
||||
/** Debug Unit: Set status of Connected LED.
|
||||
\param bit status of the Connect LED.
|
||||
- 1: Connect LED ON: debugger is connected to CMSIS-DAP Debug Unit.
|
||||
- 0: Connect LED OFF: debugger is not connected to CMSIS-DAP Debug Unit.
|
||||
*/
|
||||
static __inline void LED_CONNECTED_OUT (uint32_t bit) {
|
||||
LPC_GPIO_PORT->B[32*LED_CONNECTED_PORT + LED_CONNECTED_BIT] = bit;
|
||||
}
|
||||
|
||||
/** Debug Unit: Set status Target Running LED.
|
||||
\param bit status of the Target Running LED.
|
||||
- 1: Target Running LED ON: program execution in target started.
|
||||
- 0: Target Running LED OFF: program execution in target stopped.
|
||||
*/
|
||||
static __inline void LED_RUNNING_OUT (uint32_t bit) {
|
||||
; // Not available
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
//**************************************************************************************************
|
||||
/**
|
||||
\defgroup DAP_Config_Initialization_gr CMSIS-DAP Initialization
|
||||
\ingroup DAP_ConfigIO_gr
|
||||
@{
|
||||
|
||||
CMSIS-DAP Hardware I/O and LED Pins are initialized with the function \ref DAP_SETUP.
|
||||
*/
|
||||
|
||||
/** Setup of the Debug Unit I/O pins and LEDs (called when Debug Unit is initialized).
|
||||
This function performs the initialization of the CMSIS-DAP Hardware I/O Pins and the
|
||||
Status LEDs. In detail the operation of Hardware I/O and LED pins are enabled and set:
|
||||
- I/O clock system enabled.
|
||||
- all I/O pins: input buffer enabled, output pins are set to HighZ mode.
|
||||
- for nTRST, nRESET a weak pull-up (if available) is enabled.
|
||||
- LED output pins are enabled and LEDs are turned off.
|
||||
*/
|
||||
static __inline void DAP_SETUP (void) {
|
||||
|
||||
/* Enable clock and init GPIO outputs */
|
||||
LPC_CCU1->CLK_M4_GPIO_CFG = CCU_CLK_CFG_AUTO | CCU_CLK_CFG_RUN;
|
||||
while (!(LPC_CCU1->CLK_M4_GPIO_STAT & CCU_CLK_STAT_RUN));
|
||||
|
||||
/* Configure I/O pins: function number, input buffer enabled, */
|
||||
/* no pull-up/down except nRESET (pull-up) */
|
||||
LPC_SCU->SFSP1_17 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWCLK/TCK: GPIO0[12] */
|
||||
LPC_SCU->SFSP1_6 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWDIO/TMS: GPIO1[9] */
|
||||
LPC_SCU->SFSP1_5 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* SWDIO_OE: GPIO1[8] */
|
||||
LPC_SCU->SFSP1_18 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* TDI: GPIO0[13] */
|
||||
LPC_SCU->SFSP1_14 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* TDO: GPIO1[7] */
|
||||
LPC_SCU->SFSP2_5 = 4U | SCU_SFS_EZI; /* nRESET: GPIO5[5] */
|
||||
LPC_SCU->SFSP2_6 = 4U | SCU_SFS_EPUN|SCU_SFS_EZI; /* nRESET_OE: GPIO5[6] */
|
||||
LPC_SCU->SFSP1_1 = 0U | SCU_SFS_EPUN|SCU_SFS_EZI; /* LED: GPIO0[8] */
|
||||
|
||||
/* Configure: SWCLK/TCK, SWDIO/TMS, SWDIO_OE, TDI as outputs (high level) */
|
||||
/* TDO as input */
|
||||
/* nRESET as input with output latch set to low level */
|
||||
/* nRESET_OE as output (low level) */
|
||||
LPC_GPIO_PORT->SET[PIN_SWCLK_TCK_PORT] = (1U << PIN_SWCLK_TCK_BIT);
|
||||
LPC_GPIO_PORT->SET[PIN_SWDIO_TMS_PORT] = (1U << PIN_SWDIO_TMS_BIT);
|
||||
LPC_GPIO_PORT->SET[PIN_SWDIO_OE_PORT] = (1U << PIN_SWDIO_OE_BIT);
|
||||
LPC_GPIO_PORT->SET[PIN_TDI_PORT] = (1U << PIN_TDI_BIT);
|
||||
LPC_GPIO_PORT->CLR[PIN_nRESET_PORT] = (1U << PIN_nRESET_BIT);
|
||||
LPC_GPIO_PORT->CLR[PIN_nRESET_OE_PORT] = (1U << PIN_nRESET_OE_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_SWCLK_TCK_PORT] |= (1U << PIN_SWCLK_TCK_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_SWDIO_TMS_PORT] |= (1U << PIN_SWDIO_TMS_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_SWDIO_OE_PORT] |= (1U << PIN_SWDIO_OE_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_TDI_PORT] |= (1U << PIN_TDI_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_TDO_PORT] &= ~(1U << PIN_TDO_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_nRESET_PORT] &= ~(1U << PIN_nRESET_BIT);
|
||||
LPC_GPIO_PORT->DIR[PIN_nRESET_OE_PORT] |= (1U << PIN_nRESET_OE_BIT);
|
||||
|
||||
/* Configure: LED as output (turned off) */
|
||||
LPC_GPIO_PORT->CLR[LED_CONNECTED_PORT] = (1U << LED_CONNECTED_BIT);
|
||||
LPC_GPIO_PORT->DIR[LED_CONNECTED_PORT] |= (1U << LED_CONNECTED_BIT);
|
||||
|
||||
/* Configure Peripheral Interrupt Priorities */
|
||||
NVIC_SetPriority(USB0_IRQn, 1U);
|
||||
}
|
||||
|
||||
/** Reset Target Device with custom specific I/O pin or command sequence.
|
||||
This function allows the optional implementation of a device specific reset sequence.
|
||||
It is called when the command \ref DAP_ResetTarget and is for example required
|
||||
when a device needs a time-critical unlock sequence that enables the debug port.
|
||||
\return 0 = no device specific reset sequence is implemented.\n
|
||||
1 = a device specific reset sequence is implemented.
|
||||
*/
|
||||
static __inline uint32_t RESET_TARGET (void) {
|
||||
return (0); // change to '1' when a device reset sequence is implemented
|
||||
}
|
||||
|
||||
///@}
|
||||
|
||||
|
||||
#endif /* __DAP_CONFIG_H__ */
|
||||
+311
@@ -0,0 +1,311 @@
|
||||
/*----------------------------------------------------------------------------
|
||||
* CMSIS-RTOS - RTX
|
||||
*----------------------------------------------------------------------------
|
||||
* Name: RTX_Conf_CM.C
|
||||
* Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
|
||||
* Rev.: V4.70.1
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
|
||||
* All rights reserved.
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* - Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* - Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* - Neither the name of ARM nor the names of its contributors may be used
|
||||
* to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include "cmsis_os.h"
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* RTX User configuration part BEGIN
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||
//
|
||||
// <h>Thread Configuration
|
||||
// =======================
|
||||
//
|
||||
// <o>Number of concurrent running user threads <1-250>
|
||||
// <i> Defines max. number of user threads that will run at the same time.
|
||||
// <i> Default: 6
|
||||
#ifndef OS_TASKCNT
|
||||
#define OS_TASKCNT 4
|
||||
#endif
|
||||
|
||||
// <o>Default Thread stack size [bytes] <64-4096:8><#/4>
|
||||
// <i> Defines default stack size for threads with osThreadDef stacksz = 0
|
||||
// <i> Default: 200
|
||||
#ifndef OS_STKSIZE
|
||||
#define OS_STKSIZE 64 // this stack size value is in words
|
||||
#endif
|
||||
|
||||
// <o>Main Thread stack size [bytes] <64-32768:8><#/4>
|
||||
// <i> Defines stack size for main thread.
|
||||
// <i> Default: 200
|
||||
#ifndef OS_MAINSTKSIZE
|
||||
#define OS_MAINSTKSIZE 128 // this stack size value is in words
|
||||
#endif
|
||||
|
||||
// <o>Number of threads with user-provided stack size <0-250>
|
||||
// <i> Defines the number of threads with user-provided stack size.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_PRIVCNT
|
||||
#define OS_PRIVCNT 3
|
||||
#endif
|
||||
|
||||
// <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
|
||||
// <i> Defines the combined stack size for threads with user-provided stack size.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_PRIVSTKSIZE
|
||||
#define OS_PRIVSTKSIZE 384 // this stack size value is in words
|
||||
#endif
|
||||
|
||||
// <q>Stack overflow checking
|
||||
// <i> Enable stack overflow checks at thread switch.
|
||||
// <i> Enabling this option increases slightly the execution time of a thread switch.
|
||||
#ifndef OS_STKCHECK
|
||||
#define OS_STKCHECK 1
|
||||
#endif
|
||||
|
||||
// <q>Stack usage watermark
|
||||
// <i> Initialize thread stack with watermark pattern for analyzing stack usage (current/maximum) in System and Thread Viewer.
|
||||
// <i> Enabling this option increases significantly the execution time of osThreadCreate.
|
||||
#ifndef OS_STKINIT
|
||||
#define OS_STKINIT 0
|
||||
#endif
|
||||
|
||||
// <o>Processor mode for thread execution
|
||||
// <0=> Unprivileged mode
|
||||
// <1=> Privileged mode
|
||||
// <i> Default: Privileged mode
|
||||
#ifndef OS_RUNPRIV
|
||||
#define OS_RUNPRIV 1
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>RTX Kernel Timer Tick Configuration
|
||||
// ======================================
|
||||
// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
|
||||
// <i> Cortex-M processors provide in most cases a SysTick timer that can be used as
|
||||
// <i> as time-base for RTX.
|
||||
#ifndef OS_SYSTICK
|
||||
#define OS_SYSTICK 1
|
||||
#endif
|
||||
//
|
||||
// <o>RTOS Kernel Timer input clock frequency [Hz] <1-1000000000>
|
||||
// <i> Defines the input frequency of the RTOS Kernel Timer.
|
||||
// <i> When the Cortex-M SysTick timer is used, the input clock
|
||||
// <i> is on most systems identical with the core clock.
|
||||
#ifndef OS_CLOCK
|
||||
#define OS_CLOCK 180000000
|
||||
#endif
|
||||
|
||||
// <o>RTX Timer tick interval value [us] <1-1000000>
|
||||
// <i> The RTX Timer tick interval value is used to calculate timeout values.
|
||||
// <i> When the Cortex-M SysTick timer is enabled, the value also configures the SysTick timer.
|
||||
// <i> Default: 1000 (1ms)
|
||||
#ifndef OS_TICK
|
||||
#define OS_TICK 1000
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>System Configuration
|
||||
// =======================
|
||||
//
|
||||
// <e>Round-Robin Thread switching
|
||||
// ===============================
|
||||
//
|
||||
// <i> Enables Round-Robin Thread switching.
|
||||
#ifndef OS_ROBIN
|
||||
#define OS_ROBIN 1
|
||||
#endif
|
||||
|
||||
// <o>Round-Robin Timeout [ticks] <1-1000>
|
||||
// <i> Defines how long a thread will execute before a thread switch.
|
||||
// <i> Default: 5
|
||||
#ifndef OS_ROBINTOUT
|
||||
#define OS_ROBINTOUT 5
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <e>User Timers
|
||||
// ==============
|
||||
// <i> Enables user Timers
|
||||
#ifndef OS_TIMERS
|
||||
#define OS_TIMERS 1
|
||||
#endif
|
||||
|
||||
// <o>Timer Thread Priority
|
||||
// <1=> Low
|
||||
// <2=> Below Normal <3=> Normal <4=> Above Normal
|
||||
// <5=> High
|
||||
// <6=> Realtime (highest)
|
||||
// <i> Defines priority for Timer Thread
|
||||
// <i> Default: High
|
||||
#ifndef OS_TIMERPRIO
|
||||
#define OS_TIMERPRIO 5
|
||||
#endif
|
||||
|
||||
// <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
|
||||
// <i> Defines stack size for Timer thread.
|
||||
// <i> Default: 200
|
||||
#ifndef OS_TIMERSTKSZ
|
||||
#define OS_TIMERSTKSZ 128 // this stack size value is in words
|
||||
#endif
|
||||
|
||||
// <o>Timer Callback Queue size <1-32>
|
||||
// <i> Number of concurrent active timer callback functions.
|
||||
// <i> Default: 4
|
||||
#ifndef OS_TIMERCBQS
|
||||
#define OS_TIMERCBQS 4
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// <o>ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
|
||||
// <12=> 12 entries <16=> 16 entries
|
||||
// <24=> 24 entries <32=> 32 entries
|
||||
// <48=> 48 entries <64=> 64 entries
|
||||
// <96=> 96 entries
|
||||
// <i> ISR functions store requests to this buffer,
|
||||
// <i> when they are called from the interrupt handler.
|
||||
// <i> Default: 16 entries
|
||||
#ifndef OS_FIFOSZ
|
||||
#define OS_FIFOSZ 16
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
//------------- <<< end of configuration section >>> -----------------------
|
||||
|
||||
// Standard library system mutexes
|
||||
// ===============================
|
||||
// Define max. number system mutexes that are used to protect
|
||||
// the arm standard runtime library. For microlib they are not used.
|
||||
#ifndef OS_MUTEXCNT
|
||||
#define OS_MUTEXCNT 8
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* RTX User configuration part END
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Global Functions
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
/*--------------------------- os_idle_demon ---------------------------------*/
|
||||
|
||||
/// \brief The idle demon is running when no other thread is ready to run
|
||||
void os_idle_demon (void) {
|
||||
|
||||
for (;;) {
|
||||
/* HERE: include optional user code to be executed when no thread runs.*/
|
||||
}
|
||||
}
|
||||
|
||||
#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer
|
||||
|
||||
/*--------------------------- os_tick_init ----------------------------------*/
|
||||
|
||||
/// \brief Initializes an alternative hardware timer as RTX kernel timer
|
||||
/// \return IRQ number of the alternative hardware timer
|
||||
int os_tick_init (void) {
|
||||
return (-1); /* Return IRQ number of timer (0..239) */
|
||||
}
|
||||
|
||||
/*--------------------------- os_tick_val -----------------------------------*/
|
||||
|
||||
/// \brief Get alternative hardware timer's current value (0 .. OS_TRV)
|
||||
/// \return Current value of the alternative hardware timer
|
||||
uint32_t os_tick_val (void) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*--------------------------- os_tick_ovf -----------------------------------*/
|
||||
|
||||
/// \brief Get alternative hardware timer's overflow flag
|
||||
/// \return Overflow flag\n
|
||||
/// - 1 : overflow
|
||||
/// - 0 : no overflow
|
||||
uint32_t os_tick_ovf (void) {
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*--------------------------- os_tick_irqack --------------------------------*/
|
||||
|
||||
/// \brief Acknowledge alternative hardware timer interrupt
|
||||
void os_tick_irqack (void) {
|
||||
/* ... */
|
||||
}
|
||||
|
||||
#endif // (OS_SYSTICK == 0)
|
||||
|
||||
/*--------------------------- os_error --------------------------------------*/
|
||||
|
||||
/* OS Error Codes */
|
||||
#define OS_ERROR_STACK_OVF 1
|
||||
#define OS_ERROR_FIFO_OVF 2
|
||||
#define OS_ERROR_MBX_OVF 3
|
||||
#define OS_ERROR_TIMER_OVF 4
|
||||
|
||||
extern osThreadId svcThreadGetId (void);
|
||||
|
||||
/// \brief Called when a runtime error is detected
|
||||
/// \param[in] error_code actual error code that has been detected
|
||||
void os_error (uint32_t error_code) {
|
||||
|
||||
/* HERE: include optional code to be executed on runtime error. */
|
||||
switch (error_code) {
|
||||
case OS_ERROR_STACK_OVF:
|
||||
/* Stack overflow detected for the currently running task. */
|
||||
/* Thread can be identified by calling svcThreadGetId(). */
|
||||
break;
|
||||
case OS_ERROR_FIFO_OVF:
|
||||
/* ISR FIFO Queue buffer overflow detected. */
|
||||
break;
|
||||
case OS_ERROR_MBX_OVF:
|
||||
/* Mailbox overflow detected. */
|
||||
break;
|
||||
case OS_ERROR_TIMER_OVF:
|
||||
/* User Timer Callback Queue overflow detected. */
|
||||
break;
|
||||
}
|
||||
for (;;);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* RTX Configuration Functions
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include "RTX_CM_lib.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* end of file
|
||||
*---------------------------------------------------------------------------*/
|
||||
+2313
File diff suppressed because it is too large
Load Diff
+333
@@ -0,0 +1,333 @@
|
||||
;/**************************************************************************//**
|
||||
; * @file LPC43xx.s
|
||||
; * @brief CMSIS Cortex-M4 Core Device Startup File for
|
||||
; * NXP LPC43xxDevice Series
|
||||
; * @version V1.00
|
||||
; * @date 03. September 2013
|
||||
; *
|
||||
; * @note
|
||||
; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
|
||||
; *
|
||||
; * @par
|
||||
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
; * processor based microcontrollers. This file can be freely distributed
|
||||
; * within development tools that are supporting such ARM based processors.
|
||||
; *
|
||||
; * @par
|
||||
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
; *
|
||||
; ******************************************************************************/
|
||||
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000200
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000000
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
|
||||
Sign_Value EQU 0x5A5A5A5A
|
||||
|
||||
__Vectors DCD __initial_sp ; 0 Top of Stack
|
||||
DCD Reset_Handler ; 1 Reset Handler
|
||||
DCD NMI_Handler ; 2 NMI Handler
|
||||
DCD HardFault_Handler ; 3 Hard Fault Handler
|
||||
DCD MemManage_Handler ; 4 MPU Fault Handler
|
||||
DCD BusFault_Handler ; 5 Bus Fault Handler
|
||||
DCD UsageFault_Handler ; 6 Usage Fault Handler
|
||||
DCD Sign_Value ; 7 Reserved
|
||||
DCD 0 ; 8 Reserved
|
||||
DCD 0 ; 9 Reserved
|
||||
DCD 0 ; 10 Reserved
|
||||
DCD SVC_Handler ; 11 SVCall Handler
|
||||
DCD DebugMon_Handler ; 12 Debug Monitor Handler
|
||||
DCD 0 ; 13 Reserved
|
||||
DCD PendSV_Handler ; 14 PendSV Handler
|
||||
DCD SysTick_Handler ; 15 SysTick Handler
|
||||
|
||||
; External LPC43xx/M4 Interrupts
|
||||
DCD DAC_IRQHandler ; 0 DAC interrupt
|
||||
DCD M0APP_IRQHandler ; 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication
|
||||
DCD DMA_IRQHandler ; 2 DMA interrupt
|
||||
DCD 0 ; 3 Reserved
|
||||
DCD FLASHEEPROM_IRQHandler ; 4 flash bank A, flash bank B, EEPROM ORed interrupt
|
||||
DCD ETHERNET_IRQHandler ; 5 Ethernet interrupt
|
||||
DCD SDIO_IRQHandler ; 6 SD/MMC interrupt
|
||||
DCD LCD_IRQHandler ; 7 LCD interrupt
|
||||
DCD USB0_IRQHandler ; 8 OTG interrupt
|
||||
DCD USB1_IRQHandler ; 9 USB1 interrupt
|
||||
DCD SCT_IRQHandler ; 10 SCT combined interrupt
|
||||
DCD RITIMER_IRQHandler ; 11 RI Timer interrupt
|
||||
DCD TIMER0_IRQHandler ; 12 Timer 0 interrupt
|
||||
DCD TIMER1_IRQHandler ; 13 Timer 1 interrupt
|
||||
DCD TIMER2_IRQHandler ; 14 Timer 2 interrupt
|
||||
DCD TIMER3_IRQHandler ; 15 Timer 3 interrupt
|
||||
DCD MCPWM_IRQHandler ; 16 Motor control PWM interrupt
|
||||
DCD ADC0_IRQHandler ; 17 ADC0 interrupt
|
||||
DCD I2C0_IRQHandler ; 18 I2C0 interrupt
|
||||
DCD I2C1_IRQHandler ; 19 I2C1 interrupt
|
||||
DCD SPI_IRQHandler ; 20 SPI interrupt
|
||||
DCD ADC1_IRQHandler ; 21 ADC1 interrupt
|
||||
DCD SSP0_IRQHandler ; 22 SSP0 interrupt
|
||||
DCD SSP1_IRQHandler ; 23 SSP1 interrupt
|
||||
DCD USART0_IRQHandler ; 24 USART0 interrupt
|
||||
DCD UART1_IRQHandler ; 25 Combined UART1, Modem interrupt
|
||||
DCD USART2_IRQHandler ; 26 USART2 interrupt
|
||||
DCD USART3_IRQHandler ; 27 Combined USART3, IrDA interrupt
|
||||
DCD I2S0_IRQHandler ; 28 I2S0 interrupt
|
||||
DCD I2S1_IRQHandler ; 29 I2S1 interrupt
|
||||
DCD SPIFI_IRQHandler ; 30 SPISI interrupt
|
||||
DCD SGPIO_IRQHandler ; 31 SGPIO interrupt
|
||||
DCD PIN_INT0_IRQHandler ; 32 GPIO pin interrupt 0
|
||||
DCD PIN_INT1_IRQHandler ; 33 GPIO pin interrupt 1
|
||||
DCD PIN_INT2_IRQHandler ; 34 GPIO pin interrupt 2
|
||||
DCD PIN_INT3_IRQHandler ; 35 GPIO pin interrupt 3
|
||||
DCD PIN_INT4_IRQHandler ; 36 GPIO pin interrupt 4
|
||||
DCD PIN_INT5_IRQHandler ; 37 GPIO pin interrupt 5
|
||||
DCD PIN_INT6_IRQHandler ; 38 GPIO pin interrupt 6
|
||||
DCD PIN_INT7_IRQHandler ; 39 GPIO pin interrupt 7
|
||||
DCD GINT0_IRQHandler ; 40 GPIO global interrupt 0
|
||||
DCD GINT1_IRQHandler ; 41 GPIO global interrupt 1
|
||||
DCD EVENTROUTER_IRQHandler ; 42 Event router interrupt
|
||||
DCD C_CAN1_IRQHandler ; 43 C_CAN1 interrupt
|
||||
DCD 0 ; 44 Reserved
|
||||
DCD ADCHS_IRQHandler ; 45 ADCHS combined interrupt
|
||||
DCD ATIMER_IRQHandler ; 46 Alarm timer interrupt
|
||||
DCD RTC_IRQHandler ; 47 RTC interrupt
|
||||
DCD 0 ; 48 Reserved
|
||||
DCD WWDT_IRQHandler ; 49 WWDT interrupt
|
||||
DCD M0SUB_IRQHandler ; 50 TXEV instruction from the M0 subsystem core interrupt
|
||||
DCD C_CAN0_IRQHandler ; 51 C_CAN0 interrupt
|
||||
DCD QEI_IRQHandler ; 52 QEI interrupt
|
||||
|
||||
|
||||
;CRP address at offset 0x2FC relative to the BOOT Bank address
|
||||
IF :LNOT::DEF:NO_CRP
|
||||
SPACE (0x2FC - (. - __Vectors))
|
||||
; EXPORT CRP_Key
|
||||
CRP_Key DCD 0xFFFFFFFF
|
||||
; 0xFFFFFFFF => CRP Disabled
|
||||
; 0x12345678 => CRP Level 1
|
||||
; 0x87654321 => CRP Level 2
|
||||
; 0x43218765 => CRP Level 3 (ARE YOU SURE?)
|
||||
; 0x4E697370 => NO ISP (ARE YOU SURE?)
|
||||
ENDIF
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset Handler
|
||||
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT SystemInit
|
||||
IMPORT __main
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
EXPORT DAC_IRQHandler [WEAK]
|
||||
EXPORT M0APP_IRQHandler [WEAK]
|
||||
EXPORT DMA_IRQHandler [WEAK]
|
||||
EXPORT FLASHEEPROM_IRQHandler [WEAK]
|
||||
EXPORT ETHERNET_IRQHandler [WEAK]
|
||||
EXPORT SDIO_IRQHandler [WEAK]
|
||||
EXPORT LCD_IRQHandler [WEAK]
|
||||
EXPORT USB0_IRQHandler [WEAK]
|
||||
EXPORT USB1_IRQHandler [WEAK]
|
||||
EXPORT SCT_IRQHandler [WEAK]
|
||||
EXPORT RITIMER_IRQHandler [WEAK]
|
||||
EXPORT TIMER0_IRQHandler [WEAK]
|
||||
EXPORT TIMER1_IRQHandler [WEAK]
|
||||
EXPORT TIMER2_IRQHandler [WEAK]
|
||||
EXPORT TIMER3_IRQHandler [WEAK]
|
||||
EXPORT MCPWM_IRQHandler [WEAK]
|
||||
EXPORT ADC0_IRQHandler [WEAK]
|
||||
EXPORT I2C0_IRQHandler [WEAK]
|
||||
EXPORT I2C1_IRQHandler [WEAK]
|
||||
EXPORT SPI_IRQHandler [WEAK]
|
||||
EXPORT ADC1_IRQHandler [WEAK]
|
||||
EXPORT SSP0_IRQHandler [WEAK]
|
||||
EXPORT SSP1_IRQHandler [WEAK]
|
||||
EXPORT USART0_IRQHandler [WEAK]
|
||||
EXPORT UART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT I2S0_IRQHandler [WEAK]
|
||||
EXPORT I2S1_IRQHandler [WEAK]
|
||||
EXPORT SPIFI_IRQHandler [WEAK]
|
||||
EXPORT SGPIO_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT0_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT1_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT2_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT3_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT4_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT5_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT6_IRQHandler [WEAK]
|
||||
EXPORT PIN_INT7_IRQHandler [WEAK]
|
||||
EXPORT GINT0_IRQHandler [WEAK]
|
||||
EXPORT GINT1_IRQHandler [WEAK]
|
||||
EXPORT EVENTROUTER_IRQHandler [WEAK]
|
||||
EXPORT C_CAN1_IRQHandler [WEAK]
|
||||
EXPORT ADCHS_IRQHandler [WEAK]
|
||||
EXPORT ATIMER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT WWDT_IRQHandler [WEAK]
|
||||
EXPORT M0SUB_IRQHandler [WEAK]
|
||||
EXPORT C_CAN0_IRQHandler [WEAK]
|
||||
EXPORT QEI_IRQHandler [WEAK]
|
||||
|
||||
DAC_IRQHandler
|
||||
M0APP_IRQHandler
|
||||
DMA_IRQHandler
|
||||
FLASHEEPROM_IRQHandler
|
||||
ETHERNET_IRQHandler
|
||||
SDIO_IRQHandler
|
||||
LCD_IRQHandler
|
||||
USB0_IRQHandler
|
||||
USB1_IRQHandler
|
||||
SCT_IRQHandler
|
||||
RITIMER_IRQHandler
|
||||
TIMER0_IRQHandler
|
||||
TIMER1_IRQHandler
|
||||
TIMER2_IRQHandler
|
||||
TIMER3_IRQHandler
|
||||
MCPWM_IRQHandler
|
||||
ADC0_IRQHandler
|
||||
I2C0_IRQHandler
|
||||
I2C1_IRQHandler
|
||||
SPI_IRQHandler
|
||||
ADC1_IRQHandler
|
||||
SSP0_IRQHandler
|
||||
SSP1_IRQHandler
|
||||
USART0_IRQHandler
|
||||
UART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
I2S0_IRQHandler
|
||||
I2S1_IRQHandler
|
||||
SPIFI_IRQHandler
|
||||
SGPIO_IRQHandler
|
||||
PIN_INT0_IRQHandler
|
||||
PIN_INT1_IRQHandler
|
||||
PIN_INT2_IRQHandler
|
||||
PIN_INT3_IRQHandler
|
||||
PIN_INT4_IRQHandler
|
||||
PIN_INT5_IRQHandler
|
||||
PIN_INT6_IRQHandler
|
||||
PIN_INT7_IRQHandler
|
||||
GINT0_IRQHandler
|
||||
GINT1_IRQHandler
|
||||
EVENTROUTER_IRQHandler
|
||||
C_CAN1_IRQHandler
|
||||
ADCHS_IRQHandler
|
||||
ATIMER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
WWDT_IRQHandler
|
||||
M0SUB_IRQHandler
|
||||
C_CAN0_IRQHandler
|
||||
QEI_IRQHandler
|
||||
|
||||
B .
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
; User Initial Stack & Heap
|
||||
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, =(Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
|
||||
END
|
||||
+910
@@ -0,0 +1,910 @@
|
||||
/* -----------------------------------------------------------------------------
|
||||
* Copyright (c) 2013 - 2014 ARM Ltd.
|
||||
*
|
||||
* This software is provided 'as-is', without any express or implied warranty.
|
||||
* In no event will the authors be held liable for any damages arising from
|
||||
* the use of this software. Permission is granted to anyone to use this
|
||||
* software for any purpose, including commercial applications, and to alter
|
||||
* it and redistribute it freely, subject to the following restrictions:
|
||||
*
|
||||
* 1. The origin of this software must not be misrepresented; you must not
|
||||
* claim that you wrote the original software. If you use this software in
|
||||
* a product, an acknowledgment in the product documentation would be
|
||||
* appreciated but is not required.
|
||||
*
|
||||
* 2. Altered source versions must be plainly marked as such, and must not be
|
||||
* misrepresented as being the original software.
|
||||
*
|
||||
* 3. This notice may not be removed or altered from any source distribution.
|
||||
*
|
||||
* $Date: 16/06/16 3:27p $Revision: V5.00
|
||||
*
|
||||
* Project: NXP LPC43xx System initialization
|
||||
* -------------------------------------------------------------------------- */
|
||||
|
||||
#include "LPC43xx.h"
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
This file configures the clocks as follows:
|
||||
-----------------------------------------------------------------------------
|
||||
Clock Unit | Output clock | Source clock | Note
|
||||
-----------------------------------------------------------------------------
|
||||
PLL0USB | 480 MHz | XTAL | External crystal @ 12 MHz
|
||||
-----------------------------------------------------------------------------
|
||||
PLL1 | 180 MHz | XTAL | External crystal @ 12 MHz
|
||||
-----------------------------------------------------------------------------
|
||||
CPU | 180 MHz | PLL1 | CPU Clock == BASE_M4_CLK
|
||||
-----------------------------------------------------------------------------
|
||||
IDIV A | 60 MHz | PLL1 | To the USB1 peripheral
|
||||
-----------------------------------------------------------------------------
|
||||
IDIV B | 25 MHz | ENET_TX_CLK | ENET_TX_CLK @ 50MHz
|
||||
-----------------------------------------------------------------------------
|
||||
IDIV C | 12 MHz | IRC | Internal oscillator @ 12 MHz
|
||||
-----------------------------------------------------------------------------
|
||||
IDIV D | 12 MHz | IRC | Internal oscillator @ 12 MHz
|
||||
-----------------------------------------------------------------------------
|
||||
IDIV E | 5.3 MHz | PLL1 | To the LCD controller
|
||||
-----------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Clock source selection definitions (do not change)
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CLK_SRC_32KHZ 0x00
|
||||
#define CLK_SRC_IRC 0x01
|
||||
#define CLK_SRC_ENET_RX 0x02
|
||||
#define CLK_SRC_ENET_TX 0x03
|
||||
#define CLK_SRC_GP_CLKIN 0x04
|
||||
#define CLK_SRC_XTAL 0x06
|
||||
#define CLK_SRC_PLL0U 0x07
|
||||
#define CLK_SRC_PLL0A 0x08
|
||||
#define CLK_SRC_PLL1 0x09
|
||||
#define CLK_SRC_IDIVA 0x0C
|
||||
#define CLK_SRC_IDIVB 0x0D
|
||||
#define CLK_SRC_IDIVC 0x0E
|
||||
#define CLK_SRC_IDIVD 0x0F
|
||||
#define CLK_SRC_IDIVE 0x10
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define external input frequency values
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CLK_32KHZ 32768UL /* 32 kHz oscillator frequency */
|
||||
#define CLK_IRC 12000000UL /* Internal oscillator frequency */
|
||||
#define CLK_ENET_RX 50000000UL /* Ethernet Rx frequency */
|
||||
#define CLK_ENET_TX 50000000UL /* Ethernet Tx frequency */
|
||||
#define CLK_GP_CLKIN 12000000UL /* General purpose clock input freq. */
|
||||
#define CLK_XTAL 12000000UL /* Crystal oscilator frequency */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define clock sources
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define PLL1_CLK_SEL CLK_SRC_XTAL /* PLL1 input clock: XTAL */
|
||||
#define PLL0USB_CLK_SEL CLK_SRC_XTAL /* PLL0USB input clock: XTAL */
|
||||
#define IDIVA_CLK_SEL CLK_SRC_PLL1 /* IDIVA input clock: PLL1 */
|
||||
#define IDIVB_CLK_SEL CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX */
|
||||
#define IDIVC_CLK_SEL CLK_SRC_IRC /* IDIVC input clock: IRC */
|
||||
#define IDIVD_CLK_SEL CLK_SRC_IRC /* IDIVD input clock: IRC */
|
||||
#define IDIVE_CLK_SEL CLK_SRC_PLL1 /* IDIVD input clock: PLL1 */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Configure integer divider values
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define IDIVA_IDIV 2 /* Divide input clock by 3 */
|
||||
#define IDIVB_IDIV 1 /* Divide input clock by 2 */
|
||||
#define IDIVC_IDIV 0 /* Divide input clock by 1 */
|
||||
#define IDIVD_IDIV 0 /* Divide input clock by 1 */
|
||||
#define IDIVE_IDIV 33 /* Divide input clock by 34 */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Define CPU clock input
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CPU_CLK_SEL CLK_SRC_PLL1 /* Default CPU clock source is PLL1 */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Configure external memory controller options
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define USE_EXT_STAT_MEM_CS0 1 /* Use ext. static memory with CS0 */
|
||||
#define USE_EXT_DYN_MEM_CS0 1 /* Use ext. dynamic memory with CS0 */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Configure PLL1
|
||||
*----------------------------------------------------------------------------
|
||||
* Integer mode:
|
||||
* - PLL1_DIRECT = 0 (Post divider enabled)
|
||||
* - PLL1_FBSEL = 1 (Feedback divider runs from PLL output)
|
||||
* - Output frequency:
|
||||
* FCLKOUT = (FCLKIN / N) * M
|
||||
* FCCO = FCLKOUT * 2 * P
|
||||
*
|
||||
* Non-integer:
|
||||
* - PLL1_DIRECT = 0 (Post divider enabled)
|
||||
* - PLL1_FBSEL = 0 (Feedback divider runs from CCO clock)
|
||||
* - Output frequency:
|
||||
* FCLKOUT = (FCLKIN / N) * M / (2 * P)
|
||||
* FCCO = FCLKOUT * 2 * P
|
||||
*
|
||||
* Direct mode:
|
||||
* - PLL1_DIRECT = 1 (Post divider disabled)
|
||||
* - PLL1_FBSEL = dont care (Feedback divider runs from CCO clock)
|
||||
* - Output frequency:
|
||||
* FCLKOUT = (FCLKIN / N) * M
|
||||
* FCCO = FCLKOUT
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
* PLL1 requirements:
|
||||
* | Frequency | Minimum | Maximum | Note |
|
||||
* | FCLKIN | 1MHz | 25MHz | Clock source is external crystal |
|
||||
* | FCLKIN | 1MHz | 50MHz | |
|
||||
* | FCCO | 156MHz | 320MHz | |
|
||||
* | FCLKOUT | 9.75MHz | 320MHz | |
|
||||
*----------------------------------------------------------------------------
|
||||
* Configuration examples:
|
||||
* | Fclkout | Fcco | N | M | P | DIRECT | FBSEL | BYPASS |
|
||||
* | 36MHz | 288MHz | 1 | 24 | 4 | 0 | 0 | 0 |
|
||||
* | 72MHz | 288MHz | 1 | 24 | 2 | 0 | 0 | 0 |
|
||||
* | 100MHz | 200MHz | 3 | 50 | 1 | 0 | 0 | 0 |
|
||||
* | 120MHz | 240MHz | 1 | 20 | 1 | 0 | 0 | 0 |
|
||||
* | 160MHz | 160MHz | 3 | 40 | x | 1 | 0 | 0 |
|
||||
* | 180MHz | 180MHz | 1 | 15 | x | 1 | 0 | 0 |
|
||||
* | 204MHz | 204MHz | 1 | 17 | x | 1 | 0 | 0 |
|
||||
*----------------------------------------------------------------------------
|
||||
* Relations beetwen PLL dividers and definitions:
|
||||
* N = PLL1_NSEL + 1, M = PLL1_MSEL + 1, P = 2 ^ PLL1_PSEL
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x */
|
||||
#define PLL1_NSEL 0 /* Range [0 - 3]: Pre-divider ratio N */
|
||||
#define PLL1_MSEL 14 /* Range [0 - 255]: Feedback-divider ratio M */
|
||||
#define PLL1_PSEL 0 /* Range [0 - 3]: Post-divider ratio P */
|
||||
|
||||
#define PLL1_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
|
||||
#define PLL1_DIRECT 1 /* 0: Use PSEL, 1: Don't use PSEL */
|
||||
#define PLL1_FBSEL 0 /* 0: FCCO is used as PLL feedback */
|
||||
/* 1: FCLKOUT is used as PLL feedback */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* Configure PLL0USB
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Normal operating mode without post-divider and without pre-divider
|
||||
* - PLL0USB_DIRECTI = 1
|
||||
* - PLL0USB_DIRECTO = 1
|
||||
* - PLL0USB_BYPASS = 0
|
||||
* - Output frequency:
|
||||
* FOUT = FIN * 2 * M
|
||||
* FCCO = FOUT
|
||||
*
|
||||
* Normal operating mode with post-divider and without pre-divider
|
||||
* - PLL0USB_DIRECTI = 1
|
||||
* - PLL0USB_DIRECTO = 0
|
||||
* - PLL0USB_BYPASS = 0
|
||||
* - Output frequency:
|
||||
* FOUT = FIN * (M / P)
|
||||
* FCCO = FOUT * 2 * P
|
||||
*
|
||||
* Normal operating mode without post-divider and with pre-divider
|
||||
* - PLL0USB_DIRECTI = 0
|
||||
* - PLL0USB_DIRECTO = 1
|
||||
* - PLL0USB_BYPASS = 0
|
||||
* - Output frequency:
|
||||
* FOUT = FIN * 2 * M / N
|
||||
* FCCO = FOUT
|
||||
*
|
||||
* Normal operating mode with post-divider and with pre-divider
|
||||
* - PLL0USB_DIRECTI = 0
|
||||
* - PLL0USB_DIRECTO = 0
|
||||
* - PLL0USB_BYPASS = 0
|
||||
* - Output frequency:
|
||||
* FOUT = FIN * M / (P * N)
|
||||
* FCCO = FOUT * 2 * P
|
||||
*----------------------------------------------------------------------------
|
||||
* PLL0 requirements:
|
||||
* | Frequency | Minimum | Maximum | Note |
|
||||
* | FCLKIN | 14kHz | 25MHz | Clock source is external crystal |
|
||||
* | FCLKIN | 14kHz | 150MHz | |
|
||||
* | FCCO | 275MHz | 550MHz | |
|
||||
* | FCLKOUT | 4.3MHz | 550MHz | |
|
||||
*----------------------------------------------------------------------------
|
||||
* Configuration examples:
|
||||
* | Fclkout | Fcco | N | M | P | DIRECTI | DIRECTO | BYPASS |
|
||||
* | 120MHz | 480MHz | x | 20 | 2 | 1 | 0 | 0 |
|
||||
* | 480MHz | 480MHz | 1 | 20 | 1 | 1 | 1 | 0 |
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1 */
|
||||
#define PLL0USB_N 1 /* Range [1 - 256]: Pre-divider */
|
||||
#define PLL0USB_M 20 /* Range [1 - 2^15]: Feedback-divider */
|
||||
#define PLL0USB_P 1 /* Range [1 - 32]: Post-divider */
|
||||
|
||||
#define PLL0USB_DIRECTI 1 /* 0: Use N_DIV, 1: Don't use N_DIV */
|
||||
#define PLL0USB_DIRECTO 1 /* 0: Use P_DIV, 1: Don't use P_DIV */
|
||||
#define PLL0USB_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
End of configuration
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/* PLL0 Setting Check */
|
||||
#if (PLL0USB_BYPASS == 0)
|
||||
#if (PLL0USB_CLK_SEL == CLK_SRC_XTAL)
|
||||
#define PLL0USB_CLKIN CLK_XTAL
|
||||
#else
|
||||
#define PLL0USB_CLKIN CLK_IRC
|
||||
#endif
|
||||
|
||||
#if ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a */
|
||||
#define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M)
|
||||
#define PLL0USB_FCCO (PLL0USB_FOUT)
|
||||
#elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b */
|
||||
#define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P)
|
||||
#define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
|
||||
#elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c */
|
||||
#define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N)
|
||||
#define PLL0USB_FCCO (PLL0USB_FOUT)
|
||||
#else /* Mode 1d */
|
||||
#define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N))
|
||||
#define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
|
||||
#endif
|
||||
|
||||
#if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL)
|
||||
#error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)"
|
||||
#endif
|
||||
#if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL)
|
||||
#error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* PLL1 Setting Check */
|
||||
#if (PLL1_BYPASS == 0)
|
||||
#if (PLL1_CLK_SEL == CLK_SRC_XTAL)
|
||||
#define PLL1_CLKIN CLK_XTAL
|
||||
#else
|
||||
#define PLL1_CLKIN CLK_IRC
|
||||
#endif
|
||||
|
||||
#if (PLL1_DIRECT == 1) /* Direct Mode */
|
||||
#define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
|
||||
#define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
|
||||
#elif (PLL1_FBSEL == 1) /* Integer Mode */
|
||||
#define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
|
||||
#define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
|
||||
#else /* Noninteger Mode */
|
||||
#define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
|
||||
#define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL)))
|
||||
#endif
|
||||
#if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL)
|
||||
#error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)"
|
||||
#endif
|
||||
#if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL)
|
||||
#error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock variable
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t SystemCoreClock = CLK_IRC; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* SetClock
|
||||
******************************************************************************/
|
||||
void SetClock (void) {
|
||||
uint32_t x, i;
|
||||
uint32_t selp, seli;
|
||||
|
||||
/* Set flash wait states to maximum */
|
||||
LPC_EMC->STATICWAITRD0 = 0x1F;
|
||||
|
||||
/* Switch BASE_M4_CLOCK to IRC */
|
||||
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
|
||||
(CLK_SRC_IRC << 24) ; /* Set clock source */
|
||||
|
||||
/* Configure input to crystal oscilator */
|
||||
LPC_CGU->XTAL_OSC_CTRL = (0 << 0) | /* Enable oscillator-pad */
|
||||
(0 << 1) | /* Operation with crystal connected */
|
||||
(0 << 2) ; /* Low-frequency mode */
|
||||
|
||||
/* Wait ~250us @ 12MHz */
|
||||
for (i = 1500; i; i--);
|
||||
|
||||
#if (USE_SPIFI)
|
||||
/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
|
||||
LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
|
||||
(0 << 2) | /* IDIV */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(CLK_SRC_IRC << 24) ; /* Clock source */
|
||||
|
||||
LPC_CGU->BASE_SPIFI_CLK = (0 << 0) | /* Disable Power-down */
|
||||
(0 << 2) | /* IDIV */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(CLK_SRC_IDIVA << 24) ; /* Clock source */
|
||||
#endif
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
PLL1 Setup
|
||||
*----------------------------------------------------------------------------*/
|
||||
/* Power down PLL */
|
||||
LPC_CGU->PLL1_CTRL |= 1;
|
||||
|
||||
#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1))
|
||||
/* To run at full speed, CPU must first run at an intermediate speed */
|
||||
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
|
||||
(PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
|
||||
(PLL1_FBSEL << 6) | /* PLL output used as feedback */
|
||||
(0 << 7) | /* Direct on/off */
|
||||
(PLL1_PSEL << 8) | /* PSEL */
|
||||
(0 << 11)| /* Autoblock Disabled */
|
||||
(PLL1_NSEL << 12)| /* NSEL */
|
||||
(PLL1_MSEL << 16)| /* MSEL */
|
||||
(PLL1_CLK_SEL << 24); /* Clock source */
|
||||
/* Wait for lock */
|
||||
while (!(LPC_CGU->PLL1_STAT & 1));
|
||||
|
||||
/* CPU base clock is in the mid frequency range before final clock set */
|
||||
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
|
||||
(0x09 << 24) ; /* Clock source: PLL1 */
|
||||
|
||||
/* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */
|
||||
for (i = 1050; i; i--); /* Wait minimum 2100 cycles */
|
||||
#endif
|
||||
/* Configure PLL1 */
|
||||
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
|
||||
(PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
|
||||
(PLL1_FBSEL << 6) | /* PLL output used as feedback */
|
||||
(PLL1_DIRECT << 7) | /* Direct on/off */
|
||||
(PLL1_PSEL << 8) | /* PSEL */
|
||||
(1 << 11)| /* Autoblock En */
|
||||
(PLL1_NSEL << 12)| /* NSEL */
|
||||
(PLL1_MSEL << 16)| /* MSEL */
|
||||
(PLL1_CLK_SEL << 24); /* Clock source */
|
||||
|
||||
/* Wait for lock */
|
||||
while (!(LPC_CGU->PLL1_STAT & 1));
|
||||
|
||||
/* Set CPU base clock source */
|
||||
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
|
||||
(CPU_CLK_SEL << 24) ; /* Set clock source */
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
PLL0USB Setup
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/* Power down PLL0USB */
|
||||
LPC_CGU->PLL0USB_CTRL |= 1;
|
||||
|
||||
/* M divider */
|
||||
x = 0x00004000;
|
||||
switch (PLL0USB_M) {
|
||||
case 0: x = 0xFFFFFFFF;
|
||||
break;
|
||||
case 1: x = 0x00018003;
|
||||
break;
|
||||
case 2: x = 0x00010003;
|
||||
break;
|
||||
default:
|
||||
for (i = PLL0USB_M; i <= 0x8000; i++) {
|
||||
x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
|
||||
}
|
||||
}
|
||||
|
||||
if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1;
|
||||
else selp = 31;
|
||||
|
||||
if (PLL0USB_M > 16384) seli = 1;
|
||||
else if (PLL0USB_M > 8192) seli = 2;
|
||||
else if (PLL0USB_M > 2048) seli = 4;
|
||||
else if (PLL0USB_M >= 501) seli = 8;
|
||||
else if (PLL0USB_M >= 60) seli = 4 * (1024 / (PLL0USB_M + 9));
|
||||
else seli = (PLL0USB_M & 0x3C) + 4;
|
||||
LPC_CGU->PLL0USB_MDIV = (selp << 17) |
|
||||
(seli << 22) |
|
||||
(x << 0);
|
||||
|
||||
/* N divider */
|
||||
x = 0x80;
|
||||
switch (PLL0USB_N) {
|
||||
case 0: x = 0xFFFFFFFF;
|
||||
break;
|
||||
case 1: x = 0x00000302;
|
||||
break;
|
||||
case 2: x = 0x00000202;
|
||||
break;
|
||||
default:
|
||||
for (i = PLL0USB_N; i <= 0x0100; i++) {
|
||||
x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
|
||||
}
|
||||
}
|
||||
LPC_CGU->PLL0USB_NP_DIV = (x << 12);
|
||||
|
||||
/* P divider */
|
||||
x = 0x10;
|
||||
switch (PLL0USB_P) {
|
||||
case 0: x = 0xFFFFFFFF;
|
||||
break;
|
||||
case 1: x = 0x00000062;
|
||||
break;
|
||||
case 2: x = 0x00000042;
|
||||
break;
|
||||
default:
|
||||
for (i = PLL0USB_P; i <= 0x200; i++) {
|
||||
x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F);
|
||||
}
|
||||
}
|
||||
LPC_CGU->PLL0USB_NP_DIV |= x;
|
||||
|
||||
LPC_CGU->PLL0USB_CTRL = (PLL0USB_CLK_SEL << 24) | /* Clock source sel */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(1 << 4 ) | /* PLL0USB clock en */
|
||||
(PLL0USB_DIRECTO << 3 ) | /* Direct output */
|
||||
(PLL0USB_DIRECTI << 2 ) | /* Direct input */
|
||||
(PLL0USB_BYPASS << 1 ) | /* PLL bypass */
|
||||
(0 << 0 ) ; /* PLL0USB Enabled */
|
||||
while (!(LPC_CGU->PLL0USB_STAT & 1));
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Integer divider Setup
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/* Configure integer dividers */
|
||||
LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
|
||||
(IDIVA_IDIV << 2) | /* IDIV */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(IDIVA_CLK_SEL << 24) ; /* Clock source */
|
||||
|
||||
LPC_CGU->IDIVB_CTRL = (0 << 0) | /* Disable Power-down */
|
||||
(IDIVB_IDIV << 2) | /* IDIV */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(IDIVB_CLK_SEL << 24) ; /* Clock source */
|
||||
|
||||
LPC_CGU->IDIVC_CTRL = (0 << 0) | /* Disable Power-down */
|
||||
(IDIVC_IDIV << 2) | /* IDIV */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(IDIVC_CLK_SEL << 24) ; /* Clock source */
|
||||
|
||||
LPC_CGU->IDIVD_CTRL = (0 << 0) | /* Disable Power-down */
|
||||
(IDIVD_IDIV << 2) | /* IDIV */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(IDIVD_CLK_SEL << 24) ; /* Clock source */
|
||||
|
||||
LPC_CGU->IDIVE_CTRL = (0 << 0) | /* Disable Power-down */
|
||||
(IDIVE_IDIV << 2) | /* IDIV */
|
||||
(1 << 11) | /* Autoblock En */
|
||||
(IDIVE_CLK_SEL << 24) ; /* Clock source */
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Approximate delay function (must be used after SystemCoreClockUpdate() call)
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)
|
||||
|
||||
static void WaitUs (uint32_t us) {
|
||||
uint32_t cyc = us * CPU_NANOSEC(1000)/4;
|
||||
while(cyc--);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
External Memory Controller Definitions
|
||||
*----------------------------------------------------------------------------*/
|
||||
#define SDRAM_ADDR_BASE 0x28000000 /* SDRAM base address */
|
||||
/* Write Mode register macro */
|
||||
#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))
|
||||
|
||||
/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */
|
||||
#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
|
||||
#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000)
|
||||
|
||||
#define EMC_CLK_DLY_TIM_2 (0x7777) /* 3.5 ns delay for the EMC clock out */
|
||||
#define EMC_CLK_DLY_TIM_0 (0x0000) /* No delay for the EMC clock out */
|
||||
|
||||
typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg);
|
||||
|
||||
const uint16_t emcdivby2_opc[] = {
|
||||
0x6803, /* LDR R3,[R0,#0] ; Load CREG6 */
|
||||
0xF443,0x3380, /* ORR R3,R3,#0x10000 ; Set Divided by 2 */
|
||||
0x6003, /* STR R3,[R0,#0] ; Store CREG6 */
|
||||
0x600A, /* STR R2,[R1,#0] ; EMCDIV_CFG = cfg */
|
||||
0x684B, /* loop LDR R3,[R1,#4] ; Load EMCDIV_STAT */
|
||||
0x07DB, /* LSLS R3,R3,#31 ; Check EMCDIV_STAT.0 */
|
||||
0xD0FC, /* BEQ loop ; Jump if 0 */
|
||||
0x4770, /* BX LR ; Exit */
|
||||
0,
|
||||
};
|
||||
|
||||
#define emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4)
|
||||
#define emcdivby2_ram 0x10000000
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Initialize external memory controller
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
void SystemInit_ExtMemCtl (void) {
|
||||
uint32_t emcdivby2_buf[emcdivby2_szw];
|
||||
uint32_t div, n;
|
||||
|
||||
/* Select and enable EMC branch clock */
|
||||
LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1;
|
||||
while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1));
|
||||
|
||||
/* Set EMC clock output delay */
|
||||
if (SystemCoreClock < 80000000UL) {
|
||||
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay */
|
||||
}
|
||||
else {
|
||||
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay */
|
||||
}
|
||||
|
||||
/* Configure EMC port pins */
|
||||
LPC_SCU->SFSP1_0 = EMC_PIN_SET | 2; /* P1_0: A5 */
|
||||
LPC_SCU->SFSP1_1 = EMC_PIN_SET | 2; /* P1_1: A6 */
|
||||
LPC_SCU->SFSP1_2 = EMC_PIN_SET | 2; /* P1_2: A7 */
|
||||
LPC_SCU->SFSP1_3 = EMC_PIN_SET | 3; /* P1_3: OE */
|
||||
LPC_SCU->SFSP1_4 = EMC_PIN_SET | 3; /* P1_4: BLS0 */
|
||||
LPC_SCU->SFSP1_5 = EMC_PIN_SET | 3; /* P1_5: CS0 */
|
||||
LPC_SCU->SFSP1_6 = EMC_PIN_SET | 3; /* P1_6: WE */
|
||||
LPC_SCU->SFSP1_7 = EMC_PIN_SET | 3; /* P1_7: D0 */
|
||||
LPC_SCU->SFSP1_8 = EMC_PIN_SET | 3; /* P1_8: D1 */
|
||||
LPC_SCU->SFSP1_9 = EMC_PIN_SET | 3; /* P1_9: D2 */
|
||||
LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3; /* P1_10: D3 */
|
||||
LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3; /* P1_11: D4 */
|
||||
LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3; /* P1_12: D5 */
|
||||
LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3; /* P1_13: D6 */
|
||||
LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3; /* P1_14: D7 */
|
||||
|
||||
LPC_SCU->SFSP2_0 = EMC_PIN_SET | 2; /* P2_0: A13 */
|
||||
LPC_SCU->SFSP2_1 = EMC_PIN_SET | 2; /* P2_1: A12 */
|
||||
LPC_SCU->SFSP2_2 = EMC_PIN_SET | 2; /* P2_2: A11 */
|
||||
LPC_SCU->SFSP2_6 = EMC_PIN_SET | 2; /* P2_6: A10 */
|
||||
LPC_SCU->SFSP2_7 = EMC_PIN_SET | 3; /* P2_7: A9 */
|
||||
LPC_SCU->SFSP2_8 = EMC_PIN_SET | 3; /* P2_8: A8 */
|
||||
LPC_SCU->SFSP2_9 = EMC_PIN_SET | 3; /* P2_9: A0 */
|
||||
LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3; /* P2_10: A1 */
|
||||
LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3; /* P2_11: A2 */
|
||||
LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3; /* P2_12: A3 */
|
||||
LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3; /* P2_13: A4 */
|
||||
|
||||
LPC_SCU->SFSP5_0 = EMC_PIN_SET | 2; /* P5_0: D12 */
|
||||
LPC_SCU->SFSP5_1 = EMC_PIN_SET | 2; /* P5_1: D13 */
|
||||
LPC_SCU->SFSP5_2 = EMC_PIN_SET | 2; /* P5_2: D14 */
|
||||
LPC_SCU->SFSP5_3 = EMC_PIN_SET | 2; /* P5_3: D15 */
|
||||
LPC_SCU->SFSP5_4 = EMC_PIN_SET | 2; /* P5_4: D8 */
|
||||
LPC_SCU->SFSP5_5 = EMC_PIN_SET | 2; /* P5_5: D9 */
|
||||
LPC_SCU->SFSP5_6 = EMC_PIN_SET | 2; /* P5_6: D10 */
|
||||
LPC_SCU->SFSP5_7 = EMC_PIN_SET | 2; /* P5_7: D11 */
|
||||
|
||||
LPC_SCU->SFSP6_1 = EMC_PIN_SET | 1; /* P6_1: DYCS1 */
|
||||
LPC_SCU->SFSP6_2 = EMC_PIN_SET | 1; /* P6_3: CKEOUT1 */
|
||||
LPC_SCU->SFSP6_3 = EMC_PIN_SET | 3; /* P6_3: CS1 */
|
||||
LPC_SCU->SFSP6_4 = EMC_PIN_SET | 3; /* P6_4: CAS */
|
||||
LPC_SCU->SFSP6_5 = EMC_PIN_SET | 3; /* P6_5: RAS */
|
||||
LPC_SCU->SFSP6_6 = EMC_PIN_SET | 1; /* P6_6: BLS1 */
|
||||
LPC_SCU->SFSP6_7 = EMC_PIN_SET | 1; /* P6_7: A15 */
|
||||
LPC_SCU->SFSP6_8 = EMC_PIN_SET | 1; /* P6_8: A14 */
|
||||
LPC_SCU->SFSP6_9 = EMC_PIN_SET | 3; /* P6_9: DYCS0 */
|
||||
LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3; /* P6_10: DQMOUT1 */
|
||||
LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3; /* P6_11: CKEOUT0 */
|
||||
LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3; /* P6_12: DQMOUT0 */
|
||||
|
||||
LPC_SCU->SFSPA_4 = EMC_PIN_SET | 3; /* PA_4: A23 */
|
||||
|
||||
LPC_SCU->SFSPD_0 = EMC_PIN_SET | 2; /* PD_0: DQMOUT2 */
|
||||
LPC_SCU->SFSPD_1 = EMC_PIN_SET | 2; /* PD_1: CKEOUT2 */
|
||||
LPC_SCU->SFSPD_2 = EMC_PIN_SET | 2; /* PD_2: D16 */
|
||||
LPC_SCU->SFSPD_3 = EMC_PIN_SET | 2; /* PD_3: D17 */
|
||||
LPC_SCU->SFSPD_4 = EMC_PIN_SET | 2; /* PD_4: D18 */
|
||||
LPC_SCU->SFSPD_5 = EMC_PIN_SET | 2; /* PD_5: D19 */
|
||||
LPC_SCU->SFSPD_6 = EMC_PIN_SET | 2; /* PD_6: D20 */
|
||||
LPC_SCU->SFSPD_7 = EMC_PIN_SET | 2; /* PD_7: D21 */
|
||||
LPC_SCU->SFSPD_8 = EMC_PIN_SET | 2; /* PD_8: D22 */
|
||||
LPC_SCU->SFSPD_9 = EMC_PIN_SET | 2; /* PD_9: D23 */
|
||||
LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2; /* PD_10: BLS3 */
|
||||
LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2; /* PD_11: CS3 */
|
||||
LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2; /* PD_12: CS2 */
|
||||
LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2; /* PD_13: BLS2 */
|
||||
LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2; /* PD_14: DYCS2 */
|
||||
LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2; /* PD_15: A17 */
|
||||
LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2; /* PD_16: A16 */
|
||||
|
||||
LPC_SCU->SFSPE_0 = EMC_PIN_SET | 3; /* PE_0: A18 */
|
||||
LPC_SCU->SFSPE_1 = EMC_PIN_SET | 3; /* PE_1: A19 */
|
||||
LPC_SCU->SFSPE_2 = EMC_PIN_SET | 3; /* PE_2: A20 */
|
||||
LPC_SCU->SFSPE_3 = EMC_PIN_SET | 3; /* PE_3: A21 */
|
||||
LPC_SCU->SFSPE_4 = EMC_PIN_SET | 3; /* PE_4: A22 */
|
||||
LPC_SCU->SFSPE_5 = EMC_PIN_SET | 3; /* PE_5: D24 */
|
||||
LPC_SCU->SFSPE_6 = EMC_PIN_SET | 3; /* PE_6: D25 */
|
||||
LPC_SCU->SFSPE_7 = EMC_PIN_SET | 3; /* PE_7: D26 */
|
||||
LPC_SCU->SFSPE_8 = EMC_PIN_SET | 3; /* PE_8: D27 */
|
||||
LPC_SCU->SFSPE_9 = EMC_PIN_SET | 3; /* PE_9: D28 */
|
||||
LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3; /* PE_10: D29 */
|
||||
LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3; /* PE_11: D30 */
|
||||
LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3; /* PE_12: D31 */
|
||||
LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3; /* PE_13: DQMOUT3 */
|
||||
LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3; /* PE_14: DYCS3 */
|
||||
LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3; /* PE_15: CKEOUT3 */
|
||||
|
||||
LPC_EMC->CONTROL = 0x00000001; /* EMC Enable */
|
||||
LPC_EMC->CONFIG = 0x00000000; /* Little-endian, Clock Ratio 1:1 */
|
||||
|
||||
div = 0;
|
||||
if (SystemCoreClock > 120000000UL) {
|
||||
/* Use EMC clock divider and EMC clock output delay */
|
||||
div = 1;
|
||||
/* Following code must be executed in RAM to ensure stable operation */
|
||||
/* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1; */
|
||||
/* LPC_CREG->CREG6 |= (1 << 16); // EMC_CLK_DIV divided by 2 */
|
||||
/* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1)); */
|
||||
|
||||
/* This code configures EMC clock divider and is executed in RAM */
|
||||
for (n = 0; n < emcdivby2_szw; n++) {
|
||||
emcdivby2_buf[n] = *((uint32_t *)emcdivby2_ram + n);
|
||||
*((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
|
||||
}
|
||||
__ISB();
|
||||
((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
|
||||
for (n = 0; n < emcdivby2_szw; n++) {
|
||||
*((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure EMC clock-out pins */
|
||||
LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0; /* CLK0 */
|
||||
LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0; /* CLK1 */
|
||||
LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0; /* CLK2 */
|
||||
LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0; /* CLK3 */
|
||||
|
||||
/* Static memory configuration (chip select 0) */
|
||||
#if (USE_EXT_STAT_MEM_CS0)
|
||||
LPC_EMC->STATICCONFIG0 = (1 << 7) | /* Byte lane state: use WE signal */
|
||||
(2 << 0) | /* Memory width 32-bit */
|
||||
(1 << 3); /* Async page mode enable */
|
||||
|
||||
LPC_EMC->STATICWAITOEN0 = (0 << 0) ; /* Wait output enable: No delay */
|
||||
|
||||
LPC_EMC->STATICWAITPAGE0 = 2;
|
||||
|
||||
/* Set Static Memory Read Delay for 90ns External NOR Flash */
|
||||
LPC_EMC->STATICWAITRD0 = 1 + EMC_NANOSEC(90, SystemCoreClock, div);
|
||||
LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer */
|
||||
#endif
|
||||
|
||||
/* Dynamic memory configuration (chip select 0) */
|
||||
#if (USE_EXT_DYN_MEM_CS0)
|
||||
|
||||
/* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
|
||||
LPC_EMC->DYNAMICCONFIG0 = (1 << 14) | /* AM[14] = 1 */
|
||||
(0 << 12) | /* AM[12] = 0 */
|
||||
(2 << 9) | /* AM[11:9] = 2 */
|
||||
(2 << 7) ; /* AM[8:7] = 2 */
|
||||
|
||||
LPC_EMC->DYNAMICRASCAS0 = 0x00000303; /* Latency: RAS 3, CAS 3 CCLK cyc.*/
|
||||
LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed by 1/2 CCLK */
|
||||
|
||||
LPC_EMC->DYNAMICRP = EMC_NANOSEC (20, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICRAS = EMC_NANOSEC (42, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICSREX = EMC_NANOSEC (63, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICAPR = EMC_NANOSEC (70, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICDAL = EMC_NANOSEC (70, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICWR = EMC_NANOSEC (30, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICRC = EMC_NANOSEC (63, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICRFC = EMC_NANOSEC (63, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICXSR = EMC_NANOSEC (63, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICRRD = EMC_NANOSEC (14, SystemCoreClock, div);
|
||||
LPC_EMC->DYNAMICMRD = EMC_NANOSEC (30, SystemCoreClock, div);
|
||||
|
||||
WaitUs (100);
|
||||
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
|
||||
WaitUs (10);
|
||||
LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */
|
||||
WaitUs (1);
|
||||
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
|
||||
WaitUs (1);
|
||||
LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC( 200, SystemCoreClock, div) / 16 + 1;
|
||||
WaitUs (10);
|
||||
LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
|
||||
WaitUs (10);
|
||||
LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */
|
||||
|
||||
/* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3 */
|
||||
WR_MODE(((3 << 4) | 2) << 12);
|
||||
|
||||
WaitUs (10);
|
||||
LPC_EMC->DYNAMICCONTROL = 0x00000002; /* Issue NORMAL command */
|
||||
LPC_EMC->DYNAMICCONFIG0 |= (1 << 19); /* Enable buffer */
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Measure frequency using frequency monitor
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t MeasureFreq (uint32_t clk_sel) {
|
||||
uint32_t fcnt, rcnt, fout;
|
||||
|
||||
/* Set register values */
|
||||
LPC_CGU->FREQ_MON &= ~(1 << 23); /* Stop frequency counters */
|
||||
LPC_CGU->FREQ_MON = (clk_sel << 24) | 511; /* RCNT == 511 */
|
||||
LPC_CGU->FREQ_MON |= (1 << 23); /* Start RCNT and FCNT */
|
||||
while (LPC_CGU->FREQ_MON & (1 << 23)) {
|
||||
fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
|
||||
rcnt = (LPC_CGU->FREQ_MON ) & 0x01FF;
|
||||
if (fcnt == 0 && rcnt == 0) {
|
||||
return (0); /* No input clock present */
|
||||
}
|
||||
}
|
||||
fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
|
||||
fout = fcnt * (12000000U/511U); /* FCNT * (IRC_CLK / RCNT) */
|
||||
|
||||
return (fout);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Get PLL1 (divider and multiplier) parameters
|
||||
*----------------------------------------------------------------------------*/
|
||||
__inline uint32_t GetPLL1Param (void) {
|
||||
uint32_t ctrl;
|
||||
uint32_t p;
|
||||
uint32_t div, mul;
|
||||
|
||||
ctrl = LPC_CGU->PLL1_CTRL;
|
||||
div = ((ctrl >> 12) & 0x03) + 1;
|
||||
mul = ((ctrl >> 16) & 0xFF) + 1;
|
||||
p = 1 << ((ctrl >> 8) & 0x03);
|
||||
|
||||
if (ctrl & (1 << 1)) {
|
||||
/* Bypass = 1, PLL1 input clock sent to post-dividers */
|
||||
if (ctrl & (1 << 7)) {
|
||||
div *= (2*p);
|
||||
}
|
||||
}
|
||||
else {
|
||||
/* Direct and integer mode */
|
||||
if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) {
|
||||
/* Non-integer mode */
|
||||
div *= (2*p);
|
||||
}
|
||||
}
|
||||
return ((div << 8) | (mul));
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Get input clock source for specified clock generation block
|
||||
*----------------------------------------------------------------------------*/
|
||||
int32_t GetClkSel (uint32_t clk_src) {
|
||||
uint32_t reg;
|
||||
int32_t clk_sel = -1;
|
||||
|
||||
switch (clk_src) {
|
||||
case CLK_SRC_IRC:
|
||||
case CLK_SRC_ENET_RX:
|
||||
case CLK_SRC_ENET_TX:
|
||||
case CLK_SRC_GP_CLKIN:
|
||||
return (clk_src);
|
||||
|
||||
case CLK_SRC_32KHZ:
|
||||
return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ);
|
||||
case CLK_SRC_XTAL:
|
||||
return (LPC_CGU->XTAL_OSC_CTRL & 1) ? (-1) : (CLK_SRC_XTAL);
|
||||
|
||||
case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL; break;
|
||||
case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL; break;
|
||||
case CLK_SRC_PLL1: reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break;
|
||||
|
||||
case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL; break;
|
||||
case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL; break;
|
||||
case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL; break;
|
||||
case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL; break;
|
||||
case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL; break;
|
||||
|
||||
default:
|
||||
return (clk_sel);
|
||||
}
|
||||
if (!(reg & 1)) {
|
||||
clk_sel = (reg >> 24) & 0x1F;
|
||||
}
|
||||
return (clk_sel);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Get clock frequency for specified clock source
|
||||
*----------------------------------------------------------------------------*/
|
||||
uint32_t GetClockFreq (uint32_t clk_src) {
|
||||
uint32_t tmp;
|
||||
uint32_t mul = 1;
|
||||
uint32_t div = 1;
|
||||
uint32_t main_freq = 0;
|
||||
int32_t clk_sel = clk_src;
|
||||
|
||||
do {
|
||||
switch (clk_sel) {
|
||||
case CLK_SRC_32KHZ: main_freq = CLK_32KHZ; break;
|
||||
case CLK_SRC_IRC: main_freq = CLK_IRC; break;
|
||||
case CLK_SRC_ENET_RX: main_freq = CLK_ENET_RX; break;
|
||||
case CLK_SRC_ENET_TX: main_freq = CLK_ENET_TX; break;
|
||||
case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN; break;
|
||||
case CLK_SRC_XTAL: main_freq = CLK_XTAL; break;
|
||||
|
||||
case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x03) + 1; break;
|
||||
case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x0F) + 1; break;
|
||||
case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x0F) + 1; break;
|
||||
case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x0F) + 1; break;
|
||||
case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0xFF) + 1; break;
|
||||
|
||||
case CLK_SRC_PLL0U: /* Not implemented */ break;
|
||||
case CLK_SRC_PLL0A: /* Not implemented */ break;
|
||||
|
||||
case CLK_SRC_PLL1:
|
||||
tmp = GetPLL1Param ();
|
||||
mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */
|
||||
div *= (tmp >> 8) & 0xFF; /* PLL input clock divider */
|
||||
break;
|
||||
|
||||
default:
|
||||
return (0); /* Clock not running or not supported */
|
||||
}
|
||||
if (main_freq == 0) {
|
||||
clk_sel = GetClkSel (clk_sel);
|
||||
}
|
||||
}
|
||||
while (main_freq == 0);
|
||||
|
||||
return ((main_freq * mul) / div);
|
||||
}
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
System Core Clock update
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemCoreClockUpdate (void) {
|
||||
/* Check BASE_M4_CLK connection */
|
||||
uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F;
|
||||
|
||||
/* Update core clock frequency */
|
||||
SystemCoreClock = GetClockFreq (base_src);
|
||||
}
|
||||
|
||||
|
||||
extern uint32_t __Vectors; /* see startup_LPC43xx.s */
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
Initialize the system
|
||||
*----------------------------------------------------------------------------*/
|
||||
void SystemInit (void) {
|
||||
|
||||
#if (__FPU_USED == 1)
|
||||
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
|
||||
(3UL << 11*2) ); /* set CP11 Full Access */
|
||||
#endif
|
||||
|
||||
/* Stop CM0 core */
|
||||
LPC_RGU->RESET_CTRL1 = (1 << 24);
|
||||
|
||||
/* Disable SysTick timer */
|
||||
SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
|
||||
|
||||
/* Set vector table pointer */
|
||||
SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL;
|
||||
|
||||
/* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
|
||||
SetClock();
|
||||
|
||||
/* Update SystemCoreClock variable */
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
/* Configure External Memory Controller */
|
||||
//SystemInit_ExtMemCtl ();
|
||||
}
|
||||
+25
@@ -0,0 +1,25 @@
|
||||
|
||||
/*
|
||||
* Auto generated Run-Time-Environment Component Configuration File
|
||||
* *** Do not modify ! ***
|
||||
*
|
||||
* Project: 'CMSIS_DAP'
|
||||
* Target: 'LPC4320 SPIFI'
|
||||
*/
|
||||
|
||||
#ifndef RTE_COMPONENTS_H
|
||||
#define RTE_COMPONENTS_H
|
||||
|
||||
#define RTE_CMSIS_RTOS /* CMSIS-RTOS */
|
||||
#define RTE_CMSIS_RTOS_RTX /* CMSIS-RTOS Keil RTX */
|
||||
#define RTE_DEVICE_STARTUP_LPC43XX /* Device Startup for NXP43XX */
|
||||
#define RTE_Drivers_USART0 /* Driver USART0 */
|
||||
#define RTE_Drivers_USART1 /* Driver USART1 */
|
||||
#define RTE_Drivers_USART2 /* Driver USART2 */
|
||||
#define RTE_Drivers_USART3 /* Driver USART3 */
|
||||
#define RTE_Drivers_USBD0 /* Driver USBD0 */
|
||||
#define RTE_USB_Core /* USB Core */
|
||||
#define RTE_USB_Device_0 /* USB Device 0 */
|
||||
#define RTE_USB_Device_HID_0 /* USB Device HID instance 0 */
|
||||
|
||||
#endif /* RTE_COMPONENTS_H */
|
||||
+171
@@ -0,0 +1,171 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::USB:Device
|
||||
* Copyright (c) 2004-2014 ARM Germany GmbH. All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: USBD_Config_0.c
|
||||
* Purpose: USB Device Configuration
|
||||
* Rev.: V5.00
|
||||
*------------------------------------------------------------------------------
|
||||
* Use the following configuration settings in the Device Class configuration
|
||||
* files to assign a Device Class to this USB Device 0.
|
||||
*
|
||||
* Configuration Setting Value
|
||||
* --------------------- -----
|
||||
* Assign Device Class to USB Device # = 0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>USB Device 0
|
||||
// <o>Connect to hardware via Driver_USBD# <0-255>
|
||||
// <i>Select driver control block for hardware interface.
|
||||
#define USBD0_PORT 0
|
||||
|
||||
// <o.0>High-speed
|
||||
// <i>Enable High-speed functionality (if device supports it).
|
||||
#define USBD0_HS 1
|
||||
|
||||
// <h>Device Settings
|
||||
// <i>These settings are used to create the Device Descriptor
|
||||
// <o>Max Endpoint 0 Packet Size
|
||||
// <i>Maximum packet size for Endpoint 0 (bMaxPacketSize0).
|
||||
// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes
|
||||
#define USBD0_MAX_PACKET0 64
|
||||
|
||||
// <o.0..15>Vendor ID <0x0000-0xFFFF>
|
||||
// <i>Vendor ID assigned by USB-IF (idVendor).
|
||||
#define USBD0_DEV_DESC_IDVENDOR 0xC251
|
||||
|
||||
// <o.0..15>Product ID <0x0000-0xFFFF>
|
||||
// <i>Product ID assigned by manufacturer (idProduct).
|
||||
#define USBD0_DEV_DESC_IDPRODUCT 0xF001
|
||||
|
||||
// <o.0..15>Device Release Number <0x0000-0xFFFF>
|
||||
// <i>Device Release Number in binary-coded decimal (bcdDevice)
|
||||
#define USBD0_DEV_DESC_BCDDEVICE 0x0100
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Configuration Settings
|
||||
// <i>These settings are used to create the Configuration Descriptor.
|
||||
// <o.6>Power
|
||||
// <i>Default Power Setting (D6: of bmAttributes).
|
||||
// <0=>Bus-powered
|
||||
// <1=>Self-powered
|
||||
// <o.5>Remote Wakeup
|
||||
// <i>Configuration support for Remote Wakeup (D5: of bmAttributes).
|
||||
#define USBD0_CFG_DESC_BMATTRIBUTES 0x80
|
||||
|
||||
// <o.0..7>Maximum Power Consumption (in mA) <0-510><#/2>
|
||||
// <i>Maximum Power Consumption of USB Device from bus in this
|
||||
// <i>specific configuration when device is fully operational (bMaxPower).
|
||||
#define USBD0_CFG_DESC_BMAXPOWER 250
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>String Settings
|
||||
// <i>These settings are used to create the String Descriptor.
|
||||
// <o.0..15>Language ID <0x0000-0xFCFF>
|
||||
// <i>English (United States) = 0x0409.
|
||||
#define USBD0_STR_DESC_LANGID 0x0409
|
||||
|
||||
// <s.126>Manufacturer String
|
||||
// <i>String Descriptor describing Manufacturer.
|
||||
#define USBD0_STR_DESC_MAN L"KEIL - Tools By ARM"
|
||||
|
||||
// <s.126>Product String
|
||||
// <i>String Descriptor describing Product.
|
||||
#define USBD0_STR_DESC_PROD L"LPC-Link-II CMSIS-DAP"
|
||||
|
||||
// <e.0>Serial Number
|
||||
// <i>Enable Serial Number String.
|
||||
// <i>If disabled Serial Number String will not be assigned to USB Device.
|
||||
#define USBD0_STR_DESC_SER_EN 1
|
||||
|
||||
// <s.126>Serial Number String
|
||||
// <i>String Descriptor describing device's Serial Number.
|
||||
#define USBD0_STR_DESC_SER L"0001A0000000"
|
||||
|
||||
// </e>
|
||||
// </h>
|
||||
|
||||
// <h>OS Resources Settings
|
||||
// <i>These settings are used to optimize usage of OS resources.
|
||||
// <o>Core Thread Stack Size <64-65536>
|
||||
#define USBD0_CORE_THREAD_STACK_SIZE 512
|
||||
|
||||
// Core Thread Priority
|
||||
#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
|
||||
#include "..\RTE_Components.h"
|
||||
|
||||
#ifdef RTE_USB_Device_CustomClass_0
|
||||
#include "USBD_Config_CustomClass_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CustomClass_1
|
||||
#include "USBD_Config_CustomClass_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CustomClass_2
|
||||
#include "USBD_Config_CustomClass_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CustomClass_3
|
||||
#include "USBD_Config_CustomClass_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_HID_0
|
||||
#include "USBD_Config_HID_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_HID_1
|
||||
#include "USBD_Config_HID_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_HID_2
|
||||
#include "USBD_Config_HID_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_HID_3
|
||||
#include "USBD_Config_HID_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_MSC_0
|
||||
#include "USBD_Config_MSC_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_MSC_1
|
||||
#include "USBD_Config_MSC_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_MSC_2
|
||||
#include "USBD_Config_MSC_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_MSC_3
|
||||
#include "USBD_Config_MSC_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_CDC_0
|
||||
#include "USBD_Config_CDC_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_1
|
||||
#include "USBD_Config_CDC_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_2
|
||||
#include "USBD_Config_CDC_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_3
|
||||
#include "USBD_Config_CDC_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_ADC_0
|
||||
#include "USBD_Config_ADC_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_ADC_1
|
||||
#include "USBD_Config_ADC_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_ADC_2
|
||||
#include "USBD_Config_ADC_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_ADC_3
|
||||
#include "USBD_Config_ADC_3.h"
|
||||
#endif
|
||||
|
||||
#include "usbd_config.h"
|
||||
+171
@@ -0,0 +1,171 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::USB:Device
|
||||
* Copyright (c) 2004-2015 ARM Germany GmbH. All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: USBD_Config_HID_0.h
|
||||
* Purpose: USB Device Human Interface Device class (HID) Configuration
|
||||
* Rev.: V5.0.1
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>USB Device: Human Interface Device class (HID) 0
|
||||
// <o>Assign Device Class to USB Device # <0-3>
|
||||
// <i>Select USB Device that is used for this Device Class instance
|
||||
#define USBD_HID0_DEV 0
|
||||
|
||||
// <h>Interrupt Endpoint Settings
|
||||
// <i>By default, the settings match the first USB Class instance in a USB Device.
|
||||
// <i>Endpoint conflicts are flagged by compile-time error messages.
|
||||
//
|
||||
// <h>Interrupt IN Endpoint Settings
|
||||
// <o.0..3>Interrupt IN Endpoint Number
|
||||
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
|
||||
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
|
||||
#define USBD_HID0_EP_INT_IN 1
|
||||
|
||||
// <h>Endpoint Settings
|
||||
// <i>Parameters are used to create USB Descriptors, HID Device Descriptor
|
||||
// <i>and for memory allocation in the USB component.
|
||||
//
|
||||
// <h>Full/Low-speed (High-speed disabled)
|
||||
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
|
||||
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 64.
|
||||
#define USBD_HID0_EP_INT_IN_WMAXPACKETSIZE 64
|
||||
|
||||
// <o.0..7>Endpoint polling Interval (in ms) <1-255>
|
||||
// <i>Specifies the frequency of requests initiated by USB Host for
|
||||
// <i>function USBD_HIDn_GetReport.
|
||||
#define USBD_HID0_EP_INT_IN_BINTERVAL 1
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>High-speed
|
||||
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
|
||||
//
|
||||
// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 1024.
|
||||
// <o.11..12>Additional transactions per microframe
|
||||
// <i>Additional transactions improve communication performance.
|
||||
// <0=>None <1=>1 additional <2=>2 additional
|
||||
#define USBD_HID0_EP_INT_IN_HS_WMAXPACKETSIZE 64
|
||||
|
||||
// <o.0..4>Endpoint polling Interval (in 125 us intervals)
|
||||
// <i>Specifies the frequency of requests initiated by USB Host for
|
||||
// <i>function USBD_HIDn_GetReport.
|
||||
// <1=> 1 <2=> 2 <3=> 4 <4=> 8
|
||||
// <5=> 16 <6=> 32 <7=> 64 <8=> 128
|
||||
// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
|
||||
// <13=>4096 <14=>8192 <15=>16384 <16=>32768
|
||||
#define USBD_HID0_EP_INT_IN_HS_BINTERVAL 1
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
// <h>Interrupt OUT Endpoint Settings
|
||||
// <o.0..3>Interrupt OUT Endpoint Number
|
||||
// <i>When OUT Endpoint is set to "Not used" the USB Host uses
|
||||
// <i>the Control Endpoint 0 for Out Reports.
|
||||
// <0=>Not used
|
||||
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
|
||||
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
|
||||
#define USBD_HID0_EP_INT_OUT 1
|
||||
|
||||
// <h>Endpoint Settings
|
||||
// <i>Parameters are used to create USB Descriptors, HID Device Descriptor
|
||||
// <i>and for memory allocation in the USB component.
|
||||
//
|
||||
// <h>Full/Low-speed (High-speed disabled)
|
||||
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
|
||||
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 64.
|
||||
#define USBD_HID0_EP_INT_OUT_WMAXPACKETSIZE 64
|
||||
|
||||
// <o.0..7>Endpoint polling Interval (in ms) <1-255>
|
||||
// <i>Specifies the frequency of requests initiated by USB Host for
|
||||
// <i>function USBD_HIDn_GetReport.
|
||||
#define USBD_HID0_EP_INT_OUT_BINTERVAL 1
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>High-speed
|
||||
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
|
||||
//
|
||||
// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 1024.
|
||||
// <o.11..12>Additional transactions per microframe
|
||||
// <i>Additional transactions improve communication performance.
|
||||
// <0=>None <1=>1 additional <2=>2 additional
|
||||
#define USBD_HID0_EP_INT_OUT_HS_WMAXPACKETSIZE 64
|
||||
|
||||
// <o.0..4>Endpoint polling Interval (in 125 us intervals)
|
||||
// <i>Specifies the frequency of requests initiated by USB Host for
|
||||
// <i>function USBD_HIDn_GetReport.
|
||||
// <1=> 1 <2=> 2 <3=> 4 <4=> 8
|
||||
// <5=> 16 <6=> 32 <7=> 64 <8=> 128
|
||||
// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
|
||||
// <13=>4096 <14=>8192 <15=>16384 <16=>32768
|
||||
#define USBD_HID0_EP_INT_OUT_HS_BINTERVAL 1
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
// <h>Human Interface Device Class Settings
|
||||
// <i>Parameters are used to create USB Descriptors, USB HID Report Descriptor
|
||||
// <i>and for memory allocation in the USB component.
|
||||
//
|
||||
// <s.126>HID Interface String
|
||||
#define USBD_HID0_STR_DESC L"LPC-Link-II CMSIS-DAP"
|
||||
|
||||
// <o.0..4>Number of Input Reports <1-32>
|
||||
// <i>Configures max 'rid' value for USBD_HID0_GetReport and USBD_HID_GetReportTrigger
|
||||
#define USBD_HID0_IN_REPORT_NUM 1
|
||||
|
||||
// <o.0..4>Number of Output Reports <1-32>
|
||||
// <i>Configures max 'rid' value for USBD_HID0_SetReport
|
||||
#define USBD_HID0_OUT_REPORT_NUM 1
|
||||
|
||||
// <o.0..15>Maximum Input Report Size (in bytes) <1-65535>
|
||||
// <i>Allocates memory and configures 'len' value for USBD_HID0_GetReport
|
||||
// <i>and USBD_HID_GetReportTrigger
|
||||
#define USBD_HID0_IN_REPORT_MAX_SZ 1024
|
||||
|
||||
// <o.0..15>Maximum Output Report Size (in bytes) <1-65535>
|
||||
// <i>Allocates memory and configures 'len' value for USBD_HID0_SetReport
|
||||
// <i>when rtype=HID_REPORT_OUTPUT.
|
||||
#define USBD_HID0_OUT_REPORT_MAX_SZ 1024
|
||||
|
||||
// <o.0..15>Maximum Feature Report Size (in bytes) <1-65535>
|
||||
// <i>Allocates memory and configures 'len' value for USBD_HID0_SetReport
|
||||
// <i>when rtype=HID_REPORT_FEATURE
|
||||
#define USBD_HID0_FEAT_REPORT_MAX_SZ 1
|
||||
|
||||
// <e.0>Use User Provided HID Report Descriptor
|
||||
// <i>User needs to provide HID Report Descriptor in array
|
||||
// <i>const uint8_t usbd_hid0_report_descriptor[]
|
||||
#define USBD_HID0_USER_REPORT_DESCRIPTOR 0
|
||||
|
||||
// <o>User Provided HID Report Descriptor Size (in bytes) <1-65535>
|
||||
#define USBD_HID0_USER_REPORT_DESCRIPTOR_SIZE 33
|
||||
|
||||
// </e>
|
||||
// </h>
|
||||
|
||||
// <h>OS Resources Settings
|
||||
// <i>These settings are used to optimize usage of OS resources.
|
||||
// <o>Human Interface Device Class Thread Stack Size <64-65536>
|
||||
#define USBD_HID0_THREAD_STACK_SIZE 512
|
||||
|
||||
// Human Interface Device Class Thread Priority
|
||||
#define USBD_HID0_THREAD_PRIORITY osPriorityAboveNormal
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
+237
@@ -0,0 +1,237 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::USB:Device
|
||||
* Copyright (c) 2004-2014 ARM Germany GmbH. All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: USBD_User_HID_0.c
|
||||
* Purpose: USB Device Human Interface Device class (HID) User module
|
||||
* Rev.: V6.2
|
||||
*----------------------------------------------------------------------------*/
|
||||
/**
|
||||
* \addtogroup usbd_hidFunctions
|
||||
*
|
||||
* USBD_User_HID_0.c implements the application specific functionality of the
|
||||
* HID class and is used to receive and send data reports to the USB Host.
|
||||
*
|
||||
* The implementation must match the configuration file USBD_Config_HID_0.h.
|
||||
* The following values in USBD_Config_HID_0.h affect the user code:
|
||||
*
|
||||
* - 'Endpoint polling Interval' specifies the frequency of requests
|
||||
* initiated by USB Host for \ref USBD_HIDn_GetReport.
|
||||
*
|
||||
* - 'Number of Output Reports' configures the values for \em rid of
|
||||
* \ref USBD_HIDn_SetReport.
|
||||
*
|
||||
* - 'Number of Input Reports' configures the values for \em rid of
|
||||
* \ref USBD_HIDn_GetReport and \ref USBD_HID_GetReportTrigger.
|
||||
*
|
||||
* - 'Maximum Input Report Size' specifies the maximum value for:
|
||||
* - return of \ref USBD_HIDn_GetReport
|
||||
* - len of \ref USBD_HID_GetReportTrigger.
|
||||
*
|
||||
* - 'Maximum Output Report Size' specifies the maximum value for \em len
|
||||
* in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_OUTPUT
|
||||
*
|
||||
* - 'Maximum Feature Report Size' specifies the maximum value for \em len
|
||||
* in \ref USBD_HIDn_SetReport for rtype=HID_REPORT_FEATURE
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
//! [code_USBD_User_HID]
|
||||
|
||||
#include <string.h>
|
||||
#define osObjectsExternal
|
||||
#include "cmsis_os.h"
|
||||
#include "osObjects.h"
|
||||
#include "rl_usb.h"
|
||||
#include "USB\USBD_Config_HID_0.h"
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
|
||||
|
||||
#if (USBD_HID0_OUT_REPORT_MAX_SZ != DAP_PACKET_SIZE)
|
||||
#error "USB HID0 Output Report Size must match DAP Packet Size"
|
||||
#endif
|
||||
#if (USBD_HID0_IN_REPORT_MAX_SZ != DAP_PACKET_SIZE)
|
||||
#error "USB HID Input Report Size must match DAP Packet Size"
|
||||
#endif
|
||||
|
||||
static uint16_t USB_RequestIndexI; // Request Index In
|
||||
static uint16_t USB_RequestIndexO; // Request Index Out
|
||||
static uint16_t USB_RequestCountI; // Request Count In
|
||||
static uint16_t USB_RequestCountO; // Request Count Out
|
||||
|
||||
static uint16_t USB_ResponseIndexI; // Response Index In
|
||||
static uint16_t USB_ResponseIndexO; // Response Index Out
|
||||
static uint16_t USB_ResponseCountI; // Response Count In
|
||||
static uint16_t USB_ResponseCountO; // Response Count Out
|
||||
static uint8_t USB_ResponseIdle; // Response Idle Flag
|
||||
|
||||
static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Request Buffer
|
||||
static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Response Buffer
|
||||
|
||||
|
||||
// Called during USBD_Initialize to initialize the USB Device class.
|
||||
void USBD_HID0_Initialize (void) {
|
||||
// Initialize variables
|
||||
USB_RequestIndexI = 0U;
|
||||
USB_RequestIndexO = 0U;
|
||||
USB_RequestCountI = 0U;
|
||||
USB_RequestCountO = 0U;
|
||||
USB_ResponseIndexI = 0U;
|
||||
USB_ResponseIndexO = 0U;
|
||||
USB_ResponseCountI = 0U;
|
||||
USB_ResponseCountO = 0U;
|
||||
USB_ResponseIdle = 1U;
|
||||
}
|
||||
|
||||
|
||||
// Called during USBD_Uninitialize to de-initialize the USB Device class.
|
||||
void USBD_HID0_Uninitialize (void) {
|
||||
}
|
||||
|
||||
|
||||
// \brief Prepare HID Report data to send.
|
||||
// \param[in] rtype report type:
|
||||
// - HID_REPORT_INPUT = input report requested
|
||||
// - HID_REPORT_FEATURE = feature report requested
|
||||
// \param[in] req request type:
|
||||
// - USBD_HID_REQ_EP_CTRL = control endpoint request
|
||||
// - USBD_HID_REQ_PERIOD_UPDATE = idle period expiration request
|
||||
// - USBD_HID_REQ_EP_INT = previously sent report on interrupt endpoint request
|
||||
// \param[in] rid report ID (0 if only one report exists).
|
||||
// \param[out] buf buffer containing report data to send.
|
||||
// \return number of report data bytes prepared to send or invalid report requested.
|
||||
// - value >= 0: number of report data bytes prepared to send
|
||||
// - value = -1: invalid report requested
|
||||
int32_t USBD_HID0_GetReport (uint8_t rtype, uint8_t req, uint8_t rid, uint8_t *buf) {
|
||||
|
||||
switch (rtype) {
|
||||
case HID_REPORT_INPUT:
|
||||
switch (req) {
|
||||
case USBD_HID_REQ_EP_CTRL: // Explicit USB Host request via Control OUT Endpoint
|
||||
case USBD_HID_REQ_PERIOD_UPDATE: // Periodic USB Host request via Interrupt OUT Endpoint
|
||||
break;
|
||||
case USBD_HID_REQ_EP_INT: // Called after USBD_HID_GetReportTrigger to signal data obtained.
|
||||
if (USB_ResponseCountI != USB_ResponseCountO) {
|
||||
// Load data from response buffer to be sent back
|
||||
memcpy(buf, USB_Response[USB_ResponseIndexO], DAP_PACKET_SIZE);
|
||||
USB_ResponseIndexO++;
|
||||
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
|
||||
USB_ResponseIndexO = 0U;
|
||||
}
|
||||
USB_ResponseCountO++;
|
||||
return ((int32_t)DAP_PACKET_SIZE);
|
||||
} else {
|
||||
USB_ResponseIdle = 1U;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case HID_REPORT_FEATURE:
|
||||
break;
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
|
||||
// \brief Process received HID Report data.
|
||||
// \param[in] rtype report type:
|
||||
// - HID_REPORT_OUTPUT = output report received
|
||||
// - HID_REPORT_FEATURE = feature report received
|
||||
// \param[in] req request type:
|
||||
// - USBD_HID_REQ_EP_CTRL = report received on control endpoint
|
||||
// - USBD_HID_REQ_EP_INT = report received on interrupt endpoint
|
||||
// \param[in] rid report ID (0 if only one report exists).
|
||||
// \param[in] buf buffer that receives report data.
|
||||
// \param[in] len length of received report data.
|
||||
// \return true received report data processed.
|
||||
// \return false received report data not processed or request not supported.
|
||||
bool USBD_HID0_SetReport (uint8_t rtype, uint8_t req, uint8_t rid, const uint8_t *buf, int32_t len) {
|
||||
|
||||
switch (rtype) {
|
||||
case HID_REPORT_OUTPUT:
|
||||
if (len == 0) { break; }
|
||||
if (buf[0] == ID_DAP_TransferAbort) {
|
||||
DAP_TransferAbort = 1U;
|
||||
break;
|
||||
}
|
||||
if ((uint16_t)(USB_RequestCountI - USB_RequestCountO) == DAP_PACKET_COUNT) {
|
||||
osSignalSet(HID0_ThreadId, 0x80);
|
||||
break; // Discard packet when buffer is full
|
||||
}
|
||||
// Store received data into request buffer
|
||||
memcpy(USB_Request[USB_RequestIndexI], buf, len);
|
||||
USB_RequestIndexI++;
|
||||
if (USB_RequestIndexI == DAP_PACKET_COUNT) {
|
||||
USB_RequestIndexI = 0U;
|
||||
}
|
||||
USB_RequestCountI++;
|
||||
osSignalSet(HID0_ThreadId, 0x01);
|
||||
break;
|
||||
case HID_REPORT_FEATURE:
|
||||
break;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
// HID0 Thread.
|
||||
void HID0_Thread (void const *arg) {
|
||||
osEvent evt;
|
||||
uint32_t n;
|
||||
|
||||
for (;;) {
|
||||
osSignalWait(0, osWaitForever);
|
||||
|
||||
// Process pending requests
|
||||
while (USB_RequestCountI != USB_RequestCountO) {
|
||||
|
||||
// Handle Queue Commands
|
||||
n = USB_RequestIndexO;
|
||||
while (USB_Request[n][0] == ID_DAP_QueueCommands) {
|
||||
USB_Request[n][0] = ID_DAP_ExecuteCommands;
|
||||
n++;
|
||||
if (n == DAP_PACKET_COUNT) {
|
||||
n = 0U;
|
||||
}
|
||||
if (n == USB_RequestIndexI) {
|
||||
evt = osSignalWait(0, osWaitForever);
|
||||
if (evt.value.signals & 0x80) { break; }
|
||||
}
|
||||
}
|
||||
|
||||
// Execute DAP Command (process request and prepare response)
|
||||
DAP_ExecuteCommand(USB_Request[USB_RequestIndexO], USB_Response[USB_ResponseIndexI]);
|
||||
|
||||
// Update Request Index and Count
|
||||
USB_RequestIndexO++;
|
||||
if (USB_RequestIndexO == DAP_PACKET_COUNT) {
|
||||
USB_RequestIndexO = 0U;
|
||||
}
|
||||
USB_RequestCountO++;
|
||||
|
||||
// Update Response Index and Count
|
||||
USB_ResponseIndexI++;
|
||||
if (USB_ResponseIndexI == DAP_PACKET_COUNT) {
|
||||
USB_ResponseIndexI = 0U;
|
||||
}
|
||||
USB_ResponseCountI++;
|
||||
|
||||
if (USB_ResponseIdle) {
|
||||
if (USB_ResponseCountI != USB_ResponseCountO) {
|
||||
// Load data from response buffer to be sent back
|
||||
n = USB_ResponseIndexO++;
|
||||
if (USB_ResponseIndexO == DAP_PACKET_COUNT) {
|
||||
USB_ResponseIndexO = 0U;
|
||||
}
|
||||
USB_ResponseCountO++;
|
||||
USB_ResponseIdle = 0U;
|
||||
USBD_HID_GetReportTrigger(0U, 0U, USB_Response[n], DAP_PACKET_SIZE);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//! [code_USBD_User_HID]
|
||||
@@ -0,0 +1,50 @@
|
||||
/******************************************************************************
|
||||
* @file main.c
|
||||
* @brief CMSIS-DAP Main module
|
||||
* @version V1.10
|
||||
* @date 20. Jan 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#include "cmsis_os.h"
|
||||
#include "osObjects.h"
|
||||
#include "rl_usb.h"
|
||||
#include "DAP_config.h"
|
||||
#include "DAP.h"
|
||||
|
||||
// Main program
|
||||
int main (void) {
|
||||
|
||||
DAP_Setup(); // DAP Setup
|
||||
|
||||
USBD_Initialize(0U); // USB Device Initialization
|
||||
USBD_Connect(0U); // USB Device Connect
|
||||
|
||||
while (!USBD_Configured(0U)); // Wait for USB Device to configure
|
||||
|
||||
LED_CONNECTED_OUT(1U); // Turn on Debugger Connected LED
|
||||
LED_RUNNING_OUT(1U); // Turn on Target Running LED
|
||||
Delayms(500U); // Wait for 500ms
|
||||
LED_RUNNING_OUT(0U); // Turn off Target Running LED
|
||||
LED_CONNECTED_OUT(0U); // Turn off Debugger Connected LED
|
||||
|
||||
// Create HID Thread
|
||||
HID0_ThreadId = osThreadCreate(osThread(HID0_Thread), NULL);
|
||||
|
||||
osThreadSetPriority(osThreadGetId(), osPriorityIdle);
|
||||
for (;;); // Endless Loop
|
||||
}
|
||||
@@ -0,0 +1,37 @@
|
||||
/******************************************************************************
|
||||
* @file osObjects.h
|
||||
* @brief CMSIS-DAP RTOS Objects
|
||||
* @version V1.10
|
||||
* @date 20. Jan 2015
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2012-2015 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __osObjects_h__
|
||||
#define __osObjects_h__
|
||||
|
||||
#include "cmsis_os.h"
|
||||
|
||||
#ifdef osObjectsExternal
|
||||
extern osThreadId HID0_ThreadId;
|
||||
#else
|
||||
osThreadId HID0_ThreadId;
|
||||
#endif
|
||||
|
||||
extern void HID0_Thread (void const *arg);
|
||||
osThreadDef(HID0_Thread, osPriorityNormal, 1U, 512U);
|
||||
|
||||
#endif /* __osObjects_h__ */
|
||||
Reference in New Issue
Block a user